diff -r dbbbbf113c25 -r 94b72f56b957 configs/example/fs.py --- a/configs/example/fs.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/example/fs.py Tue Oct 21 17:07:58 2014 -0500 @@ -136,6 +136,8 @@ sys.exit(1) Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) + test_sys.physmem = [SimpleMemory(range = r, null = True) + for r in test_sys.mem_ranges] # Create a seperate clock domain for Ruby test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, @@ -160,13 +162,9 @@ cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master - test_sys.ruby._cpu_ports[i].access_phys_mem = True - - # Create the appropriate memory controllers - # and connect them to the IO bus - test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] - for i in xrange(len(test_sys.mem_ctrls)): - test_sys.mem_ctrls[i].port = test_sys.iobus.master + # Connect the ruby io port to the PIO bus, + # assuming that there is just one such port. + test_sys.iobus.master = test_sys.ruby._io_port.slave else: if options.caches or options.l2cache: diff -r dbbbbf113c25 -r 94b72f56b957 configs/example/ruby_mem_test.py --- a/configs/example/ruby_mem_test.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/example/ruby_mem_test.py Tue Oct 21 17:07:58 2014 -0500 @@ -159,12 +159,6 @@ # system.ruby._cpu_ports[i].deadlock_threshold = 5000000 - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - system.ruby._cpu_ports[i].access_phys_mem = False - for (i, dma) in enumerate(dmas): # # Tie the dma memtester ports to the correct functional port diff -r dbbbbf113c25 -r 94b72f56b957 configs/example/ruby_network_test.py --- a/configs/example/ruby_network_test.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/example/ruby_network_test.py Tue Oct 21 17:07:58 2014 -0500 @@ -125,8 +125,6 @@ # Tie the cpu test ports to the ruby cpu port # cpus[i].test = ruby_port.slave - ruby_port.access_phys_mem = False - i += 1 # ----------------------- diff -r dbbbbf113c25 -r 94b72f56b957 configs/example/ruby_random_test.py --- a/configs/example/ruby_random_test.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/example/ruby_random_test.py Tue Oct 21 17:07:58 2014 -0500 @@ -137,12 +137,6 @@ # ruby_port.using_ruby_tester = True - # - # Ruby doesn't need the backing image of memory when running with - # the tester. - # - ruby_port.access_phys_mem = False - # ----------------------- # run simulation # ----------------------- diff -r dbbbbf113c25 -r 94b72f56b957 configs/ruby/MESI_Two_Level.py --- a/configs/ruby/MESI_Two_Level.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/ruby/MESI_Two_Level.py Tue Oct 21 17:07:58 2014 -0500 @@ -196,7 +196,8 @@ for i, dma_port in enumerate(dma_ports): # Create the Ruby objects associated with the dma controller dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -204,7 +205,6 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) # Connect the dma controller to the network @@ -212,11 +212,24 @@ dma_cntrl.requestToDir = ruby_system.network.slave + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.requestToDir = ruby_system.network.slave + + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) - return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r dbbbbf113c25 -r 94b72f56b957 configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/ruby/MOESI_CMP_directory.py Tue Oct 21 17:07:58 2014 -0500 @@ -192,7 +192,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -200,14 +201,33 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) + # Connect the dma controller to the network + dma_cntrl.responseFromDir = ruby_system.network.master + dma_cntrl.reqToDir = ruby_system.network.slave + dma_cntrl.respToDir = ruby_system.network.slave + + + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.reqToDir = ruby_system.network.slave + io_controller.respToDir = ruby_system.network.slave + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r dbbbbf113c25 -r 94b72f56b957 configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/ruby/MOESI_CMP_token.py Tue Oct 21 17:07:58 2014 -0500 @@ -222,7 +222,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -230,13 +231,30 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) + # Connect the dma controller to the network + dma_cntrl.responseFromDir = ruby_system.network.master + dma_cntrl.reqToDirectory = ruby_system.network.slave + + + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller + + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.reqToDirectory = ruby_system.network.slave + all_cntrls = l1_cntrl_nodes + \ l2_cntrl_nodes + \ dir_cntrl_nodes + \ - dma_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) diff -r dbbbbf113c25 -r 94b72f56b957 configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Tue Oct 21 17:05:37 2014 -0500 +++ b/configs/ruby/MOESI_hammer.py Tue Oct 21 17:07:58 2014 -0500 @@ -224,7 +224,8 @@ # Create the Ruby objects associated with the dma controller # dma_seq = DMASequencer(version = i, - ruby_system = ruby_system) + ruby_system = ruby_system, + slave = dma_port) dma_cntrl = DMA_Controller(version = i, dma_sequencer = dma_seq, @@ -232,7 +233,6 @@ ruby_system = ruby_system) exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) - exec("ruby_system.dma_cntrl%d.dma_sequencer.slave = dma_port" % i) dma_cntrl_nodes.append(dma_cntrl) if options.recycle_latency: @@ -242,7 +242,20 @@ dma_cntrl.responseFromDir = ruby_system.network.master dma_cntrl.requestToDir = ruby_system.network.slave + # Create the io controller and the sequencer + io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) + ruby_system._io_port = io_seq + io_controller = DMA_Controller(version = len(dma_ports), + dma_sequencer = io_seq, + ruby_system = ruby_system) + ruby_system.io_controller = io_controller - all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes + # Connect the dma controller to the network + io_controller.responseFromDir = ruby_system.network.master + io_controller.requestToDir = ruby_system.network.slave + + + all_cntrls = l1_cntrl_nodes + dir_cntrl_nodes + dma_cntrl_nodes + \ + [io_controller] topology = create_topology(all_cntrls, options) return (cpu_sequencers, dir_cntrl_nodes, topology) diff -r dbbbbf113c25 -r 94b72f56b957 src/mem/protocol/MESI_Two_Level-dma.sm --- a/src/mem/protocol/MESI_Two_Level-dma.sm Tue Oct 21 17:05:37 2014 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dma.sm Tue Oct 21 17:07:58 2014 -0500 @@ -49,11 +49,6 @@ Ack, desc="DMA write to memory completed"; } - structure(DMASequencer, external="yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - MessageBuffer mandatoryQueue, ordered="false"; State cur_state; diff -r dbbbbf113c25 -r 94b72f56b957 src/mem/protocol/MOESI_CMP_directory-dma.sm --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Tue Oct 21 17:05:37 2014 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Tue Oct 21 17:07:58 2014 -0500 @@ -62,11 +62,6 @@ DataBlock DataBlk, desc="Data"; } - structure(DMASequencer, external = "yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - structure(TBETable, external = "yes") { TBE lookup(Address); void allocate(Address); diff -r dbbbbf113c25 -r 94b72f56b957 src/mem/protocol/MOESI_CMP_token-dma.sm --- a/src/mem/protocol/MOESI_CMP_token-dma.sm Tue Oct 21 17:05:37 2014 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Tue Oct 21 17:07:58 2014 -0500 @@ -51,11 +51,6 @@ Ack, desc="DMA write to memory completed"; } - structure(DMASequencer, external="yes") { - void ackCallback(); - void dataCallback(DataBlock); - } - MessageBuffer mandatoryQueue, ordered="false"; State cur_state; diff -r dbbbbf113c25 -r 94b72f56b957 src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Tue Oct 21 17:05:37 2014 -0500 +++ b/src/mem/ruby/system/DMASequencer.cc Tue Oct 21 17:07:58 2014 -0500 @@ -56,6 +56,8 @@ m_mandatory_q_ptr->setSender(this); m_is_busy = false; m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); + + slave_port.sendRangeChange(); } BaseSlavePort & diff -r dbbbbf113c25 -r 94b72f56b957 tests/configs/pc-simple-timing-ruby.py --- a/tests/configs/pc-simple-timing-ruby.py Tue Oct 21 17:05:37 2014 -0500 +++ b/tests/configs/pc-simple-timing-ruby.py Tue Oct 21 17:07:58 2014 -0500 @@ -74,6 +74,10 @@ system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, voltage_domain = system.voltage_domain) +# Connect the ruby io port to the PIO bus, +# assuming that there is just one such port. +system.iobus.master = system.ruby._io_port.slave + for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() @@ -82,17 +86,13 @@ cpu.dcache_port = system.ruby._cpu_ports[i].slave cpu.itb.walker.port = system.ruby._cpu_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave + cpu.interrupts.pio = system.ruby._cpu_ports[i].master cpu.interrupts.int_master = system.ruby._cpu_ports[i].slave cpu.interrupts.int_slave = system.ruby._cpu_ports[i].master - # Set access_phys_mem to True for ruby port - system.ruby._cpu_ports[i].access_phys_mem = True - -system.physmem = [DDR3_1600_x64(range = r) +system.physmem = [SimpleMemory(range = r, null = True) for r in system.mem_ranges] -for i in xrange(len(system.physmem)): - system.physmem[i].port = system.iobus.master root = Root(full_system = True, system = system) m5.ticks.setGlobalFrequency('1THz')