diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa.cc --- a/src/arch/arm/isa.cc Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa.cc Mon Aug 23 11:31:27 2010 -0500 @@ -139,6 +139,8 @@ (0 << 2) | // 3:2 0; // 1:0 + miscRegs[MISCREG_CPACR] = 0; + miscRegs[MISCREG_FPSID] = 0x410430A0; //XXX We need to initialize the rest of the state. } diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/insts/fp.isa --- a/src/arch/arm/isa/insts/fp.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/insts/fp.isa Mon Aug 23 11:31:27 2010 -0500 @@ -192,14 +192,14 @@ exec_output = "" vmsrIop = InstObjParams("vmsr", "Vmsr", "FpRegRegOp", - { "code": vmsrrsEnabledCheckCode + \ + { "code": vmsrEnabledCheckCode + \ "MiscDest = Op1;", "predicate_test": predicateTest }, []) header_output += FpRegRegOpDeclare.subst(vmsrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrIop); exec_output += PredOpExecute.subst(vmsrIop); - vmsrFpscrCode = vmsrrsEnabledCheckCode + ''' + vmsrFpscrCode = vmsrEnabledCheckCode + ''' Fpscr = Op1 & ~FpCondCodesMask; FpCondCodes = Op1 & FpCondCodesMask; ''' @@ -211,7 +211,7 @@ exec_output += PredOpExecute.subst(vmsrFpscrIop); vmrsIop = InstObjParams("vmrs", "Vmrs", "FpRegRegOp", - { "code": vmsrrsEnabledCheckCode + \ + { "code": vmrsEnabledCheckCode + \ "Dest = MiscOp1;", "predicate_test": predicateTest }, []) header_output += FpRegRegOpDeclare.subst(vmrsIop); @@ -219,14 +219,14 @@ exec_output += PredOpExecute.subst(vmrsIop); vmrsFpscrIop = InstObjParams("vmrs", "VmrsFpscr", "FpRegRegOp", - { "code": vmsrrsEnabledCheckCode + \ + { "code": vmrsEnabledCheckCode + \ "Dest = Fpscr | FpCondCodes;", "predicate_test": predicateTest }, []) header_output += FpRegRegOpDeclare.subst(vmrsFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmrsFpscrIop); exec_output += PredOpExecute.subst(vmrsFpscrIop); - vmrsApsrCode = vmsrrsEnabledCheckCode + ''' + vmrsApsrCode = vmrsEnabledCheckCode + ''' Dest = (MiscOp1 & imm) | (Dest & ~imm); ''' vmrsApsrIop = InstObjParams("vmrs", "VmrsApsr", "FpRegRegImmOp", @@ -236,7 +236,7 @@ decoder_output += FpRegRegImmOpConstructor.subst(vmrsApsrIop); exec_output += PredOpExecute.subst(vmrsApsrIop); - vmrsApsrFpscrCode = vmsrrsEnabledCheckCode + ''' + vmrsApsrFpscrCode = vmrsEnabledCheckCode + ''' assert((imm & ~FpCondCodesMask) == 0); Dest = (FpCondCodes & imm) | (Dest & ~imm); ''' diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/insts/ldr.isa Mon Aug 23 11:31:27 2010 -0500 @@ -160,6 +160,10 @@ if not self.post: eaCode += self.offset eaCode += ";" + + if self.flavor == "fp": + eaCode += vfpEnabledCheckCode + self.codeBlobs["ea_code"] = eaCode # Code that actually handles the access @@ -220,6 +224,10 @@ if not self.post: eaCode += self.offset eaCode += ";" + + if self.flavor == "fp": + eaCode += vfpEnabledCheckCode + self.codeBlobs["ea_code"] = eaCode # Code that actually handles the access diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/insts/macromem.isa --- a/src/arch/arm/isa/insts/macromem.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/insts/macromem.isa Mon Aug 23 11:31:27 2010 -0500 @@ -59,7 +59,7 @@ microLdrFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrFpUop', 'MicroMemOp', {'memacc_code': microLdrFpUopCode, - 'ea_code': + 'ea_code': vfpEnabledCheckCode + 'EA = Rb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -68,7 +68,7 @@ microLdrDBFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDBFpUop', 'MicroMemOp', {'memacc_code': microLdrFpUopCode, - 'ea_code': ''' + 'ea_code': vfpEnabledCheckCode + ''' EA = Rb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); ''', @@ -79,7 +79,7 @@ microLdrDTFpUopIop = InstObjParams('ldrfp_uop', 'MicroLdrDTFpUop', 'MicroMemOp', {'memacc_code': microLdrFpUopCode, - 'ea_code': ''' + 'ea_code': vfpEnabledCheckCode + ''' EA = Rb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); ''', @@ -117,7 +117,8 @@ 'MicroMemOp', {'memacc_code': microStrFpUopCode, 'postacc_code': "", - 'ea_code': 'EA = Rb + (up ? imm : -imm);', + 'ea_code': vfpEnabledCheckCode + + 'EA = Rb + (up ? imm : -imm);', 'predicate_test': predicateTest}, ['IsMicroop']) @@ -126,7 +127,7 @@ 'MicroMemOp', {'memacc_code': microStrFpUopCode, 'postacc_code': "", - 'ea_code': ''' + 'ea_code': vfpEnabledCheckCode + ''' EA = Rb + (up ? imm : -imm) + (((CPSR)Cpsr).e ? 4 : 0); ''', @@ -138,7 +139,7 @@ 'MicroMemOp', {'memacc_code': microStrFpUopCode, 'postacc_code': "", - 'ea_code': ''' + 'ea_code': vfpEnabledCheckCode + ''' EA = Rb + (up ? imm : -imm) - (((CPSR)Cpsr).e ? 4 : 0); ''', @@ -222,7 +223,7 @@ { 'mem_decl' : memDecl, 'size' : size, 'memacc_code' : loadMemAccCode, - 'ea_code' : eaCode, + 'ea_code' : simdEnabledCheckCode + eaCode, 'predicate_test' : predicateTest }, [ 'IsMicroop', 'IsMemRef', 'IsLoad' ]) storeIop = InstObjParams('strneon%(size)d_uop' % subst, @@ -231,7 +232,7 @@ { 'mem_decl' : memDecl, 'size' : size, 'memacc_code' : storeMemAccCode, - 'ea_code' : eaCode, + 'ea_code' : simdEnabledCheckCode + eaCode, 'predicate_test' : predicateTest }, [ 'IsMicroop', 'IsMemRef', 'IsStore' ]) diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/insts/neon.isa --- a/src/arch/arm/isa/insts/neon.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/insts/neon.isa Mon Aug 23 11:31:27 2010 -0500 @@ -620,13 +620,6 @@ }}; let {{ - simdEnabledCheckCode = ''' - if (!neonEnabled(Cpacr, Cpsr, Fpexc)) - return disabledFault(); - ''' -}}; - -let {{ header_output = "" exec_output = "" @@ -3235,7 +3228,7 @@ RegVect srcReg1, srcReg2, destReg; ''' for reg in range(rCount): - eWalkCode += ''' + eWalkCode += simdEnabledCheckCode + ''' srcReg1.regs[%(reg)d] = htog(FpOp1P%(reg)d.uw); srcReg2.regs[%(reg)d] = htog(FpOp2P%(reg)d.uw); ''' % { "reg" : reg } diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/insts/str.isa --- a/src/arch/arm/isa/insts/str.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/insts/str.isa Mon Aug 23 11:31:27 2010 -0500 @@ -171,6 +171,10 @@ if not self.post: eaCode += self.offset eaCode += ";" + + if self.flavor == "fp": + eaCode += vfpEnabledCheckCode + self.codeBlobs["ea_code"] = eaCode # Code that actually handles the access @@ -241,6 +245,10 @@ if not self.post: eaCode += self.offset eaCode += ";" + + if self.flavor == "fp": + eaCode += vfpEnabledCheckCode + self.codeBlobs["ea_code"] = eaCode # Code that actually handles the access diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/templates/neon.isa --- a/src/arch/arm/isa/templates/neon.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/templates/neon.isa Mon Aug 23 11:31:27 2010 -0500 @@ -37,6 +37,14 @@ // // Authors: Gabe Black +let {{ + simdEnabledCheckCode = ''' + if (!neonEnabled(Cpacr, Cpsr, Fpexc)) + return disabledFault(); + ''' +}}; + + def template NeonRegRegRegOpDeclare {{ template class %(class_name)s : public %(base_class)s diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/isa/templates/vfp.isa --- a/src/arch/arm/isa/templates/vfp.isa Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/isa/templates/vfp.isa Mon Aug 23 11:31:27 2010 -0500 @@ -43,9 +43,24 @@ return disabledFault(); ''' - vmsrrsEnabledCheckCode = ''' + vmsrEnabledCheckCode = ''' if (!vfpEnabled(Cpacr, Cpsr)) - return disabledFault(); + if (dest != (int)MISCREG_FPEXC && dest != (int)MISCREG_FPSID) + return disabledFault(); + if (!inPrivilegedMode(Cpsr)) + if (dest != (int)MISCREG_FPSCR) + return disabledFault(); + + ''' + + vmrsEnabledCheckCode = ''' + if (!vfpEnabled(Cpacr, Cpsr)) + if (op1 != (int)MISCREG_FPEXC && op1 != (int)MISCREG_FPSID && + op1 != (int)MISCREG_MVFR0 && op1 != (int)MISCREG_MVFR1) + return disabledFault(); + if (!inPrivilegedMode(Cpsr)) + if (op1 != (int)MISCREG_FPSCR) + return disabledFault(); ''' }}; diff -r 3255a377bd56 -r a82c814b13b5 src/arch/arm/utility.hh --- a/src/arch/arm/utility.hh Mon Aug 23 11:31:15 2010 -0500 +++ b/src/arch/arm/utility.hh Mon Aug 23 11:31:27 2010 -0500 @@ -169,7 +169,7 @@ vfpEnabled(CPACR cpacr, CPSR cpsr) { return cpacr.cp10 == 0x3 || - (cpacr.cp10 == 0x2 && inPrivilegedMode(cpsr)); + (cpacr.cp10 == 0x1 && inPrivilegedMode(cpsr)); } static inline bool