diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/basic.isa --- a/src/arch/arm/isa/templates/basic.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/basic.isa Wed Apr 23 13:06:15 2014 +0100 @@ -73,7 +73,7 @@ }}; def template BasicConstructor64 {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) + %(class_name)s::%(class_name)s(ExtMachInst machInst) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; } diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/branch.isa --- a/src/arch/arm/isa/templates/branch.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/branch.isa Wed Apr 23 13:06:15 2014 +0100 @@ -48,7 +48,7 @@ }}; def template BranchImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -81,7 +81,7 @@ }}; def template BranchImmCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -110,7 +110,7 @@ }}; def template BranchRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -140,7 +140,7 @@ }}; def template BranchRegCondConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -187,7 +187,7 @@ }}; def template BranchRegRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) @@ -218,7 +218,7 @@ // Only used by CBNZ, CBZ which is conditional based on // a register value even though the instruction is always unconditional. def template BranchImmRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/branch64.isa --- a/src/arch/arm/isa/templates/branch64.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/branch64.isa Wed Apr 23 13:06:15 2014 +0100 @@ -48,7 +48,7 @@ }}; def template BranchImm64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { @@ -68,7 +68,7 @@ }}; def template BranchImmCond64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, ConditionCode _condCode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -89,7 +89,7 @@ }}; def template BranchReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) { @@ -109,7 +109,7 @@ }}; def template BranchImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) @@ -130,7 +130,7 @@ }}; def template BranchImmImmReg64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/data64.isa --- a/src/arch/arm/isa/templates/data64.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/data64.isa Wed Apr 23 13:06:15 2014 +0100 @@ -49,7 +49,7 @@ }}; def template DataXImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) @@ -73,7 +73,7 @@ }}; def template DataXSRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -99,7 +99,7 @@ }}; def template DataXERegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -124,7 +124,7 @@ }}; def template DataX1RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) @@ -145,7 +145,7 @@ }}; def template DataX2RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) @@ -168,7 +168,7 @@ }}; def template DataX2RegImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -192,7 +192,7 @@ }}; def template DataX3RegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -216,7 +216,7 @@ }}; def template DataXCondCompImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint64_t _imm, ConditionCode _condCode, @@ -241,7 +241,7 @@ }}; def template DataXCondCompRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2, ConditionCode _condCode, @@ -266,7 +266,7 @@ }}; def template DataXCondSelConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/mem.isa --- a/src/arch/arm/isa/templates/mem.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/mem.isa Wed Apr 23 13:06:15 2014 +0100 @@ -860,7 +860,7 @@ }}; def template RfeConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _base, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_base, (AddrMode)_mode, _wb) @@ -889,7 +889,7 @@ }}; def template SrsConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _regMode, int _mode, bool _wb) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (OperatingMode)_regMode, (AddrMode)_mode, _wb) @@ -912,7 +912,7 @@ }}; def template SwapConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _op1, uint32_t _base) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base) @@ -927,7 +927,7 @@ }}; def template LoadStoreDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -952,7 +952,7 @@ }}; def template StoreExDImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -979,7 +979,7 @@ }}; def template LoadStoreImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) @@ -1002,7 +1002,7 @@ }}; def template StoreExImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _result, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1028,7 +1028,7 @@ }}; def template StoreDRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1056,7 +1056,7 @@ }}; def template StoreRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1083,7 +1083,7 @@ }}; def template LoadDRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1123,7 +1123,7 @@ }}; def template LoadRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -1189,7 +1189,7 @@ }}; def template LoadImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm) diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/mem64.isa --- a/src/arch/arm/isa/templates/mem64.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/mem64.isa Wed Apr 23 13:06:15 2014 +0100 @@ -589,7 +589,7 @@ }}; def template StoreImmDEx64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base, int64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/misc.isa --- a/src/arch/arm/isa/templates/misc.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/misc.isa Wed Apr 23 13:06:15 2014 +0100 @@ -49,7 +49,7 @@ }}; def template MrsConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest) { @@ -78,7 +78,7 @@ }}; def template MrsBankedRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _sysM, bool _r) @@ -109,7 +109,7 @@ }}; def template MsrBankedRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t _sysM, bool _r) @@ -137,7 +137,7 @@ }}; def template MsrRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask) @@ -163,7 +163,7 @@ }}; def template MsrImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, imm, mask) @@ -190,7 +190,7 @@ }}; def template MrrcOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex op1, IntRegIndex dest, IntRegIndex dest2, @@ -220,7 +220,7 @@ }}; def template McrrOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex op1, IntRegIndex op2, IntRegIndex dest, @@ -249,7 +249,7 @@ }}; def template ImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) + %(class_name)s::%(class_name)s(ExtMachInst machInst, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) { %(constructor)s; @@ -273,7 +273,7 @@ }}; def template RegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm) { @@ -299,7 +299,7 @@ }}; def template RegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1) { @@ -326,7 +326,7 @@ }}; def template RegRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -357,7 +357,7 @@ }}; def template RegRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -387,7 +387,7 @@ }}; def template RegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) @@ -417,7 +417,7 @@ }}; def template RegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) @@ -446,7 +446,7 @@ }}; def template RegImmImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm1, uint64_t _imm2) @@ -476,7 +476,7 @@ }}; def template RegRegImmImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, @@ -506,7 +506,7 @@ }}; def template RegImmRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1) @@ -536,7 +536,7 @@ }}; def template RegImmRegShiftOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, IntRegIndex _op1, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/misc64.isa --- a/src/arch/arm/isa/templates/misc64.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/misc64.isa Wed Apr 23 13:06:15 2014 +0100 @@ -51,7 +51,7 @@ }}; def template RegRegImmImmOp64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1, @@ -77,7 +77,7 @@ }}; def template RegRegRegImmOp64Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/mult.isa --- a/src/arch/arm/isa/templates/mult.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/mult.isa Wed Apr 23 13:06:15 2014 +0100 @@ -49,7 +49,7 @@ }}; def template Mult3Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2) @@ -78,7 +78,7 @@ }}; def template Mult4Constructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/pred.isa --- a/src/arch/arm/isa/templates/pred.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/pred.isa Wed Apr 23 13:06:15 2014 +0100 @@ -62,7 +62,7 @@ }}; def template DataImmConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, @@ -101,7 +101,7 @@ }}; def template DataRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -146,7 +146,7 @@ }}; def template DataRegRegConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/vfp.isa --- a/src/arch/arm/isa/templates/vfp.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/vfp.isa Wed Apr 23 13:06:15 2014 +0100 @@ -166,7 +166,7 @@ }}; def template FpRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -193,7 +193,7 @@ }}; def template FpRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) @@ -220,7 +220,7 @@ }}; def template FpRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, @@ -250,7 +250,7 @@ }}; def template FpRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, diff -r fdbb731d5565 -r 4dac507c6ab5 src/arch/arm/isa/templates/vfp64.isa --- a/src/arch/arm/isa/templates/vfp64.isa Wed Mar 19 19:18:43 2014 -0500 +++ b/src/arch/arm/isa/templates/vfp64.isa Wed Apr 23 13:06:15 2014 +0100 @@ -38,7 +38,7 @@ // Authors: Thomas Grocutt def template AA64FpRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -52,7 +52,7 @@ }}; def template AA64FpRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, @@ -66,7 +66,7 @@ }}; def template AA64FpRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm, mode) @@ -79,7 +79,7 @@ }}; def template AA64FpRegRegImmOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm, @@ -95,7 +95,7 @@ }}; def template AA64FpRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, @@ -123,7 +123,7 @@ }}; def template AA64FpRegRegRegRegOpConstructor {{ - inline %(class_name)s::%(class_name)s(ExtMachInst machInst, + %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,