diff -r 8f76362764d5 -r a286134ba20e src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/alpha/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -87,6 +87,8 @@
     TLB(const Params *p);
     virtual ~TLB();
 
+    void takeOverFrom(BaseTLB *otlb) {}
+
     virtual void regStats();
 
     int getsize() const { return size; }
diff -r 8f76362764d5 -r a286134ba20e src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/arm/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -155,6 +155,8 @@
 
     virtual ~TLB();
 
+    void takeOverFrom(BaseTLB *otlb);
+
     /// setup all the back pointers
     virtual void init();
 
diff -r 8f76362764d5 -r a286134ba20e src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/arm/tlb.cc	Wed Apr 23 13:07:55 2014 +0100
@@ -354,6 +354,30 @@
 }
 
 void
+TLB::takeOverFrom(BaseTLB *_otlb)
+{
+    TLB *otlb = dynamic_cast<TLB*>(_otlb);
+    /* Make sure we actually have a valid type */
+    if (otlb) {
+        _attr = otlb->_attr;
+        haveLPAE = otlb->haveLPAE;
+        directToStage2 = otlb->directToStage2;
+        stage2Req = otlb->stage2Req;
+        bootUncacheability = otlb->bootUncacheability;
+
+        /* Sync the stage2 MMU if they exist in both
+         * the old CPU and the new
+         */
+        if (!isStage2 &&
+            stage2Tlb && otlb->stage2Tlb) {
+            stage2Tlb->takeOverFrom(otlb->stage2Tlb);
+        }
+    } else {
+        panic("Incompatible TLB type!");
+    }
+}
+
+void
 TLB::serialize(ostream &os)
 {
     DPRINTF(Checkpoint, "Serializing Arm TLB\n");
diff -r 8f76362764d5 -r a286134ba20e src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/mips/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -87,6 +87,9 @@
     int probeEntry(Addr vpn,uint8_t) const;
     MipsISA::PTE *getEntry(unsigned) const;
     virtual ~TLB();
+
+    void takeOverFrom(BaseTLB *otlb) {}
+
     int smallPages;
     int getsize() const { return size; }
 
diff -r 8f76362764d5 -r a286134ba20e src/arch/power/tlb.hh
--- a/src/arch/power/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/power/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -130,6 +130,8 @@
     TLB(const Params *p);
     virtual ~TLB();
 
+    void takeOverFrom(BaseTLB *otlb) {}
+
     int probeEntry(Addr vpn,uint8_t) const;
     PowerISA::PTE *getEntry(unsigned) const;
 
diff -r 8f76362764d5 -r a286134ba20e src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/sparc/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -154,6 +154,8 @@
     typedef SparcTLBParams Params;
     TLB(const Params *p);
 
+    void takeOverFrom(BaseTLB *otlb) {}
+
     void
     demapPage(Addr vaddr, uint64_t asn)
     {
diff -r 8f76362764d5 -r a286134ba20e src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/arch/x86/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -75,6 +75,8 @@
         typedef X86TLBParams Params;
         TLB(const Params *p);
 
+        void takeOverFrom(BaseTLB *otlb) {}
+
         TlbEntry *lookup(Addr va, bool update_lru = true);
 
         void setConfigAddress(uint32_t addr);
diff -r 8f76362764d5 -r a286134ba20e src/cpu/base.cc
--- a/src/cpu/base.cc	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/cpu/base.cc	Wed Apr 23 13:07:55 2014 +0100
@@ -432,6 +432,8 @@
             old_dtb_port->unbind();
             new_dtb_port->bind(slavePort);
         }
+        newTC->getITBPtr()->takeOverFrom(oldTC->getITBPtr());
+        newTC->getDTBPtr()->takeOverFrom(oldTC->getDTBPtr());
 
         // Checker whether or not we have to transfer CheckerCPU
         // objects over in the switch
@@ -447,6 +449,9 @@
             BaseMasterPort *new_checker_dtb_port =
                 newChecker->getDTBPtr()->getMasterPort();
 
+            newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
+            newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());
+
             // Move over any table walker ports if they exist for checker
             if (new_checker_itb_port) {
                 assert(!new_checker_itb_port->isConnected());
diff -r 8f76362764d5 -r a286134ba20e src/sim/tlb.hh
--- a/src/sim/tlb.hh	Wed Apr 23 13:07:47 2014 +0100
+++ b/src/sim/tlb.hh	Wed Apr 23 13:07:55 2014 +0100
@@ -70,6 +70,11 @@
     virtual void flushAll() = 0;
 
     /**
+     * Take over from an old tlb context
+     */
+    virtual void takeOverFrom(BaseTLB *otlb) = 0;
+
+    /**
      * Get the table walker master port if present. This is used for
      * migrating port connections during a CPU takeOverFrom()
      * call. For architectures that do not have a table walker, NULL