diff -r a7b43fb8a4aa -r 845943c6f8ad src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh	Tue Apr 29 12:54:15 2014 +0100
+++ b/src/cpu/static_inst.hh	Tue Apr 29 12:54:16 2014 +0100
@@ -326,6 +326,14 @@
     virtual std::string
     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 
+    /**
+     *  Prints the name of a flag to os. Unhandled/invalid flags are
+     *  printed as '((StaticInst::Flag) <enum-elementnumber>)'
+     *
+     *  remember to add new flag strings as they are added here.
+     */
+    void printFlag(std::ostream &os, Flags flag) const;
+
     /// Constructor.
     /// It's important to initialize everything here to a sane
     /// default, since the decoder generally only overrides
@@ -387,6 +395,12 @@
     virtual const std::string &disassemble(Addr pc,
         const SymbolTable *symtab = 0) const;
 
+    /**
+     * Print a separator separated list of this instruction's set flag
+     * names on the given stream.
+     */
+    void printFlags(std::ostream &outs, const std::string &separator) const;
+
     /// Return name of machine instruction
     std::string getName() { return mnemonic; }
 };
diff -r a7b43fb8a4aa -r 845943c6f8ad src/cpu/static_inst.cc
--- a/src/cpu/static_inst.cc	Tue Apr 29 12:54:15 2014 +0100
+++ b/src/cpu/static_inst.cc	Tue Apr 29 12:54:16 2014 +0100
@@ -92,3 +92,150 @@
 
     return *cachedDisassembly;
 }
+
+void
+StaticInst::printFlag(std::ostream &os, StaticInst::Flags flag) const
+{
+    switch (flag) {
+      case IsNop:
+        os << "IsNop";
+        break;
+      case IsInteger:
+        os << "IsInteger";
+        break;
+      case IsFloating:
+        os << "IsFloating";
+        break;
+      case IsCC:
+        os << "IsCC";
+        break;
+      case IsMemRef:
+        os << "IsMemRef";
+        break;
+      case IsLoad:
+        os << "IsLoad";
+        break;
+      case IsStore:
+        os << "IsStore";
+        break;
+      case IsStoreConditional:
+        os << "IsStoreConditional";
+        break;
+      case IsIndexed:
+        os << "IsIndexed";
+        break;
+      case IsInstPrefetch:
+        os << "IsInstPrefetch";
+        break;
+      case IsDataPrefetch:
+        os << "IsDataPrefetch";
+        break;
+      case IsControl:
+        os << "IsControl";
+        break;
+      case IsDirectControl:
+        os << "IsDirectControl";
+        break;
+      case IsIndirectControl:
+        os << "IsIndirectControl";
+        break;
+      case IsCondControl:
+        os << "IsCondControl";
+        break;
+      case IsUncondControl:
+        os << "IsUncondControl";
+        break;
+      case IsCall:
+        os << "IsCall";
+        break;
+      case IsReturn:
+        os << "IsReturn";
+        break;
+      case IsCondDelaySlot:
+        os << "IsCondDelaySlot";
+        break;
+      case IsThreadSync:
+        os << "IsThreadSync";
+        break;
+      case IsSerializing:
+        os << "IsSerializing";
+        break;
+      case IsSerializeBefore:
+        os << "IsSerializeBefore";
+        break;
+      case IsSerializeAfter:
+        os << "IsSerializeAfter";
+        break;
+      case IsMemBarrier:
+        os << "IsMemBarrier";
+        break;
+      case IsWriteBarrier:
+        os << "IsWriteBarrier";
+        break;
+      case IsReadBarrier:
+        os << "IsReadBarrier";
+        break;
+      case IsERET:
+        os << "IsERET";
+        break;
+      case IsNonSpeculative:
+        os << "IsNonSpeculative";
+        break;
+      case IsQuiesce:
+        os << "IsQuiesce";
+        break;
+      case IsIprAccess:
+        os << "IsIprAccess";
+        break;
+      case IsUnverifiable:
+        os << "IsUnverifiable";
+        break;
+      case IsSyscall:
+        os << "IsSyscall";
+        break;
+      case IsMacroop:
+        os << "IsMacroop";
+        break;
+      case IsMicroop:
+        os << "IsMicroop";
+        break;
+      case IsDelayedCommit:
+        os << "IsDelayedCommit";
+        break;
+      case IsLastMicroop:
+        os << "IsLastMicroop";
+        break;
+      case IsFirstMicroop:
+        os << "IsFirstMicroop";
+        break;
+      case IsMicroBranch:
+        os << "IsMicroBranch";
+        break;
+      case IsDspOp:
+        os << "IsDspOp";
+        break;
+      case IsSquashAfter:
+        os << "IsSquashAfter";
+        break;
+      default:
+        os << "((StaticInst::Flag) " << (int) flag << ')';
+        break;
+    }
+}
+
+void
+StaticInst::printFlags(std::ostream &outs,
+    const std::string &separator) const
+{
+    bool printed_a_flag = false;
+
+    for (unsigned int flag = IsNop; flag < NumFlags; flag++) {
+        if (flags[flag]) {
+            if (printed_a_flag)
+                outs << separator;
+
+            printFlag(outs, static_cast<Flags>(flag));
+            printed_a_flag = true;
+        }
+    }
+}