diff -r 6aad49040474 -r 02b6fdd33908 src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py	Wed Apr 23 13:12:54 2014 +0100
+++ b/src/mem/DRAMCtrl.py	Wed Apr 23 13:13:02 2014 +0100
@@ -119,6 +119,9 @@
 
     # timing behaviour and constraints - all in nanoseconds
 
+    # the base clock period of the DRAM
+    tCK = Param.Latency("Clock period")
+
     # the amount of time in nanoseconds from issuing an activate command
     # to the data being available in the row buffer for a read/write
     tRCD = Param.Latency("RAS to CAS delay")
@@ -195,6 +198,9 @@
     # DDR3 has 8 banks in all configurations
     banks_per_rank = 8
 
+    # 800 MHz
+    tCK = '1.25ns'
+
     # DDR3-1600 11-11-11-28
     tRCD = '13.75ns'
     tCL = '13.75ns'
@@ -256,6 +262,9 @@
     # DDR3 has 8 banks in all configurations
     banks_per_rank = 8
 
+    # 666 MHs
+    tCK = '1.5ns'
+
     tRCD = '15ns'
     tCL = '15ns'
     tRP = '15ns'
@@ -307,6 +316,9 @@
     # LPDDR2-S4 has 8 banks in all configurations
     banks_per_rank = 8
 
+    # 533 MHz
+    tCK = '1.876ns'
+
     # Fixed at 15 ns
     tRCD = '15ns'
 
@@ -367,6 +379,9 @@
     # WideIO has 4 banks in all configurations
     banks_per_rank = 4
 
+    # 200 MHz
+    tCK = '5ns'
+
     # WIO-200
     tRCD = '18ns'
     tCL = '18ns'
@@ -421,6 +436,9 @@
     # LPDDR3 has 8 banks in all configurations
     banks_per_rank = 8
 
+    # 800 MHz
+    tCK = '1.25ns'
+
     # Fixed at 15 ns
     tRCD = '15ns'
 
diff -r 6aad49040474 -r 02b6fdd33908 src/mem/dram_ctrl.hh
--- a/src/mem/dram_ctrl.hh	Wed Apr 23 13:12:54 2014 +0100
+++ b/src/mem/dram_ctrl.hh	Wed Apr 23 13:13:02 2014 +0100
@@ -470,6 +470,7 @@
      * Basic memory timing parameters initialized based on parameter
      * values.
      */
+    const Tick tCK;
     const Tick tWTR;
     const Tick tRTW;
     const Tick tBURST;
diff -r 6aad49040474 -r 02b6fdd33908 src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc	Wed Apr 23 13:12:54 2014 +0100
+++ b/src/mem/dram_ctrl.cc	Wed Apr 23 13:13:02 2014 +0100
@@ -74,7 +74,7 @@
     writeLowThreshold(writeBufferSize * p->write_low_thresh_perc / 100.0),
     minWritesPerSwitch(p->min_writes_per_switch),
     writesThisTime(0), readsThisTime(0),
-    tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
+    tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
     tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
     tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
     tXAW(p->tXAW), activationLimit(p->activation_limit),
@@ -551,6 +551,7 @@
             writeLowThreshold, scheduler, address_mapping, page_policy);
 
     DPRINTF(DRAM, "Memory controller %s timing specs\n" \
+            "tCK       %d ticks\n"                        \
             "tRCD      %d ticks\n"                        \
             "tCL       %d ticks\n"                        \
             "tRP       %d ticks\n"                        \
@@ -564,8 +565,8 @@
             "tRTW      %d ticks\n"                        \
             "tRRD      %d ticks\n"                        \
             "tXAW (%d) %d ticks\n",
-            name(), tRCD, tCL, tRP, tRAS, tWR, tRTP, tBURST, tRFC, tREFI, tWTR,
-            tRTW, tRRD, activationLimit, tXAW);
+            name(), tCK, tRCD, tCL, tRP, tRAS, tWR, tRTP, tBURST, tRFC,
+            tREFI, tWTR, tRTW, tRRD, activationLimit, tXAW);
 }
 
 void