diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -10,7 +10,7 @@
 # unmodified and in its entirety in all distributions of the software,
 # modified or unmodified, in source code or in binary form.
 #
-# Copyright (c) 2013 Amin Farmahini-Farahani
+# Copyright (c) 2013-2014 Amin Farmahini-Farahani
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -165,6 +165,9 @@
     # minimum row activate to row activate delay time
     tRRD = Param.Latency("ACT to ACT delay")
 
+    # minimum column to column delay
+    tCCD = Param.Latency("CAS to CAS delay")
+
     # time window in which a maximum number of activates are allowed
     # to take place, set to 0 to disable
     tXAW = Param.Latency("X activation window")
@@ -209,6 +212,7 @@
     tRP = '13.75ns'
     tRAS = '35ns'
     tRRD = '6ns'
+    tCCD = '5ns'
     tXAW = '30ns'
     activation_limit = 4
     tRFC = '260ns'
@@ -244,6 +248,7 @@
     tRP = '13.09ns'
     tRAS = '33ns'
     tRRD = '5ns'
+    tCCD = '3.752ns'
     tXAW = '25ns'
 
 # A single DDR4-2400 x64 channel (one command and address bus), with
@@ -284,6 +289,8 @@
 
     # Here using the average of RRD_S and RRD_L
     tRRD = '4.1ns'
+    # Here using the average of CCD_S and CCD_L
+    tCCD = '4.166ns'
     tXAW = '21ns'
     activation_limit = 4
     tRFC = '260ns'
@@ -358,6 +365,8 @@
 
     tRRD = '6.0ns'
 
+    tCCD = '6.0ns'
+
     tXAW = '30ns'
     activation_limit = 4
 
@@ -422,6 +431,8 @@
     # Activate to activate irrespective of density and speed grade
     tRRD = '10.0ns'
 
+    tCCD = '3.75ns'
+
     # Irrespective of density, tFAW is 50 ns
     tXAW = '50ns'
     activation_limit = 4
@@ -479,6 +490,8 @@
     # Activate to activate irrespective of density and speed grade
     tRRD = '10.0ns'
 
+    tCCD = '20.0ns'
+
     # Two instead of four activation window
     tXAW = '50ns'
     activation_limit = 2
@@ -542,6 +555,8 @@
     # Activate to activate irrespective of density and speed grade
     tRRD = '10.0ns'
 
+    tCCD = '5.0ns'
+
     # Irrespective of size, tFAW is 50 ns
     tXAW = '50ns'
     activation_limit = 4
diff --git a/src/mem/dram_ctrl.hh b/src/mem/dram_ctrl.hh
--- a/src/mem/dram_ctrl.hh
+++ b/src/mem/dram_ctrl.hh
@@ -11,7 +11,7 @@
  * unmodified and in its entirety in all distributions of the software,
  * modified or unmodified, in source code or in binary form.
  *
- * Copyright (c) 2013 Amin Farmahini-Farahani
+ * Copyright (c) 2013-2014 Amin Farmahini-Farahani
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -482,6 +482,7 @@
     const Tick tRFC;
     const Tick tREFI;
     const Tick tRRD;
+    const Tick tCCD;
     const Tick tXAW;
     const uint32_t activationLimit;
 
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -11,7 +11,7 @@
  * unmodified and in its entirety in all distributions of the software,
  * modified or unmodified, in source code or in binary form.
  *
- * Copyright (c) 2013 Amin Farmahini-Farahani
+ * Copyright (c) 2013-2014 Amin Farmahini-Farahani
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -78,7 +78,7 @@
     tCK(p->tCK), tWTR(p->tWTR), tRTW(p->tRTW), tBURST(p->tBURST),
     tRCD(p->tRCD), tCL(p->tCL), tRP(p->tRP), tRAS(p->tRAS), tWR(p->tWR),
     tRTP(p->tRTP), tRFC(p->tRFC), tREFI(p->tREFI), tRRD(p->tRRD),
-    tXAW(p->tXAW), activationLimit(p->activation_limit),
+    tCCD(p->tCCD), tXAW(p->tXAW), activationLimit(p->activation_limit),
     memSchedPolicy(p->mem_sched_policy), addrMapping(p->addr_mapping),
     pageMgmt(p->page_policy),
     maxAccessesPerRow(p->max_accesses_per_row),
@@ -956,8 +956,8 @@
     assert(dram_pkt->readyTime - busBusyUntil >= tBURST);
 
     // not strictly necessary, but update the time for the next
-    // read/write (add a max with tCCD here)
-    bank.colAllowedAt = cmd_at + tBURST;
+    // read/write
+    bank.colAllowedAt = cmd_at + std::max(tCCD, tBURST);
 
     // If this is a write, we also need to respect the write recovery
     // time before a precharge, in the case of a read, respect the