diff -r 7ed93544cf18 -r 79e027b0eb80 src/arch/arm/isa/insts/data.isa
--- a/src/arch/arm/isa/insts/data.isa	Mon Aug 23 11:34:09 2010 -0500
+++ b/src/arch/arm/isa/insts/data.isa	Mon Aug 23 11:34:26 2010 -0500
@@ -222,13 +222,23 @@
 
     def buildDataInst(mnem, code, flagType = "logic", \
                       aiw = True, regRegAiw = True,
-                      subsPcLr = True):
+                      subsPcLr = True, traceVar = None):
         regRegCode = instCode = code
         if aiw:
             instCode = "AIW" + instCode
             if regRegAiw:
                 regRegCode = "AIW" + regRegCode
 
+        regRegTraceVar = instTraceVar = traceVar
+        if (traceVar != None):
+            if aiw:
+                instTraceVar = "AIW" + traceVar
+                if regRegAiw:
+                    regRegTraceVar = "AIW" + traceVar
+
+            instCode += "if (traceData) { traceData->setData(%s); }" % instTraceVar
+            regRegCode += "if (traceData) { traceData->setData(%s); }" % regRegTraceVar
+
         buildImmDataInst(mnem, instCode, flagType)
         buildRegDataInst(mnem, instCode, flagType)
         buildRegRegDataInst(mnem, regRegCode, flagType)
@@ -240,6 +250,9 @@
             Cpsr = ~CondCodesMask & newCpsr;
             CondCodes = CondCodesMask & newCpsr;
             '''
+            if (traceVar != None):
+                code += " if (traceData) { traceData->setData(%s); }" % traceVar
+
             buildImmDataInst(mnem + 's', code, flagType,
                              suffix = "ImmPclr", buildCc = False,
                              optArgs = ["IsSerializeAfter","IsNonSpeculative"])
@@ -247,30 +260,30 @@
                              suffix = "RegPclr", buildCc = False,
                              optArgs = ["IsSerializeAfter","IsNonSpeculative"])
 
-    buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
-    buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
-    buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub")
-    buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
-    buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add")
+    buildDataInst("and", "Dest = resTemp = Op1 & secondOp;", traceVar = "Dest")
+    buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;", traceVar = "Dest")
+    buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub", traceVar = "Dest")
+    buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb", traceVar = "Dest")
+    buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add", traceVar = "Dest")
     buildImmDataInst("adr", '''
                                Dest = resTemp = (readPC(xc) & ~0x3) +
                                (op1 ? secondOp : -secondOp);
                             ''')
-    buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
-    buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
-    buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
-    buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False)
-    buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False)
-    buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False)
-    buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False)
-    buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
-    buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
-    buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False)
-    buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
-    buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
+    buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add", traceVar = "Dest")
+    buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub", traceVar = "Dest")
+    buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb", traceVar = "Dest")
+    buildDataInst("tst", "resTemp = Op1 & secondOp;", aiw = False, traceVar = "resTemp")
+    buildDataInst("teq", "resTemp = Op1 ^ secondOp;", aiw = False, traceVar = "resTemp")
+    buildDataInst("cmp", "resTemp = Op1 - secondOp;", "sub", aiw = False, traceVar = "resTemp")
+    buildDataInst("cmn", "resTemp = Op1 + secondOp;", "add", aiw = False, traceVar = "resTemp")
+    buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;", traceVar = "Dest")
+    buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False, traceVar = "Dest")
+    buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False, traceVar = "Dest")
+    buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;", traceVar = "Dest")
+    buildDataInst("mvn", "Dest = resTemp = ~secondOp;", traceVar = "Dest")
     buildDataInst("movt",
                   "Dest = resTemp = insertBits(Op1, 31, 16, secondOp);",
-                  aiw = False)
+                  aiw = False, traceVar = "Dest")
 
     buildRegDataInst("qadd", '''
             int32_t midRes;
diff -r 7ed93544cf18 -r 79e027b0eb80 src/arch/arm/isa/insts/ldr.isa
--- a/src/arch/arm/isa/insts/ldr.isa	Mon Aug 23 11:34:09 2010 -0500
+++ b/src/arch/arm/isa/insts/ldr.isa	Mon Aug 23 11:34:26 2010 -0500
@@ -186,7 +186,8 @@
             elif self.flavor == "fp":
                 accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n"
             else:
-                accCode = "IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);"
+                accCode = '''IWDest = cSwap(Mem%s, ((CPSR)Cpsr).e);
+                             if (traceData) { traceData->setData(IWDest); }'''
             accCode = accCode % buildMemSuffix(self.sign, self.size)
 
             self.codeBlobs["memacc_code"] = accCode
diff -r 7ed93544cf18 -r 79e027b0eb80 src/arch/arm/isa/insts/misc.isa
--- a/src/arch/arm/isa/insts/misc.isa	Mon Aug 23 11:34:09 2010 -0500
+++ b/src/arch/arm/isa/insts/misc.isa	Mon Aug 23 11:34:26 2010 -0500
@@ -594,6 +594,7 @@
         return new UndefinedInstruction(false, mnemonic);
 #endif
     Dest = MiscOp1;
+    if (traceData) { traceData->setData(Dest); }
     '''
 
     mrc15Iop = InstObjParams("mrc", "Mrc15", "RegRegOp",
@@ -613,6 +614,7 @@
         return new UndefinedInstruction(false, mnemonic);
 #endif
     MiscDest = Op1;
+    if (traceData) { traceData->setData(MiscDest); }
     '''
     mcr15Iop = InstObjParams("mcr", "Mcr15", "RegRegOp",
                              { "code": mcr15code,