diff -r f6a775d9e95c -r 86309d703e9a src/dev/Pci.py
--- a/src/dev/Pci.py	Tue Aug 19 10:42:56 2014 +0100
+++ b/src/dev/Pci.py	Tue Aug 19 10:44:11 2014 +0100
@@ -98,6 +98,7 @@
     BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
     BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
     BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
+    LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
 
     CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
     SubsystemID = Param.UInt16(0x00, "Subsystem ID")
diff -r f6a775d9e95c -r 86309d703e9a src/dev/pcidev.cc
--- a/src/dev/pcidev.cc	Tue Aug 19 10:42:56 2014 +0100
+++ b/src/dev/pcidev.cc	Tue Aug 19 10:44:11 2014 +0100
@@ -213,7 +213,7 @@
 
     for (int i = 0; i < 6; ++i) {
         if (legacyIO[i]) {
-            BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
+            BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
             config.baseAddr[i] = 0;
         } else {
             BARAddrs[i] = 0;
diff -r f6a775d9e95c -r 86309d703e9a src/dev/x86/SouthBridge.py
--- a/src/dev/x86/SouthBridge.py	Tue Aug 19 10:42:56 2014 +0100
+++ b/src/dev/x86/SouthBridge.py	Tue Aug 19 10:44:11 2014 +0100
@@ -84,6 +84,7 @@
     ide.ProgIF = 0x80
     ide.InterruptLine = 14
     ide.InterruptPin = 1
+    ide.LegacyIOBase = x86IOAddress(0)
 
     def attachIO(self, bus, dma_ports):
         # Route interupt signals