diff -r adaf133a9b00 -r 49feb84a5ba7 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Sat Aug 23 06:13:15 2014 +0100
+++ b/src/cpu/o3/fetch_impl.hh	Sat Aug 23 06:13:16 2014 +0100
@@ -1236,6 +1236,9 @@
     // ended this fetch block.
     bool predictedBranch = false;
 
+    // Need to halt fetch if quiesce instruction detected
+    bool quiesce = false;
+
     TheISA::MachInst *cacheInsts =
         reinterpret_cast<TheISA::MachInst *>(fetchBuffer[tid]);
 
@@ -1246,7 +1249,7 @@
     // Keep issuing while fetchWidth is available and branch is not
     // predicted taken
     while (numInst < fetchWidth && fetchQueue[tid].size() < fetchQueueSize
-           && !predictedBranch) {
+           && !predictedBranch && !quiesce) {
         // We need to process more memory if we aren't going to get a
         // StaticInst from the rom, the current macroop, or what's already
         // in the decoder.
@@ -1363,9 +1366,10 @@
 
             if (instruction->isQuiesce()) {
                 DPRINTF(Fetch,
-                        "Quiesce instruction encountered, halting fetch!");
+                        "Quiesce instruction encountered, halting fetch!\n");
                 fetchStatus[tid] = QuiescePending;
                 status_change = true;
+                quiesce = true;
                 break;
             }
         } while ((curMacroop || decoder[tid]->instReady()) &&