diff -r 79fde1c67ed8 src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py   Wed Aug 13 06:57:36 2014 -0400
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py   Mon Aug 25 16:14:49 2014 +0200
@@ -105,7 +105,7 @@

     rdval t1, "InstRegIndex(MISCREG_FOSEG)"
     st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
-"""
+""" + fxsaveCommonTemplate

 fxsave64Template = """
     rdval t1, "InstRegIndex(MISCREG_FIOFF)"
@@ -113,7 +113,7 @@

     rdval t1, "InstRegIndex(MISCREG_FOOFF)"
     st t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
-"""
+""" + fxsaveCommonTemplate

 fxrstorCommonTemplate = """
     ld t1, seg, %(mode)s, "DISPLACEMENT + 0", dataSize=2
@@ -149,7 +149,7 @@

     ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 4", dataSize=2
     wrval "InstRegIndex(MISCREG_FOSEG)", t1
-"""
+""" + fxrstorCommonTemplate

 fxrstor64Template = """
     limm t2, 0, dataSize=8
@@ -161,7 +161,7 @@
     ld t1, seg, %(mode)s, "DISPLACEMENT + 16 + 0", dataSize=8
     wrval "InstRegIndex(MISCREG_FOOFF)", t1
     wrval "InstRegIndex(MISCREG_FOSEG)", t2
-"""
+""" + fxrstorCommonTemplate

 microcode = '''
 def macroop FXSAVE_M {