diff -r 219bc108ab2b -r 16921ef15015 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh	Tue May 13 12:20:49 2014 -0500
+++ b/src/mem/cache/base.hh	Wed Aug 27 17:21:15 2014 +0100
@@ -182,7 +182,10 @@
 
       private:
 
-        EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
+        void processSendRetry();
+
+        EventWrapper<CacheSlavePort,
+                     &CacheSlavePort::processSendRetry> sendRetryEvent;
 
     };
 
diff -r 219bc108ab2b -r 16921ef15015 src/mem/cache/base.cc
--- a/src/mem/cache/base.cc	Tue May 13 12:20:49 2014 -0500
+++ b/src/mem/cache/base.cc	Wed Aug 27 17:21:15 2014 +0100
@@ -106,13 +106,20 @@
     DPRINTF(CachePort, "Cache port %s accepting new requests\n", name());
     blocked = false;
     if (mustSendRetry) {
-        DPRINTF(CachePort, "Cache port %s sending retry\n", name());
-        mustSendRetry = false;
         // @TODO: need to find a better time (next bus cycle?)
         owner.schedule(sendRetryEvent, curTick() + 1);
     }
 }
 
+void
+BaseCache::CacheSlavePort::processSendRetry()
+{
+    DPRINTF(CachePort, "Cache port %s sending retry\n", name());
+
+    // reset the flag and call retry
+    mustSendRetry = false;
+    sendRetry();
+}
 
 void
 BaseCache::init()
diff -r 219bc108ab2b -r 16921ef15015 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Tue May 13 12:20:49 2014 -0500
+++ b/src/mem/cache/cache_impl.hh	Wed Aug 27 17:21:15 2014 +0100
@@ -1937,16 +1937,27 @@
 bool
 Cache<TagStore>::CpuSidePort::recvTimingReq(PacketPtr pkt)
 {
-    // always let inhibited requests through even if blocked
-    if (!pkt->memInhibitAsserted() && blocked) {
-        assert(!cache->system->bypassCaches());
-        DPRINTF(Cache,"Scheduling a retry while blocked\n");
-        mustSendRetry = true;
-        return false;
+    assert(!cache->system->bypassCaches());
+
+    bool success = false;
+
+    // always let inhibited requests through, even if blocked
+    if (pkt->memInhibitAsserted()) {
+        // this should always succeed
+        success = cache->recvTimingReq(pkt);
+        assert(success);
+    } else if (blocked || mustSendRetry) {
+        // either already committed to send a retry, or blocked
+        success = false;
+    } else {
+        // for now this should always succeed
+        success = cache->recvTimingReq(pkt);
+        assert(success);
     }
 
-    cache->recvTimingReq(pkt);
-    return true;
+    // remember if we have to retry
+    mustSendRetry = !success;
+    return success;
 }
 
 template<class TagStore>