diff -r 9ac621f9c6c0 -r 2176929f58ad src/arch/x86/isa/decoder/two_byte_opcodes.isa
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa	Thu Aug 28 08:37:21 2014 +0100
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa	Thu Aug 28 08:37:22 2014 +0100
@@ -141,13 +141,13 @@
                         }}, IsNonSpeculative);
                         0x01: m5quiesce({{
                             PseudoInst::quiesce(xc->tcBase());
-                        }}, IsNonSpeculative);
+                        }}, IsNonSpeculative, IsQuiesce);
                         0x02: m5quiesceNs({{
                             PseudoInst::quiesceNs(xc->tcBase(), Rdi);
-                        }}, IsNonSpeculative);
+                        }}, IsNonSpeculative, IsQuiesce);
                         0x03: m5quiesceCycle({{
                             PseudoInst::quiesceCycles(xc->tcBase(), Rdi);
-                        }}, IsNonSpeculative);
+                        }}, IsNonSpeculative, IsQuiesce);
                         0x04: m5quiesceTime({{
                             Rax = PseudoInst::quiesceTime(xc->tcBase());
                         }}, IsNonSpeculative);
diff -r 9ac621f9c6c0 -r 2176929f58ad src/arch/x86/isa/microops/specop.isa
--- a/src/arch/x86/isa/microops/specop.isa	Thu Aug 28 08:37:21 2014 +0100
+++ b/src/arch/x86/isa/microops/specop.isa	Thu Aug 28 08:37:22 2014 +0100
@@ -63,7 +63,8 @@
         MicroHalt(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags) :
             X86MicroopBase(_machInst, "halt", instMnem,
-                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative),
+                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
+                           (ULL(1) << StaticInst::IsQuiesce),
                            No_OpClass)
         {
         }