diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/faults.hh
--- a/src/arch/alpha/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -34,6 +34,7 @@
 
 #include "arch/alpha/pagetable.hh"
 #include "config/full_system.hh"
+#include "mem/request.hh"
 #include "sim/faults.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
@@ -49,7 +50,8 @@
     virtual bool setRestartAddress() {return true;}
   public:
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -116,7 +118,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -151,7 +154,8 @@
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -170,7 +174,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -249,7 +254,8 @@
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -266,7 +272,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/faults.cc
--- a/src/arch/alpha/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -109,7 +109,7 @@
 #if FULL_SYSTEM
 
 void
-AlphaFault::invoke(ThreadContext *tc)
+AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
     countStat()++;
@@ -129,14 +129,14 @@
 }
 
 void
-ArithmeticFault::invoke(ThreadContext *tc)
+ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
 void
-DtbFault::invoke(ThreadContext *tc)
+DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // Set fault address and flags.  Even though we're modeling an
     // EV5, we use the EV6 technique of not latching fault registers
@@ -149,9 +149,10 @@
         tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
         // set MM_STAT register flags
+        MachInst machInst = inst->machInst;
         tc->setMiscRegNoEffect(IPR_MM_STAT,
-            (((Opcode(tc->getInst()) & 0x3f) << 11) |
-             ((Ra(tc->getInst()) & 0x1f) << 6) |
+            (((Opcode(machInst) & 0x3f) << 11) |
+             ((Ra(machInst) & 0x1f) << 6) |
              (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
@@ -163,7 +164,7 @@
 }
 
 void
-ItbFault::invoke(ThreadContext *tc)
+ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!tc->misspeculating()) {
         tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
@@ -177,7 +178,7 @@
 #else
 
 void
-ItbPageFault::invoke(ThreadContext *tc)
+ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -191,7 +192,7 @@
 }
 
 void
-NDtbMissFault::invoke(ThreadContext *tc)
+NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/isa.cc
--- a/src/arch/alpha/isa.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/isa.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -28,6 +28,8 @@
  * Authors: Gabe Black
  */
 
+#include <assert.h>
+
 #include "arch/alpha/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/process.cc
--- a/src/arch/alpha/process.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/process.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -36,6 +36,7 @@
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
+#include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/tlb.hh
--- a/src/arch/alpha/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -40,9 +40,9 @@
 #include "arch/alpha/utility.hh"
 #include "arch/alpha/vtophys.hh"
 #include "base/statistics.hh"
+#include "base/types.hh"
 #include "mem/request.hh"
 #include "params/AlphaTLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/alpha/tru64/process.cc
--- a/src/arch/alpha/tru64/process.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/alpha/tru64/process.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -34,6 +34,7 @@
 #include "arch/alpha/tru64/process.hh"
 #include "cpu/thread_context.hh"
 #include "kern/tru64/tru64.hh"
+#include "sim/byteswap.hh"
 #include "sim/process.hh"
 #include "sim/syscall_emul.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/faults.hh
--- a/src/arch/arm/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -108,7 +108,8 @@
     };
 
 #if FULL_SYSTEM
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual FaultStat& countStat() = 0;
     virtual FaultOffset offset() = 0;
@@ -140,7 +141,8 @@
 #if FULL_SYSTEM
 {
   public:
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 #else
 {};
@@ -165,7 +167,8 @@
     {
     }
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -179,7 +182,8 @@
     SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
     {}
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -199,7 +203,8 @@
         domain(_domain), status(_status)
     {}
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class PrefetchAbort : public AbortFault<PrefetchAbort>
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/faults.cc
--- a/src/arch/arm/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -94,7 +94,7 @@
 #if FULL_SYSTEM
 
 void 
-ArmFault::invoke(ThreadContext *tc)
+ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // ARM ARM B1.6.3
     FaultBase::invoke(tc);
@@ -150,7 +150,7 @@
 }
 
 void
-Reset::invoke(ThreadContext *tc)
+Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     tc->getCpuPtr()->clearInterrupts();
     tc->clearArchRegs();
@@ -160,7 +160,7 @@
 #else
 
 void
-UndefinedInstruction::invoke(ThreadContext *tc)
+UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // If the mnemonic isn't defined this has to be an unknown instruction.
     assert(unknown || mnemonic != NULL);
@@ -177,7 +177,7 @@
 }
 
 void
-SupervisorCall::invoke(ThreadContext *tc)
+SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // As of now, there isn't a 32 bit thumb version of this instruction.
     assert(!machInst.bigThumb);
@@ -203,7 +203,7 @@
 
 template<class T>
 void
-AbortFault<T>::invoke(ThreadContext *tc)
+AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     ArmFaultVals<T>::invoke(tc);
     FSR fsr = 0;
@@ -229,8 +229,10 @@
     tc->setNextMicroPC(1);
 }
 
-template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc);
-template void AbortFault<DataAbort>::invoke(ThreadContext *tc);
+template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
+                                                StaticInstPtr inst);
+template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
+                                            StaticInstPtr inst);
 
 // return via SUBS pc, lr, xxx; rfe, movs, ldm
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/isa.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -39,6 +39,7 @@
  */
 
 #include "arch/arm/isa.hh"
+#include "sim/faults.hh"
 
 namespace ArmISA
 {
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/isa/includes.isa
--- a/src/arch/arm/isa/includes.isa	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/isa/includes.isa	Tue Aug 31 16:44:49 2010 -0700
@@ -59,6 +59,7 @@
 #include "arch/arm/insts/vfp.hh"
 #include "arch/arm/isa_traits.hh"
 #include "mem/packet.hh"
+#include "sim/faults.hh"
 }};
 
 output decoder {{
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/nativetrace.cc
--- a/src/arch/arm/nativetrace.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/nativetrace.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -45,6 +45,7 @@
 #include "arch/arm/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "params/ArmNativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/process.cc
--- a/src/arch/arm/process.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/process.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -50,6 +50,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/translating_port.hh"
+#include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/table_walker.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -44,11 +44,11 @@
 
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/tlb.hh"
+#include "base/types.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "mem/request.hh"
 #include "params/ArmTableWalker.hh"
-#include "sim/faults.hh"
 #include "sim/eventq.hh"
 
 class DmaPort;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -50,9 +50,9 @@
 #include "arch/arm/vtophys.hh"
 #include "arch/arm/pagetable.hh"
 #include "base/statistics.hh"
+#include "base/types.hh"
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/arm/utility.hh
--- a/src/arch/arm/utility.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/arm/utility.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -48,6 +48,7 @@
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "base/hashmap.hh"
+#include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/mips/faults.hh
--- a/src/arch/mips/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/mips/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -53,7 +53,9 @@
     Addr entryHiVPN2X;
     Addr contextBadVPN2;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc) {};
+    void invoke(ThreadContext * tc,
+            StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
+    {}
     void setExceptionState(ThreadContext *, uint8_t);
     void setHandlerPC(Addr, ThreadContext *);
 #endif
@@ -111,7 +113,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 
 };
@@ -127,7 +130,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -155,7 +159,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class TLBInvalidIFetchFault : public MipsFault
@@ -169,7 +174,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class NDtbMissFault : public MipsFault
@@ -231,7 +237,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 
@@ -257,7 +264,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
 };
 
@@ -271,7 +279,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class SoftResetFault : public MipsFault
@@ -284,7 +293,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class DebugSingleStep : public MipsFault
@@ -297,7 +307,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class DebugInterrupt : public MipsFault
@@ -310,7 +321,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class CoprocessorUnusableFault : public MipsFault
@@ -324,7 +336,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     CoprocessorUnusableFault(int _procid){ coProcID = _procid;}
 };
 
@@ -338,7 +351,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class ThreadFault : public MipsFault
@@ -351,7 +365,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class ArithmeticFault : public MipsFault
@@ -367,7 +382,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -385,7 +401,8 @@
     FaultStat & countStat() {return _count;}
 
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -400,7 +417,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -415,7 +433,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -430,7 +449,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -445,7 +465,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -460,7 +481,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -475,7 +497,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -490,7 +513,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -505,7 +529,8 @@
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInst::StaticInstPtr inst = nullStaticInstPtr);
 #endif
 };
 
@@ -567,7 +592,8 @@
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 } // MipsISA namespace
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/mips/faults.cc
--- a/src/arch/mips/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/mips/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -216,7 +216,7 @@
 }
 
 void
-ArithmeticFault::invoke(ThreadContext *tc)
+ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0xC);
@@ -236,7 +236,7 @@
 }
 
 void
-StoreAddressErrorFault::invoke(ThreadContext *tc)
+StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x5);
@@ -250,7 +250,7 @@
 }
 
 void
-TrapFault::invoke(ThreadContext *tc)
+TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0xD);
@@ -263,7 +263,7 @@
 }
 
 void
-BreakpointFault::invoke(ThreadContext *tc)
+BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     setExceptionState(tc, 0x9);
 
@@ -275,7 +275,7 @@
 }
 
 void
-DtbInvalidFault::invoke(ThreadContext *tc)
+DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
 
@@ -300,7 +300,7 @@
 }
 
 void
-AddressErrorFault::invoke(ThreadContext *tc)
+AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x4);
@@ -314,7 +314,7 @@
 }
 
 void
-ItbInvalidFault::invoke(ThreadContext *tc)
+ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x2);
@@ -340,7 +340,7 @@
 }
 
 void
-ItbRefillFault::invoke(ThreadContext *tc)
+ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
     Addr HandlerBase;
@@ -370,7 +370,7 @@
 }
 
 void
-DtbRefillFault::invoke(ThreadContext *tc)
+DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // Set new PC
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -403,7 +403,7 @@
 }
 
 void
-TLBModifiedFault::invoke(ThreadContext *tc)
+TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
@@ -427,7 +427,7 @@
 }
 
 void
-SystemCallFault::invoke(ThreadContext *tc)
+SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x8);
@@ -440,7 +440,7 @@
 }
 
 void
-InterruptFault::invoke(ThreadContext *tc)
+InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if  FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -463,7 +463,7 @@
 #endif // FULL_SYSTEM
 
 void
-ResetFault::invoke(ThreadContext *tc)
+ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -481,7 +481,7 @@
 }
 
 void
-ReservedInstructionFault::invoke(ThreadContext *tc)
+ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if  FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -496,21 +496,21 @@
 }
 
 void
-ThreadFault::invoke(ThreadContext *tc)
+ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     panic("%s encountered.\n", name());
 }
 
 void
-DspStateDisabledFault::invoke(ThreadContext *tc)
+DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     panic("%s encountered.\n", name());
 }
 
 void
-CoprocessorUnusableFault::invoke(ThreadContext *tc)
+CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/mips/isa.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -37,8 +37,8 @@
 
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
+#include "base/types.hh"
 #include "sim/eventq.hh"
-#include "sim/faults.hh"
 
 class BaseCPU;
 class Checkpoint;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/mips/tlb.hh
--- a/src/arch/mips/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/mips/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -42,9 +42,9 @@
 #include "arch/mips/vtophys.hh"
 #include "arch/mips/pagetable.hh"
 #include "base/statistics.hh"
+#include "base/types.hh"
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/mips/utility.cc
--- a/src/arch/mips/utility.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/mips/utility.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -28,6 +28,8 @@
  * Authors: Korey Sewell
  */
 
+#include <math.h>
+
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
 #include "config/full_system.hh"
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/power/tlb.hh
--- a/src/arch/power/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/power/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -44,9 +44,9 @@
 #include "arch/power/vtophys.hh"
 #include "arch/power/pagetable.hh"
 #include "base/statistics.hh"
+#include "base/types.hh"
 #include "mem/request.hh"
 #include "params/PowerTLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/faults.hh
--- a/src/arch/sparc/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -33,6 +33,7 @@
 #define __SPARC_FAULTS_HH__
 
 #include "config/full_system.hh"
+#include "cpu/static_inst.hh"
 #include "sim/faults.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
@@ -66,7 +67,8 @@
         FaultStat count;
     };
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual TrapType trapType() = 0;
     virtual FaultPriority priority() = 0;
@@ -92,7 +94,10 @@
 
 class PowerOnReset : public SparcFault<PowerOnReset>
 {
-    void invoke(ThreadContext * tc);
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+#endif
 };
 
 class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -210,7 +215,8 @@
   public:
     FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -222,7 +228,8 @@
   public:
     FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -242,7 +249,8 @@
     SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
     //These need to be handled specially to enable spill traps in SE
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -258,7 +266,8 @@
     FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) {;}
     //These need to be handled specially to enable fill traps in SE
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -274,7 +283,8 @@
     TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;}
     //In SE, trap instructions are requesting services from the OS.
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/faults.cc
--- a/src/arch/sparc/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -505,7 +505,7 @@
 
 #if FULL_SYSTEM
 
-void SparcFaultBase::invoke(ThreadContext * tc)
+void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     //panic("Invoking a second fault!\n");
     FaultBase::invoke(tc);
@@ -559,7 +559,7 @@
     tc->setNextNPC(NPC + sizeof(MachInst));
 }
 
-void PowerOnReset::invoke(ThreadContext * tc)
+void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     //For SPARC, when a system is first started, there is a power
     //on reset Trap which sets the processor into the following state.
@@ -620,7 +620,8 @@
 
 #else // !FULL_SYSTEM
 
-void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
+void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
+                                          StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -634,7 +635,7 @@
     }
 }
 
-void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
+void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -652,7 +653,7 @@
     }
 }
 
-void SpillNNormal::invoke(ThreadContext *tc)
+void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     doNormalFault(tc, trapType(), false);
 
@@ -669,7 +670,7 @@
     tc->setNextNPC(spillStart + 2*sizeof(MachInst));
 }
 
-void FillNNormal::invoke(ThreadContext *tc)
+void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     doNormalFault(tc, trapType(), false);
 
@@ -686,7 +687,7 @@
     tc->setNextNPC(fillStart + 2*sizeof(MachInst));
 }
 
-void TrapInstruction::invoke(ThreadContext *tc)
+void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     //In SE, this mechanism is how the process requests a service from the
     //operating system. We'll get the process object from the thread context
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/nativetrace.cc
--- a/src/arch/sparc/nativetrace.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/nativetrace.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -33,6 +33,7 @@
 #include "arch/sparc/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "params/SparcNativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/remote_gdb.cc
--- a/src/arch/sparc/remote_gdb.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/remote_gdb.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -133,6 +133,7 @@
 #include "mem/page_table.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
+#include "sim/byteswap.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/tlb.hh
--- a/src/arch/sparc/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -34,10 +34,10 @@
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
 #include "base/misc.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
 #include "params/SparcTLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/tlb.cc
--- a/src/arch/sparc/tlb.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/tlb.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -31,6 +31,7 @@
 #include <cstring>
 
 #include "arch/sparc/asi.hh"
+#include "arch/sparc/faults.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/utility.hh
--- a/src/arch/sparc/utility.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/utility.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -31,11 +31,11 @@
 #ifndef __ARCH_SPARC_UTILITY_HH__
 #define __ARCH_SPARC_UTILITY_HH__
 
-#include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/misc.hh"
+#include "base/types.hh"
 #include "base/bitfield.hh"
 #include "cpu/thread_context.hh"
 
@@ -57,14 +57,7 @@
     template <class TC>
     void zeroRegisters(TC *tc);
 
-    inline void
-    initCPU(ThreadContext *tc, int cpuId)
-    {
-        static Fault por = new PowerOnReset();
-        if (cpuId == 0)
-            por->invoke(tc);
-
-    }
+    void initCPU(ThreadContext *tc, int cpuId);
 
     inline void
     startupCPU(ThreadContext *tc, int cpuId)
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/sparc/utility.cc
--- a/src/arch/sparc/utility.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/sparc/utility.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/sparc/faults.hh"
 #include "arch/sparc/utility.hh"
 #if FULL_SYSTEM
 #include "arch/sparc/vtophys.hh"
@@ -216,4 +217,13 @@
     dest->setNextPC(src->readNextPC());
     dest->setNextNPC(src->readNextNPC());
 }
+
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+    static Fault por = new PowerOnReset();
+    if (cpuId == 0)
+        por->invoke(tc);
+}
+
 } //namespace SPARC_ISA
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/x86/faults.hh
--- a/src/arch/x86/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/x86/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -86,7 +86,8 @@
         }
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
         virtual std::string describe() const;
 #endif
@@ -114,7 +115,8 @@
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     };
 
@@ -128,7 +130,8 @@
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     };
 
@@ -150,7 +153,8 @@
             return "unimplemented_micro";
         }
 
-        void invoke(ThreadContext * tc)
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr)
         {
             panic("Unimplemented instruction!");
         }
@@ -327,7 +331,8 @@
             errorCode = code;
         }
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
 #if FULL_SYSTEM
         virtual std::string describe() const;
@@ -397,7 +402,8 @@
             X86Interrupt("INIT Interrupt", "#INIT", _vector)
         {}
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     };
 
     class StartupInterrupt : public X86Interrupt
@@ -407,7 +413,8 @@
             X86Interrupt("Startup Interrupt", "#SIPI", _vector)
         {}
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     };
 
     class SoftwareInterrupt : public X86Interrupt
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/x86/faults.cc
--- a/src/arch/x86/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/x86/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -56,7 +56,7 @@
 namespace X86ISA
 {
 #if FULL_SYSTEM
-    void X86FaultBase::invoke(ThreadContext * tc)
+    void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         Addr pc = tc->readPC();
         DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
@@ -102,7 +102,7 @@
         return ss.str();
     }
     
-    void X86Trap::invoke(ThreadContext * tc)
+    void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         X86FaultBase::invoke(tc);
         // This is the same as a fault, but it happens -after- the instruction.
@@ -111,12 +111,12 @@
         tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
     }
 
-    void X86Abort::invoke(ThreadContext * tc)
+    void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         panic("Abort exception!");
     }
 
-    void PageFault::invoke(ThreadContext * tc)
+    void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
         X86FaultBase::invoke(tc);
@@ -141,7 +141,7 @@
     }
 
     void
-    InitInterrupt::invoke(ThreadContext *tc)
+    InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
     {
         DPRINTF(Faults, "Init interrupt.\n");
         // The otherwise unmodified integer registers should be set to 0.
@@ -248,7 +248,7 @@
     }
 
     void
-    StartupInterrupt::invoke(ThreadContext *tc)
+    StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
     {
         DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
         HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
@@ -270,7 +270,7 @@
 #else
 
     void
-    PageFault::invoke(ThreadContext * tc)
+    PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         PageFaultErrorCode code = errorCode;
         const char *modeStr = "";
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/x86/insts/microldstop.hh
--- a/src/arch/x86/insts/microldstop.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/x86/insts/microldstop.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -43,6 +43,7 @@
 #include "arch/x86/insts/microop.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
+#include "sim/faults.hh"
 
 namespace X86ISA
 {
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/x86/nativetrace.cc
--- a/src/arch/x86/nativetrace.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/x86/nativetrace.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -34,6 +34,7 @@
 #include "arch/x86/regs/int.hh"
 #include "cpu/thread_context.hh"
 #include "params/X86NativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/arch/x86/tlb.hh
--- a/src/arch/x86/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/arch/x86/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -46,11 +46,11 @@
 
 #include "arch/x86/pagetable.hh"
 #include "arch/x86/regs/segment.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/faults.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/base/types.hh
--- a/src/base/types.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/base/types.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -39,6 +39,8 @@
 
 #include <inttypes.h>
 
+#include "base/refcnt.hh"
+
 /** uint64_t constant */
 #define ULL(N)          ((uint64_t)N##ULL)
 /** int64_t constant */
@@ -75,4 +77,7 @@
 typedef int16_t ThreadID;
 const ThreadID InvalidThreadID = (ThreadID)-1;
 
+class FaultBase;
+typedef RefCountingPtr<FaultBase> Fault;
+
 #endif // __BASE_TYPES_HH__
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/base_dyn_inst.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -49,6 +49,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
 #include "mem/packet.hh"
+#include "sim/byteswap.hh"
 #include "sim/system.hh"
 #include "sim/tlb.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/checker/cpu_impl.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -240,7 +240,7 @@
 
         if (fault != NoFault) {
 #if FULL_SYSTEM
-            fault->invoke(tc);
+            fault->invoke(tc, curStaticInst);
             willChangePC = true;
             newPC = thread->readPC();
             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/cpu.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -347,8 +347,8 @@
     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
      *  trapCPU() - Traps to handle given fault
      */
-    void trap(Fault fault, ThreadID tid, int delay = 0);
-    void trapCPU(Fault fault, ThreadID tid);
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
+    void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 
     /** Add Thread to Active Threads List. */
     void activateContext(ThreadID tid, int delay = 0);
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/cpu.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -136,7 +136,7 @@
         break;
 
       case Trap:
-        cpu->trapCPU(fault, tid);
+        cpu->trapCPU(fault, tid, inst);
         break;
 
       default:
@@ -649,16 +649,16 @@
 #endif
 
 void
-InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
+InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 {
     //@ Squash Pipeline during TRAP
-    scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
+    scheduleCpuEvent(Trap, fault, tid, inst, delay);
 }
 
 void
-InOrderCPU::trapCPU(Fault fault, ThreadID tid)
+InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 {
-    fault->invoke(tcBase(tid));
+    fault->invoke(tcBase(tid), inst->staticInst);
 }
 
 void 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/inorder_dyn_inst.cc
--- a/src/cpu/inorder/inorder_dyn_inst.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/inorder_dyn_inst.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -326,7 +326,7 @@
 void
 InOrderDynInst::trap(Fault fault)
 {
-    this->cpu->trap(fault, this->threadNumber);
+    this->cpu->trap(fault, this->threadNumber, this);
 }
 
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/resources/cache_unit.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -434,7 +434,7 @@
 
         scheduleEvent(slot_idx, 1);
 
-        cpu->trap(cache_req->fault, tid);
+        cpu->trap(cache_req->fault, tid, inst);
     } else {
         DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
                 "to phys. addr:%08p.\n", tid, inst->seqNum,
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/resources/execution_unit.cc
--- a/src/cpu/inorder/resources/execution_unit.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/resources/execution_unit.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -236,7 +236,7 @@
                 } else {
                     warn("inst [sn:%i] had a %s fault",
                          seq_num, fault->name());
-                    cpu->trap(fault, tid);
+                    cpu->trap(fault, tid, inst);
                 }
             }
         }
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/resources/mult_div_unit.cc
--- a/src/cpu/inorder/resources/mult_div_unit.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/resources/mult_div_unit.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -301,7 +301,7 @@
                 inst->readTid(), inst->readIntResult(0));
     } else {
         warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
-        cpu->trap(fault, tid);
+        cpu->trap(fault, tid, inst);
     }    
 }
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/inorder/resources/tlb_unit.cc
--- a/src/cpu/inorder/resources/tlb_unit.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/inorder/resources/tlb_unit.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -176,7 +176,7 @@
                     scheduleEvent(slot_idx, 1);
 
                     // Let CPU handle the fault
-                    cpu->trap(tlb_req->fault, tid);
+                    cpu->trap(tlb_req->fault, tid, inst);
                 }
             } else {
                 DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/o3/commit_impl.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -1068,7 +1068,7 @@
         // needed to update the state as soon as possible.  This
         // prevents external agents from changing any specific state
         // that the trap need.
-        cpu->trap(inst_fault, tid);
+        cpu->trap(inst_fault, tid, head_inst);
 
         // Exit state update mode to avoid accidental updating.
         thread[tid]->inSyscall = false;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/o3/cpu.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -367,7 +367,7 @@
     { return globalSeqNum++; }
 
     /** Traps to handle given fault. */
-    void trap(Fault fault, ThreadID tid);
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
 #if FULL_SYSTEM
     /** HW return from error interrupt. */
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/o3/cpu.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -926,7 +926,8 @@
     this->interrupts->updateIntrInfo(this->threadContexts[0]);
 
     DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
-    this->trap(interrupt, 0);
+    DynInstPtr dummyInst;
+    this->trap(interrupt, 0, dummyInst);
 }
 
 template <class Impl>
@@ -943,10 +944,10 @@
 
 template <class Impl>
 void
-FullO3CPU<Impl>::trap(Fault fault, ThreadID tid)
+FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     // Pass the thread's TC into the invoke method.
-    fault->invoke(this->threadContexts[tid]);
+    fault->invoke(this->threadContexts[tid], inst->staticInst);
 }
 
 #if !FULL_SYSTEM
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/o3/dyn_inst_impl.hh
--- a/src/cpu/o3/dyn_inst_impl.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/o3/dyn_inst_impl.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -155,7 +155,7 @@
 void
 BaseO3DynInst<Impl>::trap(Fault fault)
 {
-    this->cpu->trap(fault, this->threadNumber);
+    this->cpu->trap(fault, this->threadNumber, this);
 }
 
 template <class Impl>
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/simple/atomic.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -38,6 +38,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/AtomicSimpleCPU.hh"
+#include "sim/faults.hh"
 #include "sim/system.hh"
 
 using namespace std;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/simple/base.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -506,7 +506,7 @@
     fetchOffset = 0;
     if (fault != NoFault) {
         curMacroStaticInst = StaticInst::nullStaticInstPtr;
-        fault->invoke(tc);
+        fault->invoke(tc, curStaticInst);
         predecoder.reset();
     } else {
         //If we're at the last micro op for this instruction
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/simple/timing.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -38,6 +38,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/TimingSimpleCPU.hh"
+#include "sim/faults.hh"
 #include "sim/system.hh"
 
 using namespace std;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/simple_thread.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -241,13 +241,6 @@
 
     virtual bool misspeculating();
 
-    Fault instRead(RequestPtr &req)
-    {
-        panic("instRead not implemented");
-        // return funcPhysMem->read(req, inst);
-        return NoFault;
-    }
-
     void copyArchRegs(ThreadContext *tc);
 
     void clearArchRegs()
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/static_inst.hh
--- a/src/cpu/static_inst.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/static_inst.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -43,8 +43,6 @@
 #include "base/refcnt.hh"
 #include "base/types.hh"
 #include "cpu/op_class.hh"
-#include "sim/faults.hh"
-#include "sim/faults.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/thread_context.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -36,9 +36,6 @@
 #include "base/types.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
-#include "mem/request.hh"
-#include "sim/byteswap.hh"
-#include "sim/faults.hh"
 #include "sim/serialize.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/cpu/translation.hh
--- a/src/cpu/translation.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/cpu/translation.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -33,6 +33,7 @@
 #ifndef __CPU_TRANSLATION_HH__
 #define __CPU_TRANSLATION_HH__
 
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 /**
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/kern/kernel_stats.hh
--- a/src/kern/kernel_stats.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/kern/kernel_stats.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -35,6 +35,7 @@
 #include <string>
 
 #include "cpu/static_inst.hh"
+#include "sim/stats.hh"
 #include "sim/serialize.hh"
 
 class BaseCPU;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/kern/tru64/tru64.hh
--- a/src/kern/tru64/tru64.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/kern/tru64/tru64.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -34,6 +34,7 @@
 
 #include "config/full_system.hh"
 #include "kern/operatingsystem.hh"
+#include "sim/byteswap.hh"
 
 #if FULL_SYSTEM
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/mem/page_table.hh
--- a/src/mem/page_table.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/mem/page_table.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -44,7 +44,6 @@
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "mem/request.hh"
-#include "sim/faults.hh"
 #include "sim/serialize.hh"
 
 class Process;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/mem/page_table.cc
--- a/src/mem/page_table.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/mem/page_table.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -38,12 +38,12 @@
 #include <map>
 #include <fstream>
 
-#include "arch/faults.hh"
 #include "base/bitfield.hh"
 #include "base/intmath.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "mem/page_table.hh"
+#include "sim/faults.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/faults.hh
--- a/src/sim/faults.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/faults.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -33,12 +33,15 @@
 #define __FAULTS_HH__
 
 #include "base/refcnt.hh"
+#include "base/types.hh"
 #include "sim/stats.hh"
 #include "config/full_system.hh"
+#include "cpu/static_inst.hh"
+
+// The Fault type is defined in base/types.hh to avoid circular dependencies
+// among header files.
 
 class ThreadContext;
-class FaultBase;
-typedef RefCountingPtr<FaultBase> Fault;
 
 typedef const char * FaultName;
 typedef Stats::Scalar FaultStat;
@@ -54,7 +57,8 @@
 {
   public:
     virtual FaultName name() const = 0;
-    virtual void invoke(ThreadContext * tc);
+    virtual void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     virtual bool isMachineCheckFault() const {return false;}
     virtual bool isAlignmentFault() const {return false;}
 };
@@ -71,7 +75,8 @@
     { }
 
     FaultName name() const {return "Unimplemented simulator feature";}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 #if !FULL_SYSTEM
@@ -82,7 +87,8 @@
   public:
     FaultName name() const {return "Generic page table fault";}
     GenericPageTableFault(Addr va) : vaddr(va) {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class GenericAlignmentFault : public FaultBase
@@ -92,7 +98,8 @@
   public:
     FaultName name() const {return "Generic alignment fault";}
     GenericAlignmentFault(Addr va) : vaddr(va) {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 #endif
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/faults.cc
--- a/src/sim/faults.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/faults.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -38,12 +38,12 @@
 #include "mem/page_table.hh"
 
 #if !FULL_SYSTEM
-void FaultBase::invoke(ThreadContext * tc)
+void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     panic("fault (%s) detected @ PC %p", name(), tc->readPC());
 }
 #else
-void FaultBase::invoke(ThreadContext * tc)
+void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC());
 
@@ -51,13 +51,13 @@
 }
 #endif
 
-void UnimpFault::invoke(ThreadContext * tc)
+void UnimpFault::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     panic("Unimpfault: %s\n", panicStr.c_str());
 }
 
 #if !FULL_SYSTEM
-void GenericPageTableFault::invoke(ThreadContext *tc)
+void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
 
@@ -66,7 +66,7 @@
 
 }
 
-void GenericAlignmentFault::invoke(ThreadContext *tc)
+void GenericAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     panic("Alignment fault when accessing virtual address %#x\n", vaddr);
 }
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/process_impl.hh
--- a/src/sim/process_impl.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/process_impl.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -45,6 +45,7 @@
 #include <vector>
 
 #include "mem/translating_port.hh"
+#include "sim/byteswap.hh"
 
 
 //This needs to be templated for cases where 32 bit pointers are needed.
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/syscall_emul.hh
--- a/src/sim/syscall_emul.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/syscall_emul.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -62,6 +62,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/translating_port.hh"
 #include "mem/page_table.hh"
+#include "sim/byteswap.hh"
 #include "sim/system.hh"
 #include "sim/process.hh"
 
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/tlb.hh
--- a/src/sim/tlb.hh	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/tlb.hh	Tue Aug 31 16:44:49 2010 -0700
@@ -32,8 +32,8 @@
 #define __SIM_TLB_HH__
 
 #include "base/misc.hh"
+#include "base/types.hh"
 #include "mem/request.hh"
-#include "sim/faults.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;
diff -r c1b66fc648e2 -r c7e1541bb5e6 src/sim/tlb.cc
--- a/src/sim/tlb.cc	Tue Aug 31 09:50:49 2010 -0700
+++ b/src/sim/tlb.cc	Tue Aug 31 16:44:49 2010 -0700
@@ -31,6 +31,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 Fault