diff -r 6f4a19eeaea0 -r 8111a8da1938 tests/configs/arm_generic.py
--- a/tests/configs/arm_generic.py	Wed Sep 10 08:56:12 2014 +0100
+++ b/tests/configs/arm_generic.py	Wed Sep 10 08:56:27 2014 +0100
@@ -43,6 +43,25 @@
 import FSConfig
 from Caches import *
 from base_config import *
+from O3_ARM_v7a import *
+
+class ArmSESystemUniprocessor(BaseSESystemUniprocessor):
+    """Syscall-emulation builder for ARM uniprocessor systems.
+
+    A small tweak of the syscall-emulation builder to use more
+    representative cache configurations.
+    """
+
+    def __init__(self, **kwargs):
+        BaseSESystem.__init__(self, **kwargs)
+
+    def create_caches_private(self, cpu):
+        # The atomic SE configurations do not use caches
+        if self.mem_mode == "timing":
+            # Use the more representative cache configuration
+            cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
+                                          O3_ARM_v7a_DCache(),
+                                          O3_ARM_v7aL2())
 
 class LinuxArmSystemBuilder(object):
     """Mix-in that implements create_system.
@@ -87,6 +106,12 @@
         BaseSystem.__init__(self, **kwargs)
         LinuxArmSystemBuilder.__init__(self, machine_type)
 
+    def create_caches_private(self, cpu):
+        # Use the more representative cache configuration
+        cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
+                                      O3_ARM_v7a_DCache(),
+                                      O3_ARM_v7aL2())
+
 class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder,
                                    BaseFSSystemUniprocessor):
     """Basic ARM full system builder for uniprocessor systems.
@@ -100,7 +125,6 @@
         BaseFSSystemUniprocessor.__init__(self, **kwargs)
         LinuxArmSystemBuilder.__init__(self, machine_type)
 
-
 class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo):
     """Uniprocessor ARM system prepared for CPU switching"""
 
diff -r 6f4a19eeaea0 -r 8111a8da1938 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py	Wed Sep 10 08:56:12 2014 +0100
+++ b/tests/configs/o3-timing.py	Wed Sep 10 08:56:27 2014 +0100
@@ -39,7 +39,17 @@
 # Authors: Andreas Hansson
 
 from m5.objects import *
+from m5.defines import buildEnv
 from base_config import *
+from arm_generic import *
+from O3_ARM_v7a import O3_ARM_v7a_3
 
-root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
-                                cpu_class=DerivO3CPU).create_root()
+# If we are running ARM regressions, use a more sensible CPU
+# configuration. This makes the results more meaningful, and also
+# increases the coverage of the regressions.
+if buildEnv['TARGET_ISA'] == "arm":
+    root = ArmSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                   cpu_class=O3_ARM_v7a_3).create_root()
+else:
+    root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64,
+                                   cpu_class=DerivO3CPU).create_root()