diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/checker/cpu_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -209,10 +209,6 @@
                                                          thread->getTC()));
 #endif
 
-#if FULL_SYSTEM
-            thread->setInst(machInst);
-#endif // FULL_SYSTEM
-
             fault = inst->getFault();
         }
 
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/checker/thread_context.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -154,9 +154,6 @@
     int threadId() { return actualTC->threadId(); }
 
     // @todo: Do I need this?
-    MachInst getInst() { return actualTC->getInst(); }
-
-    // @todo: Do I need this?
     void copyArchRegs(ThreadContext *tc)
     {
         actualTC->copyArchRegs(tc);
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/inorder/thread_context.hh
--- a/src/cpu/inorder/thread_context.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/inorder/thread_context.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -177,11 +177,6 @@
     /** Returns this thread's ID number. */
     int getThreadNum() { return thread->readTid(); }
 
-    /** Returns the instruction this thread is currently committing.
-     *  Only used when an instruction faults.
-     */
-    TheISA::MachInst getInst();
-
     /** Copies the architectural registers from another TC into this TC. */
     void copyArchRegs(ThreadContext *src_tc);
 
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/inorder/thread_context.cc
--- a/src/cpu/inorder/thread_context.cc	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/inorder/thread_context.cc	Tue Aug 31 16:59:57 2010 -0700
@@ -171,12 +171,6 @@
     panic("unserialize unimplemented");    
 }
 
-TheISA::MachInst
-InOrderThreadContext:: getInst()
-{
-    return thread->getInst();
-}
-
 
 void
 InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/o3/commit_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -1033,12 +1033,6 @@
     }
 #endif
 
-    // DTB will sometimes need the machine instruction for when
-    // faults happen.  So we will set it here, prior to the DTB
-    // possibly needing it for its fault.
-    thread[tid]->setInst(
-        static_cast<TheISA::MachInst>(head_inst->staticInst->machInst));
-
     if (inst_fault != NoFault) {
         DPRINTF(Commit, "Inst [sn:%lli] PC %#x has a fault\n",
                 head_inst->seqNum, head_inst->readPC());
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/o3/thread_context.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -151,10 +151,6 @@
     /** Samples the function profiling information. */
     virtual void profileSample();
 #endif
-    /** Returns the instruction this thread is currently committing.
-     *  Only used when an instruction faults.
-     */
-    virtual TheISA::MachInst getInst();
 
     /** Copies the architectural registers from another TC into this TC. */
     virtual void copyArchRegs(ThreadContext *tc);
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/o3/thread_context_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -216,13 +216,6 @@
 #endif
 
 template <class Impl>
-TheISA::MachInst
-O3ThreadContext<Impl>:: getInst()
-{
-    return thread->getInst();
-}
-
-template <class Impl>
 void
 O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
 {
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/ozone/cpu.hh
--- a/src/cpu/ozone/cpu.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/ozone/cpu.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -171,9 +171,6 @@
 
         int threadId();
 
-        // Also somewhat obnoxious.  Really only used for the TLB fault.
-        TheISA::MachInst getInst();
-
         void copyArchRegs(ThreadContext *tc);
 
         void clearArchRegs();
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/ozone/cpu_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -771,7 +771,6 @@
     setCpuId(old_context->cpuId());
     setContextId(old_context->contextId());
 
-    thread->setInst(old_context->getInst());
 #if !FULL_SYSTEM
     setFuncExeInst(old_context->readFuncExeInst());
 #else
@@ -863,13 +862,6 @@
 }
 
 template <class Impl>
-TheISA::MachInst
-OzoneCPU<Impl>::OzoneTC::getInst()
-{
-    return thread->getInst();
-}
-
-template <class Impl>
 void
 OzoneCPU<Impl>::OzoneTC::copyArchRegs(ThreadContext *tc)
 {
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/ozone/inorder_back_end_impl.hh
--- a/src/cpu/ozone/inorder_back_end_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/ozone/inorder_back_end_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -304,12 +304,6 @@
 
             thread->inSyscall = true;
 
-            // Hack for now; DTB will sometimes need the machine instruction
-            // for when faults happen.  So we will set it here, prior to the
-            // DTB possibly needing it for this translation.
-            thread->setInst(
-                static_cast<TheISA::MachInst>(inst->staticInst->machInst));
-
             // Consider holding onto the trap and waiting until the trap event
             // happens for this to be executed.
             inst_fault->invoke(xc);
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/ozone/lw_back_end_impl.hh
--- a/src/cpu/ozone/lw_back_end_impl.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/ozone/lw_back_end_impl.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -1171,9 +1171,6 @@
         }
 #endif
 
-        thread->setInst(
-            static_cast<TheISA::MachInst>(inst->staticInst->machInst));
-
         handleFault(inst_fault);
         return false;
     }
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/simple/base.cc	Tue Aug 31 16:59:57 2010 -0700
@@ -456,10 +456,6 @@
         DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
                 curStaticInst->getName(), curStaticInst->machInst);
 #endif // TRACING_ON
-
-#if FULL_SYSTEM
-        thread->setInst(inst);
-#endif // FULL_SYSTEM
     }
 }
 
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/simple_thread.cc
--- a/src/cpu/simple_thread.cc	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/simple_thread.cc	Tue Aug 31 16:59:57 2010 -0700
@@ -181,7 +181,6 @@
 #if !FULL_SYSTEM
     funcExeInst = oldContext->readFuncExeInst();
 #endif
-    inst = oldContext->getInst();
 
     _threadId = oldContext->threadId();
     _contextId = oldContext->contextId();
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/thread_context.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -171,10 +171,6 @@
     virtual void profileSample() = 0;
 #endif
 
-    // Also somewhat obnoxious.  Really only used for the TLB fault.
-    // However, may be quite useful in SPARC.
-    virtual TheISA::MachInst getInst() = 0;
-
     virtual void copyArchRegs(ThreadContext *tc) = 0;
 
     virtual void clearArchRegs() = 0;
@@ -352,8 +348,6 @@
     void profileClear() { return actualTC->profileClear(); }
     void profileSample() { return actualTC->profileSample(); }
 #endif
-    // @todo: Do I need this?
-    MachInst getInst() { return actualTC->getInst(); }
 
     // @todo: Do I need this?
     void copyArchRegs(ThreadContext *tc) { actualTC->copyArchRegs(tc); }
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/thread_state.hh
--- a/src/cpu/thread_state.hh	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/thread_state.hh	Tue Aug 31 16:59:57 2010 -0700
@@ -122,12 +122,6 @@
     void setMemPort(TranslatingPort *_port) { port = _port; }
 #endif
 
-    /** Sets the current instruction being committed. */
-    void setInst(TheISA::MachInst _inst) { inst = _inst; }
-
-    /** Returns the current instruction being committed. */
-    TheISA::MachInst getInst() { return inst; }
-
     /** Reads the number of instructions functionally executed and
      * committed.
      */
@@ -205,11 +199,6 @@
     Process *process;
 #endif
 
-    /** Current instruction the thread is committing.  Only set and
-     * used for DTB faults currently.
-     */
-    TheISA::MachInst inst;
-
   public:
     /**
      * Temporary storage to pass the source address from copy_load to
diff -r c7e1541bb5e6 -r f619f5ae4ce8 src/cpu/thread_state.cc
--- a/src/cpu/thread_state.cc	Tue Aug 31 16:44:49 2010 -0700
+++ b/src/cpu/thread_state.cc	Tue Aug 31 16:59:57 2010 -0700
@@ -75,7 +75,6 @@
     SERIALIZE_ENUM(_status);
     // thread_num and cpu_id are deterministic from the config
     SERIALIZE_SCALAR(funcExeInst);
-    SERIALIZE_SCALAR(inst);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick = 0;
@@ -94,7 +93,6 @@
     UNSERIALIZE_ENUM(_status);
     // thread_num and cpu_id are deterministic from the config
     UNSERIALIZE_SCALAR(funcExeInst);
-    UNSERIALIZE_SCALAR(inst);
 
 #if FULL_SYSTEM
     Tick quiesceEndTick;