diff -r dfa22eb664e9 -r b229e72bfcc6 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py	Wed Sep 24 23:53:42 2014 -0500
+++ b/configs/example/ruby_network_test.py	Thu Sep 25 00:00:18 2014 -0500
@@ -99,12 +99,12 @@
                      traffic_type=options.synthetic,
                      inj_rate=options.injectionrate,
                      precision=options.precision,
-                     num_memories=options.num_dirs) \
+                     num_memories=options.num_dirs,
+                     memory_size = AddrRange(options.mem_size).size()) \
          for i in xrange(options.num_cpus) ]
 
 # create the desired simulated system
-system = System(cpu = cpus, physmem = SimpleMemory(),
-                mem_ranges = [AddrRange(options.mem_size)])
+system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)])
 
 
 # Create a top-level voltage domain and clock domain
diff -r dfa22eb664e9 -r b229e72bfcc6 configs/ruby/Network_test.py
--- a/configs/ruby/Network_test.py	Wed Sep 24 23:53:42 2014 -0500
+++ b/configs/ruby/Network_test.py	Thu Sep 25 00:00:18 2014 -0500
@@ -85,7 +85,6 @@
 
         cpu_seq = RubySequencer(icache = cache,
                                 dcache = cache,
-                                using_network_tester = True,
                                 ruby_system = ruby_system)
 
         l1_cntrl.sequencer = cpu_seq
diff -r dfa22eb664e9 -r b229e72bfcc6 src/cpu/testers/networktest/NetworkTest.py
--- a/src/cpu/testers/networktest/NetworkTest.py	Wed Sep 24 23:53:42 2014 -0500
+++ b/src/cpu/testers/networktest/NetworkTest.py	Thu Sep 25 00:00:18 2014 -0500
@@ -35,11 +35,12 @@
     cxx_header = "cpu/testers/networktest/networktest.hh"
     block_offset = Param.Int(6, "block offset in bits")
     num_memories = Param.Int(1, "Num Memories")
-    memory_size = Param.Int(65536, "memory size")
+    memory_size = Param.UInt64("memory size")
     sim_cycles = Param.Int(1000, "Number of simulation cycles")
     fixed_pkts = Param.Bool(False, "Send fixed number of packets")
     max_packets = Param.Counter(0, "Number of packets to send when in fixed_pkts mode")
-    traffic_type = Param.Counter(0, "Traffic type: uniform random, tornado, bit complement")
+    traffic_type = Param.Counter(0,
+            "Traffic type: uniform random, tornado, bit complement")
     inj_rate = Param.Float(0.1, "Packet injection rate")
     precision = Param.Int(3, "Number of digits of precision after decimal point")
     test = MasterPort("Port to the memory system to test")
diff -r dfa22eb664e9 -r b229e72bfcc6 src/cpu/testers/networktest/networktest.cc
--- a/src/cpu/testers/networktest/networktest.cc	Wed Sep 24 23:53:42 2014 -0500
+++ b/src/cpu/testers/networktest/networktest.cc	Thu Sep 25 00:00:18 2014 -0500
@@ -176,7 +176,8 @@
 {
     unsigned destination = id;
     if (trafficType == 0) { // Uniform Random
-        destination = random_mt.random<unsigned>(0, numMemories - 1);
+        destination = random_mt.random<unsigned>(0, size-1);
+        destination >>= blockSizeBits;
     } else if (trafficType == 1) { // Tornado
         int networkDimension = (int) sqrt(numMemories);
         int my_x = id%networkDimension;
diff -r dfa22eb664e9 -r b229e72bfcc6 src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh	Wed Sep 24 23:53:42 2014 -0500
+++ b/src/mem/ruby/system/Sequencer.hh	Thu Sep 25 00:00:18 2014 -0500
@@ -98,7 +98,6 @@
     void checkCoherence(const Address& address);
 
     void markRemoved();
-    void removeRequest(SequencerRequest* request);
     void evictionCallback(const Address& address);
     void invalidateSC(const Address& address);
 
@@ -193,8 +192,6 @@
     Stats::Scalar m_load_waiting_on_store;
     Stats::Scalar m_load_waiting_on_load;
 
-    bool m_usingNetworkTester;
-
     //! Histogram for number of outstanding requests per cycle.
     Stats::Histogram m_outstandReqHist;
 
diff -r dfa22eb664e9 -r b229e72bfcc6 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc	Wed Sep 24 23:53:42 2014 -0500
+++ b/src/mem/ruby/system/Sequencer.cc	Thu Sep 25 00:00:18 2014 -0500
@@ -68,8 +68,6 @@
     assert(m_deadlock_threshold > 0);
     assert(m_instCache_ptr != NULL);
     assert(m_dataCache_ptr != NULL);
-
-    m_usingNetworkTester = p->using_network_tester;
 }
 
 Sequencer::~Sequencer()
@@ -293,29 +291,6 @@
 }
 
 void
-Sequencer::removeRequest(SequencerRequest* srequest)
-{
-    assert(m_outstanding_count ==
-           m_writeRequestTable.size() + m_readRequestTable.size());
-
-    Address line_addr(srequest->pkt->getAddr());
-    line_addr.makeLineAddress();
-    if ((srequest->m_type == RubyRequestType_ST) ||
-        (srequest->m_type == RubyRequestType_RMW_Read) ||
-        (srequest->m_type == RubyRequestType_RMW_Write) ||
-        (srequest->m_type == RubyRequestType_Load_Linked) ||
-        (srequest->m_type == RubyRequestType_Store_Conditional) ||
-        (srequest->m_type == RubyRequestType_Locked_RMW_Read) ||
-        (srequest->m_type == RubyRequestType_Locked_RMW_Write)) {
-        m_writeRequestTable.erase(line_addr);
-    } else {
-        m_readRequestTable.erase(line_addr);
-    }
-
-    markRemoved();
-}
-
-void
 Sequencer::invalidateSC(const Address& address)
 {
     RequestTable::iterator i = m_writeRequestTable.find(address);
@@ -447,15 +422,9 @@
            (request->m_type == RubyRequestType_Locked_RMW_Write) ||
            (request->m_type == RubyRequestType_FLUSH));
 
-    //
     // For Alpha, properly handle LL, SC, and write requests with respect to
     // locked cache blocks.
-    //
-    // Not valid for Network_test protocl
-    //
-    bool success = true;
-    if(!m_usingNetworkTester)
-        success = handleLlsc(address, request);
+    bool success = handleLlsc(address, request);
 
     if (request->m_type == RubyRequestType_Locked_RMW_Read) {
         m_controller->blockOnQueue(address, m_mandatory_q_ptr);
diff -r dfa22eb664e9 -r b229e72bfcc6 src/mem/ruby/system/Sequencer.py
--- a/src/mem/ruby/system/Sequencer.py	Wed Sep 24 23:53:42 2014 -0500
+++ b/src/mem/ruby/system/Sequencer.py	Thu Sep 25 00:00:18 2014 -0500
@@ -65,7 +65,6 @@
         "max requests (incl. prefetches) outstanding")
     deadlock_threshold = Param.Cycles(500000,
         "max outstanding cycles for a request before deadlock/livelock declared")
-    using_network_tester = Param.Bool(False, "")
 
 class DMASequencer(MemObject):
     type = 'DMASequencer'