diff -r 12a5f4d02f57 -r 348800a540fd src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh	Mon Sep 29 11:39:07 2014 +0100
+++ b/src/arch/arm/tlb.hh	Mon Sep 29 11:39:20 2014 +0100
@@ -53,6 +53,7 @@
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/probe/pmu.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;
@@ -131,6 +132,9 @@
     Stats::Formula misses;
     Stats::Formula accesses;
 
+    /** PMU probe for TLB refills */
+    ProbePoints::PMUUPtr ppRefills;
+
     int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
 
     bool bootUncacheability;
@@ -291,6 +295,8 @@
 
     void regStats();
 
+    void regProbePoints() M5_ATTR_OVERRIDE;
+
     /**
      * Get the table walker master port. This is used for migrating
      * port connections during a CPU takeOverFrom() call. For
diff -r 12a5f4d02f57 -r 348800a540fd src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc	Mon Sep 29 11:39:07 2014 +0100
+++ b/src/arch/arm/tlb.cc	Mon Sep 29 11:39:20 2014 +0100
@@ -197,6 +197,7 @@
     table[0] = entry;
 
     inserts++;
+    ppRefills->notify(1);
 }
 
 void
@@ -531,6 +532,12 @@
     accesses = readAccesses + writeAccesses + instAccesses;
 }
 
+void
+TLB::regProbePoints()
+{
+    ppRefills.reset(new ProbePoints::PMU(getProbeManager(), "Refills"));
+}
+
 Fault
 TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
                  Translation *translation, bool &delay, bool timing)