diff -r 0e86fac7254c src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Sat May 31 18:00:23 2014 -0700
+++ b/src/cpu/o3/fetch_impl.hh	Sat Oct 25 16:56:24 2014 -0500
@@ -738,7 +738,7 @@
     decoder[tid]->reset();
 
     // Clear the icache miss if it's outstanding.
-    if (fetchStatus[tid] == IcacheWaitResponse) {
+    if (fetchStatus[tid] == IcacheWaitResponse || fetchStatus[tid] == IcacheWaitRetry) {
         DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
                 tid);
         memReq[tid] = NULL;
diff -r 0e86fac7254c src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh	Sat May 31 18:00:23 2014 -0700
+++ b/src/cpu/o3/lsq_impl.hh	Sat Oct 25 16:56:24 2014 -0500
@@ -175,8 +175,10 @@
     }
 
     if (retryTid != InvalidThreadID) {
-        DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.\n");
-        drained = false;
+        if(thread[retryTid].loadBlocked()  ||  thread[retryTid].storeBlocked()) {
+             DPRINTF(Drain, "Not drained, the LSQ has blocked the caches.\n");
+             drained = false;
+        }
     }
 
     return drained;
diff -r 0e86fac7254c src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Sat May 31 18:00:23 2014 -0700
+++ b/src/cpu/o3/lsq_unit.hh	Sat Oct 25 16:56:24 2014 -0500
@@ -186,6 +186,10 @@
     bool loadBlocked()
     { return isLoadBlocked; }
 
+    /** Returns if a store became blocked due to the memory system */
+    bool storeBlocked()
+    { return isStoreBlocked; }
+
     /** Clears the signal that a load became blocked. */
     void clearLoadBlocked()
     { isLoadBlocked = false; }
diff -r 0e86fac7254c src/mem/ruby/system/RubyMemoryControl.cc
--- a/src/mem/ruby/system/RubyMemoryControl.cc	Sat May 31 18:00:23 2014 -0700
+++ b/src/mem/ruby/system/RubyMemoryControl.cc	Sat Oct 25 16:56:24 2014 -0500
@@ -674,9 +674,6 @@
 RubyMemoryControl::drain(DrainManager *dm)
 {
     DPRINTF(RubyMemory, "MemoryController drain\n");
-    if(m_event.scheduled()) {
-        deschedule(m_event);
-    }
     return 0;
 }