diff -r ba51f8572571 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Mon Nov 03 10:14:42 2014 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Fri Nov 07 15:26:45 2014 -0600
@@ -754,7 +754,7 @@
     decoder[tid]->reset();
 
     // Clear the icache miss if it's outstanding.
-    if (fetchStatus[tid] == IcacheWaitResponse) {
+    if (fetchStatus[tid] == IcacheWaitResponse || fetchStatus[tid] == IcacheWaitRetry) {
         DPRINTF(Fetch, "[tid:%i]: Squashing outstanding Icache miss.\n",
                 tid);
         memReq[tid] = NULL;
diff -r ba51f8572571 src/mem/ruby/structures/RubyMemoryControl.cc
--- a/src/mem/ruby/structures/RubyMemoryControl.cc	Mon Nov 03 10:14:42 2014 -0600
+++ b/src/mem/ruby/structures/RubyMemoryControl.cc	Fri Nov 07 15:26:45 2014 -0600
@@ -675,9 +675,6 @@
 RubyMemoryControl::drain(DrainManager *dm)
 {
     DPRINTF(RubyMemory, "MemoryController drain\n");
-    if(m_event.scheduled()) {
-        deschedule(m_event);
-    }
     return 0;
 }