diff -r ba886c297ed5 -r 0d4e2892ee6a src/mem/dram_ctrl.cc
--- a/src/mem/dram_ctrl.cc	Sun Oct 26 08:35:29 2014 -0500
+++ b/src/mem/dram_ctrl.cc	Mon Oct 27 22:25:01 2014 -0500
@@ -1060,14 +1060,13 @@
         // Record the activation and deal with all the global timing
         // constraints caused be a new activation (tRRD and tXAW)
         activateBank(bank, act_tick, dram_pkt->row);
-
-        // issue the command as early as possible
-        cmd_at = bank.colAllowedAt;
     }
 
     // we need to wait until the bus is available before we can issue
     // the command
-    cmd_at = std::max(cmd_at, busBusyUntil - tCL);
+    if (busBusyUntil >= tCL) {
+        cmd_at = std::max(cmd_at, busBusyUntil - tCL);
+    }
 
     // update the packet ready time
     dram_pkt->readyTime = cmd_at + tCL + tBURST;
@@ -1205,7 +1204,9 @@
     // conservative estimate of when we have to schedule the next
     // request to not introduce any unecessary bubbles. In most cases
     // we will wake up sooner than we have to.
-    nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
+    if (busBusyUntil >= tRP + tRCD + tCL) {
+        nextReqTime = busBusyUntil - (tRP + tRCD + tCL);
+    }
 
     // Update the stats and schedule the next request
     if (dram_pkt->isRead) {