# Node ID 63b52d190220a79d0e0feb80895a1ebcf02e3a31
# Parent  6c566599e7e7605f2ec244cfcdb1e893212bb374
diff --git a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
--- a/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
+++ b/src/arch/x86/isa/insts/general_purpose/control_transfer/jump.py
@@ -145,7 +145,7 @@
     zexti t3, t1, 15, dataSize=8
     slli t3, t3, 4, dataSize=8
     wrsel cs, t1, dataSize=2
-    wrbase cs, t3
+    wrbase cs, t3, dataSize=8
     wrip t0, t2, dataSize=asz
 };
 
@@ -168,7 +168,7 @@
     mov t2, t0, t2
     slli t3, t1, 4, dataSize=8
     wrsel cs, t1, dataSize=2
-    wrbase cs, t3
+    wrbase cs, t3, dataSize=8
     wrip t0, t2, dataSize=asz
 };
 '''
diff --git a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
--- a/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
+++ b/src/arch/x86/isa/insts/general_purpose/data_transfer/move.py
@@ -215,7 +215,7 @@
     zexti t2, regm, 15, dataSize=8
     slli t3, t2, 4, dataSize=8
     wrsel reg, regm
-    wrbase reg, t3
+    wrbase reg, t3, dataSize=8
 };
 
 def macroop MOV_REAL_S_M {
@@ -223,7 +223,7 @@
     zexti t2, t1, 15, dataSize=8
     slli t3, t2, 4, dataSize=8
     wrsel reg, t1
-    wrbase reg, t3
+    wrbase reg, t3, dataSize=8
 };
 
 def macroop MOV_REAL_S_P {