diff -r d5d0f7213427 -r 1126acf9f3b6 src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh	Mon Nov 24 12:27:22 2014 +0000
+++ b/src/cpu/o3/lsq_impl.hh	Mon Nov 24 12:27:23 2014 +0000
@@ -347,6 +347,8 @@
         DPRINTF(LSQ, "Got error packet back for address: %#X\n",
                 pkt->getAddr());
     thread[pkt->req->threadId()].completeDataAccess(pkt);
+    delete pkt->req;
+    delete pkt;
     return true;
 }
 
diff -r d5d0f7213427 -r 1126acf9f3b6 src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh	Mon Nov 24 12:27:22 2014 +0000
+++ b/src/cpu/o3/lsq_unit_impl.hh	Mon Nov 24 12:27:23 2014 +0000
@@ -105,15 +105,11 @@
         DPRINTF(IEW, "[sn:%lli]: Response from first half of earlier "
                 "blocked split load recieved. Ignoring.\n", inst->seqNum);
         delete state;
-        delete pkt->req;
-        delete pkt;
         return;
     }
 
     // If this is a split access, wait until all packets are received.
     if (TheISA::HasUnalignedMemAcc && !state->complete()) {
-        delete pkt->req;
-        delete pkt;
         return;
     }
 
@@ -142,8 +138,6 @@
     cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt));
 
     delete state;
-    delete pkt->req;
-    delete pkt;
 }
 
 template <class Impl>