diff -r 80177d2dc2a8 -r 15fb33736bdb src/arch/alpha/isa/decoder.isa --- a/src/arch/alpha/isa/decoder.isa Wed Nov 03 18:14:16 2010 -0500 +++ b/src/arch/alpha/isa/decoder.isa Wed Nov 03 18:14:20 2010 -0500 @@ -47,11 +47,6 @@ 0x23: ldt({{ Fa = Mem.df; }}); 0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC); 0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC); -#ifdef USE_COPY - 0x20: MiscPrefetch::copy_load({{ EA = Ra; }}, - {{ fault = xc->copySrcTranslate(EA); }}, - inst_flags = [IsMemRef, IsLoad, IsCopy]); -#endif } format LoadOrPrefetch { @@ -71,11 +66,6 @@ 0x0f: stq_u({{ Mem.uq = Ra.uq; }}, {{ EA = (Rb + disp) & ~7; }}); 0x26: sts({{ Mem.ul = t_to_s(Fa.uq); }}); 0x27: stt({{ Mem.df = Fa; }}); -#ifdef USE_COPY - 0x24: MiscPrefetch::copy_store({{ EA = Rb; }}, - {{ fault = xc->copy(EA); }}, - inst_flags = [IsMemRef, IsStore, IsCopy]); -#endif } format StoreCond { @@ -788,10 +778,8 @@ format MiscPrefetch { 0xf800: wh64({{ EA = Rb & ~ULL(63); }}, - {{ xc->writeHint(EA, 64, memAccessFlags); }}, - mem_flags = PREFETCH, - inst_flags = [IsMemRef, IsDataPrefetch, - IsStore, MemWriteOp]); + {{ ; }}, + mem_flags = PREFETCH); } format BasicOperate { diff -r 80177d2dc2a8 -r 15fb33736bdb src/arch/alpha/isa/mem.isa --- a/src/arch/alpha/isa/mem.isa Wed Nov 03 18:14:16 2010 -0500 +++ b/src/arch/alpha/isa/mem.isa Wed Nov 03 18:14:20 2010 -0500 @@ -396,6 +396,7 @@ %(op_rd)s; %(ea_code)s; + warn_once("Prefetch instrutions is Alpha do not do anything\n"); if (fault == NoFault) { %(memacc_code)s; } @@ -404,6 +405,8 @@ } }}; +// Prefetches in Alpha don't actually do anything +// They just build an effective address and complete def template MiscInitiateAcc {{ Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const @@ -411,6 +414,7 @@ warn("initiateAcc undefined: Misc instruction does not support split " "access method!"); return NoFault; + } }}; @@ -422,7 +426,6 @@ { warn("completeAcc undefined: Misc instruction does not support split " "access method!"); - return NoFault; } }}; @@ -530,12 +533,11 @@ inst_flags = makeList(inst_flags) pf_mem_flags = mem_flags + pf_flags + ['PREFETCH'] - pf_inst_flags = inst_flags + ['IsMemRef', 'IsLoad', - 'IsDataPrefetch', 'MemReadOp'] + pf_inst_flags = inst_flags (pf_header_output, pf_decoder_output, _, pf_exec_output) = \ LoadStoreBase(name, Name + 'Prefetch', ea_code, - 'xc->prefetch(EA, memAccessFlags);', + ';', pf_mem_flags, pf_inst_flags, exec_template_base = 'Misc') header_output += pf_header_output diff -r 80177d2dc2a8 -r 15fb33736bdb src/arch/arm/isa/insts/ldr.isa --- a/src/arch/arm/isa/insts/ldr.isa Wed Nov 03 18:14:16 2010 -0500 +++ b/src/arch/arm/isa/insts/ldr.isa Wed Nov 03 18:14:20 2010 -0500 @@ -161,8 +161,13 @@ if self.user: self.memFlags.append("ArmISA::TLB::UserMode") - if self.flavor == "prefetch": + self.instFlags = [] + if self.flavor == "dprefetch": self.memFlags.append("Request::PREFETCH") + self.instFlags = ['IsDataPrefetch'] + elif self.flavor == "iprefetch": + self.memFlags.append("Request::PREFETCH") + self.instFlags = ['IsInstPrefetch'] elif self.flavor == "exclusive": self.memFlags.append("Request::LLSC") elif self.flavor == "normal": @@ -185,7 +190,7 @@ self.codeBlobs["ea_code"] = eaCode # Code that actually handles the access - if self.flavor == "prefetch": + if self.flavor == "dprefetch" or self.flavor == "iprefetch": accCode = 'uint64_t temp = Mem%s; temp = temp;' elif self.flavor == "fp": accCode = "FpDest.uw = cSwap(Mem%s, ((CPSR)Cpsr).e);\n" @@ -200,7 +205,7 @@ wbDecl = None if self.writeback: wbDecl = self.wbDecl - self.emitHelper(base, wbDecl) + self.emitHelper(base, wbDecl, self.instFlags) def loadImmClassName(post, add, writeback, size=4, sign=False, user=False): return memClassName("LOAD_IMM", post, add, writeback, size, sign, user) @@ -325,11 +330,11 @@ RfeInst(mnem, False, False, True).emit() RfeInst(mnem, False, False, False).emit() - def buildPrefetches(mnem): - LoadReg(mnem, False, False, False, size=1, flavor="prefetch").emit() - LoadImm(mnem, False, False, False, size=1, flavor="prefetch").emit() - LoadReg(mnem, False, True, False, size=1, flavor="prefetch").emit() - LoadImm(mnem, False, True, False, size=1, flavor="prefetch").emit() + def buildPrefetches(mnem, type): + LoadReg(mnem, False, False, False, size=1, flavor=type).emit() + LoadImm(mnem, False, False, False, size=1, flavor=type).emit() + LoadReg(mnem, False, True, False, size=1, flavor=type).emit() + LoadImm(mnem, False, True, False, size=1, flavor=type).emit() buildLoads("ldr") buildLoads("ldrt", user=True) @@ -346,9 +351,9 @@ buildRfeLoads("rfe") - buildPrefetches("pld") - buildPrefetches("pldw") - buildPrefetches("pli") + buildPrefetches("pld", "dprefetch") + buildPrefetches("pldw", "dprefetch") + buildPrefetches("pli", "iprefetch") LoadImm("ldrex", False, True, False, size=4, flavor="exclusive").emit() LoadImm("ldrexh", False, True, False, size=2, flavor="exclusive").emit() diff -r 80177d2dc2a8 -r 15fb33736bdb src/cpu/simple/timing.cc --- a/src/cpu/simple/timing.cc Wed Nov 03 18:14:16 2010 -0500 +++ b/src/cpu/simple/timing.cc Wed Nov 03 18:14:20 2010 -0500 @@ -1,4 +1,16 @@ /* + * Copyright (c) 2010 ARM Limited + * All rights reserved + * + * The license below extends only to copyright in the software and shall + * not be construed as granting a license to any other intellectual + * property including but not limited to intellectual property relating + * to a hardware implementation of the functionality of the software + * licensed hereunder. You may use the software subject to the license + * terms below provided that you ensure that this notice is replicated + * unmodified and in its entirety in all distributions of the software, + * modified or unmodified, in source code or in binary form. + * * Copyright (c) 2002-2005 The Regents of The University of Michigan * All rights reserved. * @@ -750,7 +762,7 @@ void TimingSimpleCPU::advanceInst(Fault fault) { - if (fault != NoFault || !stayAtPC) + if (!stayAtPC || (fault != NoFault)) advancePC(fault); if (_status == Running) { @@ -789,10 +801,12 @@ } preExecute(); - if (curStaticInst && - curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { + if (curStaticInst && curStaticInst->isMemRef()) { // load or store: just send to dcache Fault fault = curStaticInst->initiateAcc(this, traceData); + if (curStaticInst->isPrefetch()) { + fault = NoFault; + } if (_status != Running) { // instruction will complete in dcache response callback assert(_status == DcacheWaitResponse || diff -r 80177d2dc2a8 -r 15fb33736bdb src/cpu/static_inst.hh --- a/src/cpu/static_inst.hh Wed Nov 03 18:14:16 2010 -0500 +++ b/src/cpu/static_inst.hh Wed Nov 03 18:14:20 2010 -0500 @@ -226,6 +226,8 @@ bool isStoreConditional() const { return flags[IsStoreConditional]; } bool isInstPrefetch() const { return flags[IsInstPrefetch]; } bool isDataPrefetch() const { return flags[IsDataPrefetch]; } + bool isPrefetch() const { return flags[IsInstPrefetch] || + flags[IsDataPrefetch]; } bool isCopy() const { return flags[IsCopy];} bool isInteger() const { return flags[IsInteger]; } diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:56:01 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:21:55 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -44,4 +46,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 165376986500 because target called exit() +Exiting @ tick 162779779500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,339 +1,339 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 264030 # Simulator instruction rate (inst/s) -host_mem_usage 193748 # Number of bytes of host memory used -host_seconds 2142.00 # Real time elapsed on the host -host_tick_rate 77206740 # Simulator tick rate (ticks/s) +host_inst_rate 299092 # Simulator instruction rate (inst/s) +host_mem_usage 240504 # Number of bytes of host memory used +host_seconds 1890.90 # Real time elapsed on the host +host_tick_rate 86086026 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 565552443 # Number of instructions simulated -sim_seconds 0.165377 # Number of seconds simulated -sim_ticks 165376986500 # Number of ticks simulated +sim_seconds 0.162780 # Number of seconds simulated +sim_ticks 162779779500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 63929788 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 71429024 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 197 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 4120838 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 70454375 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 76396550 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1676108 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 63926991 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 71320793 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 193 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 4120736 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 70355271 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 76295210 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1675650 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 62547159 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 20033371 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 19927815 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 320816297 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.876017 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.306184 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 315794082 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.905853 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.338192 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 102501444 31.95% 31.95% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 105613320 32.92% 64.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 36739083 11.45% 76.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 11050019 3.44% 79.77% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 10174748 3.17% 82.94% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 21768321 6.79% 89.72% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 10744082 3.35% 93.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 2191909 0.68% 93.76% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 20033371 6.24% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 102454006 32.44% 32.44% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 100543040 31.84% 64.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 36844526 11.67% 75.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 9307171 2.95% 78.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10247874 3.25% 82.14% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 21736977 6.88% 89.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 12524254 3.97% 92.99% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 2208419 0.70% 93.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 19927815 6.31% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 320816297 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 315794082 # Number of insts commited each cycle system.cpu.commit.COM:count 601856963 # Number of instructions committed -system.cpu.commit.COM:loads 115049510 # Number of loads committed +system.cpu.commit.COM:loads 114514042 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 154862033 # Number of memory references committed +system.cpu.commit.COM:refs 153965363 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 4120001 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 4119890 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 61749735 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 60520337 # The number of squashed insts skipped by commit system.cpu.committedInsts 565552443 # Number of Instructions Simulated system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated -system.cpu.cpi 0.584833 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.584833 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 4 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 4 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 115012927 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 14990.355830 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7392.342173 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 114228619 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 11757056000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.006819 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 784308 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 566126 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1612876000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.001897 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 218182 # number of ReadReq MSHR misses +system.cpu.cpi 0.575649 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.575649 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 112312480 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 15160.742892 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 7367.811163 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 111525313 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 11934036500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007009 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 787167 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 569138 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1606396500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.001941 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 218029 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 39451321 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 14906.098057 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11053.696113 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 38301940 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 17132785891 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.029134 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1149381 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 892463 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2839893498 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 14279.189894 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11300.460826 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 38165820 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 18355912888 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.032584 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1285501 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1028584 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2903280494 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.006512 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 256918 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6663.699115 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 256917 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7297.150943 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 20363.636364 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 321.049385 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 113 # number of cycles access was blocked +system.cpu.dcache.avg_refs 315.175064 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 106 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 752998 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 773498 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 224000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 154464248 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 14940.273173 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency -system.cpu.dcache.demand_hits 152530559 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 28889841891 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.012519 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1933689 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 1458589 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 4452769498 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.003076 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 475100 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 151763801 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 14613.989982 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency +system.cpu.dcache.demand_hits 149691133 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 30289949388 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.013657 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2072668 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 1597722 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 4509676994 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.003130 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 474946 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.999558 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4094.188781 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 154464248 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 14940.273173 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 9372.278463 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.999550 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4094.156298 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 151763801 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 14613.989982 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 9495.136277 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 152530559 # number of overall hits -system.cpu.dcache.overall_miss_latency 28889841891 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.012519 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1933689 # number of overall misses -system.cpu.dcache.overall_mshr_hits 1458589 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 4452769498 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.003076 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 475100 # number of overall MSHR misses +system.cpu.dcache.overall_hits 149691133 # number of overall hits +system.cpu.dcache.overall_miss_latency 30289949388 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.013657 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2072668 # number of overall misses +system.cpu.dcache.overall_mshr_hits 1597722 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 4509676994 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.003130 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 474946 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 471004 # number of replacements -system.cpu.dcache.sampled_refs 475100 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 470850 # number of replacements +system.cpu.dcache.sampled_refs 474946 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4094.188781 # Cycle average of tags in use -system.cpu.dcache.total_refs 152530563 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 126404000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 423151 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 48113828 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 871 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 4177876 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 689990711 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 144277716 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 122985866 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 9844039 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 3043 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 5438887 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 163094811 # DTB accesses +system.cpu.dcache.tagsinuse 4094.156298 # Cycle average of tags in use +system.cpu.dcache.total_refs 149691136 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 126698000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 423042 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 45000094 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 877 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 4176202 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 688674202 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 142513181 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 122905016 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 9698747 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 3338 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 5375791 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 163053496 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 163045966 # DTB hits -system.cpu.dtb.data_misses 48845 # DTB misses +system.cpu.dtb.data_hits 163001268 # DTB hits +system.cpu.dtb.data_misses 52228 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 122278185 # DTB read accesses +system.cpu.dtb.read_accesses 122206073 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 122255138 # DTB read hits -system.cpu.dtb.read_misses 23047 # DTB read misses -system.cpu.dtb.write_accesses 40816626 # DTB write accesses +system.cpu.dtb.read_hits 122181392 # DTB read hits +system.cpu.dtb.read_misses 24681 # DTB read misses +system.cpu.dtb.write_accesses 40847423 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 40790828 # DTB write hits -system.cpu.dtb.write_misses 25798 # DTB write misses -system.cpu.fetch.Branches 76396550 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 65649275 # Number of cache lines fetched -system.cpu.fetch.Cycles 195872330 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1325100 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 699185184 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 4170349 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230977 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 65649275 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 65605896 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.113913 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 330660336 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.114512 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.085107 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 40819876 # DTB write hits +system.cpu.dtb.write_misses 27547 # DTB write misses +system.cpu.fetch.Branches 76295210 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 65560315 # Number of cache lines fetched +system.cpu.fetch.Cycles 195638983 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1304986 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 697895611 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 4169829 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.234351 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 65560315 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 65602641 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.143680 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 325492829 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.144120 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.095910 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 200437318 60.62% 60.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 10372140 3.14% 63.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 15863919 4.80% 68.55% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 13948828 4.22% 72.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 12077397 3.65% 76.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 13850642 4.19% 80.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 5888624 1.78% 82.39% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3427564 1.04% 83.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 54793904 16.57% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 195414198 60.04% 60.04% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 10425646 3.20% 63.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 15856104 4.87% 68.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 13952359 4.29% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 12095872 3.72% 76.11% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 13761061 4.23% 80.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 5876732 1.81% 82.15% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3435361 1.06% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 54675496 16.80% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 330660336 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 65649275 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 36269.949066 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35524.725275 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 65648097 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 42726000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 325492829 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 65560315 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 36252.118644 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35514.835165 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 65559135 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 42777500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000018 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1178 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 268 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32327500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1180 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 270 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32318500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 72140.765934 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 72043.005495 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 65649275 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 36269.949066 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency -system.cpu.icache.demand_hits 65648097 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 42726000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 65560315 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 36252.118644 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency +system.cpu.icache.demand_hits 65559135 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 42777500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000018 # miss rate for demand accesses -system.cpu.icache.demand_misses 1178 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 268 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32327500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1180 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 270 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32318500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000014 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.378879 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 775.944948 # Average occupied blocks per context -system.cpu.icache.overall_accesses 65649275 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 36269.949066 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35524.725275 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.378389 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 774.939822 # Average occupied blocks per context +system.cpu.icache.overall_accesses 65560315 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 36252.118644 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35514.835165 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 65648097 # number of overall hits -system.cpu.icache.overall_miss_latency 42726000 # number of overall miss cycles +system.cpu.icache.overall_hits 65559135 # number of overall hits +system.cpu.icache.overall_miss_latency 42777500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000018 # miss rate for overall accesses -system.cpu.icache.overall_misses 1178 # number of overall misses -system.cpu.icache.overall_mshr_hits 268 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32327500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1180 # number of overall misses +system.cpu.icache.overall_mshr_hits 270 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32318500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 32 # number of replacements +system.cpu.icache.replacements 34 # number of replacements system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 775.944948 # Cycle average of tags in use -system.cpu.icache.total_refs 65648097 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 774.939822 # Cycle average of tags in use +system.cpu.icache.total_refs 65559135 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 93638 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 67433622 # Number of branches executed -system.cpu.iew.EXEC:nop 43234709 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.811577 # Inst execution rate -system.cpu.iew.EXEC:refs 164032675 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 41211382 # Number of stores executed +system.cpu.idleCycles 66731 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 67424273 # Number of branches executed +system.cpu.iew.EXEC:nop 43222760 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.839913 # Inst execution rate +system.cpu.iew.EXEC:refs 163081324 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 40875188 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 492720055 # num instructions consuming a value -system.cpu.iew.WB:count 595983189 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.807592 # average fanout of values written-back +system.cpu.iew.WB:consumers 487722865 # num instructions consuming a value +system.cpu.iew.WB:count 595805949 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811742 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 397916939 # num instructions producing a value -system.cpu.iew.WB:rate 1.801893 # insts written-back per cycle -system.cpu.iew.WB:sent 597091543 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 4603878 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 1505457 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 126939472 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 3143406 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 43126164 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 663744184 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 122821293 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 6299898 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 599186314 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 2121 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 395904949 # num instructions producing a value +system.cpu.iew.WB:rate 1.830098 # insts written-back per cycle +system.cpu.iew.WB:sent 596918670 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 4602797 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 1364972 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 126095826 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 3115345 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 42628898 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 662516409 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 122206136 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 6268247 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 599001166 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 43958 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 28444 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 9844039 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 43665 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 13859 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 9698747 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 63343 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 720 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 7235686 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 12544 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 729 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 9862373 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 10156 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 71476 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 5929 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 11889962 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 3313641 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 71476 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 943110 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 3660768 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.709889 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.709889 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 70243 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 5936 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 11581784 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 3177577 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 70243 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 943658 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 3659139 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.737170 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.737170 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 438748901 72.46% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 29 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 5 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.46% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 124774485 20.61% 93.07% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 41956101 6.93% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 439513912 72.61% 72.61% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 6682 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 35 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 6 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 5 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 72.62% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 124151932 20.51% 93.13% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 41596836 6.87% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 605486212 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 7206090 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011901 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 605269413 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 7095490 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.011723 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5226098 72.52% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 48 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 72.52% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 1579159 21.91% 94.44% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 400785 5.56% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5209273 73.42% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 47 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 73.42% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 1541723 21.73% 95.15% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 344447 4.85% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 330660336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.831143 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.672265 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 325492829 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.859548 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.691188 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 90539952 27.38% 27.38% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 66701453 20.17% 47.55% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 79600053 24.07% 71.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 36541170 11.05% 82.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 31317153 9.47% 92.15% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 13281184 4.02% 96.17% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 11041150 3.34% 99.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 1066057 0.32% 99.83% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 572164 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 87236535 26.80% 26.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 66508902 20.43% 47.23% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 78677146 24.17% 71.41% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 34244703 10.52% 81.93% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 30387182 9.34% 91.26% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 15745565 4.84% 96.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 11042338 3.39% 99.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 1062135 0.33% 99.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 588323 0.18% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 330660336 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.830624 # Inst issue rate -system.cpu.iq.iqInstsAdded 620509446 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 605486212 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 53535562 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 17232 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 29599324 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 325492829 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.859166 # Inst issue rate +system.cpu.iq.iqInstsAdded 619293624 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 605269413 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 25 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 52323110 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12647 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 8 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 28040159 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 65649312 # ITB accesses +system.cpu.itb.fetch_accesses 65560352 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 65649275 # ITB hits +system.cpu.itb.fetch_hits 65560315 # ITB hits system.cpu.itb.fetch_misses 37 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -343,98 +343,98 @@ system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 256918 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34522.310610 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31406.220232 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 197081 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2065711500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.232903 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_accesses 256917 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34478.809098 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31357.738523 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 197080 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 2063108500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.232904 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 59837 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 1879254000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232903 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 1876353000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.232904 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 59837 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 219092 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34389.734476 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.456070 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 186176 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1131972500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.150238 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 32916 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1021003500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150238 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 32916 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 423151 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 423151 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5261.194030 # average number of cycles each access was blocked +system.cpu.l2cache.ReadReq_accesses 218939 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34396.642358 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.006381 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 186029 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1131993500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.150316 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 32910 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1020835500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150316 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 32910 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 423042 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 423042 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 5257.142857 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 5.283534 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 67 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 5.281796 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 352500 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 368000 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 476010 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34475.262256 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 383257 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 3197684000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.194855 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 92753 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 475856 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34449.653358 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 383109 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 3195102000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.194906 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 92747 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 2900257500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.194855 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 92753 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 2897188500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.194906 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 92747 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.052815 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.488399 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 1730.637326 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 16003.856484 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 476010 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34475.262256 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31268.611258 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.052860 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.487907 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 1732.123670 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15987.736166 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 475856 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34449.653358 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31237.544072 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 383257 # number of overall hits -system.cpu.l2cache.overall_miss_latency 3197684000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.194855 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 92753 # number of overall misses +system.cpu.l2cache.overall_hits 383109 # number of overall hits +system.cpu.l2cache.overall_miss_latency 3195102000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.194906 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 92747 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 2900257500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.194855 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 92753 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 2897188500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.194906 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 92747 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 74446 # number of replacements -system.cpu.l2cache.sampled_refs 90349 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 74441 # number of replacements +system.cpu.l2cache.sampled_refs 90342 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 17734.493810 # Cycle average of tags in use -system.cpu.l2cache.total_refs 477362 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 17719.859836 # Cycle average of tags in use +system.cpu.l2cache.total_refs 477168 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 59324 # number of writebacks -system.cpu.memDep0.conflictingLoads 22261692 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 15435128 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 126939472 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 43126164 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 330753974 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 12738848 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 59318 # number of writebacks +system.cpu.memDep0.conflictingLoads 17165638 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 12779208 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 126095826 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 42628898 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 325559560 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 12578826 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 463854889 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 34708853 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 151708807 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 618719 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 82 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 896183749 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 680208714 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 518824645 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 115765657 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 9844039 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 40602289 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 54969756 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 696 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 32 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 79641546 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 31 # count of temporary serializing insts renamed -system.cpu.timesIdled 3516 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 31670463 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 149957875 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 662477 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 118 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 894828905 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 679288968 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 518109497 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 115552585 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 9698747 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 37704265 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 54254608 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 531 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 30 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 73685603 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 29 # count of temporary serializing insts renamed +system.cpu.timesIdled 2072 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:36:02 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:31:02 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -44,3 +46,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 300930958000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1810362 # Simulator instruction rate (inst/s) -host_mem_usage 184036 # Number of bytes of host memory used -host_seconds 332.45 # Real time elapsed on the host -host_tick_rate 905187706 # Simulator tick rate (ticks/s) +host_inst_rate 6224890 # Simulator instruction rate (inst/s) +host_mem_usage 232016 # Number of bytes of host memory used +host_seconds 96.69 # Real time elapsed on the host +host_tick_rate 3112463113 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.300931 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 601861917 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references +system.cpu.num_refs 153970296 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=gzip input.log 1 -cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/gzip +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/gzip gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:13:16 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:44:32 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/00.gzip/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/00.gzip/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1603392 # Simulator instruction rate (inst/s) -host_mem_usage 192888 # Number of bytes of host memory used -host_seconds 375.37 # Real time elapsed on the host -host_tick_rate 2039675547 # Simulator tick rate (ticks/s) +host_inst_rate 2723974 # Simulator instruction rate (inst/s) +host_mem_usage 239668 # Number of bytes of host memory used +host_seconds 220.95 # Real time elapsed on the host +host_tick_rate 3465167347 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 601856964 # Number of instructions simulated sim_seconds 0.765623 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1531246064 # number of cpu cycles simulated system.cpu.num_insts 601856964 # Number of instructions executed -system.cpu.num_refs 154866966 # Number of memory references +system.cpu.num_refs 153970296 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -661,7 +661,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -681,7 +681,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -807,7 +807,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,14 +7,13 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:17:04 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3-dual +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:04:53 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 118370500 -Exiting @ tick 1900828642500 because m5_exit instruction encountered +Exiting @ tick 1900844230500 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,449 +1,449 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 158375 # Simulator instruction rate (inst/s) -host_mem_usage 283016 # Number of bytes of host memory used -host_seconds 359.78 # Real time elapsed on the host -host_tick_rate 5283356726 # Simulator tick rate (ticks/s) +host_inst_rate 199216 # Simulator instruction rate (inst/s) +host_mem_usage 328188 # Number of bytes of host memory used +host_seconds 286.07 # Real time elapsed on the host +host_tick_rate 6644616468 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 56979511 # Number of instructions simulated -sim_seconds 1.900829 # Number of seconds simulated -sim_ticks 1900828642500 # Number of ticks simulated +sim_insts 56990237 # Number of instructions simulated +sim_seconds 1.900844 # Number of seconds simulated +sim_ticks 1900844230500 # Number of ticks simulated system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.BTBHits 5876227 # Number of BTB hits -system.cpu0.BPredUnit.BTBLookups 11175399 # Number of BTB lookups -system.cpu0.BPredUnit.RASInCorrect 27772 # Number of incorrect RAS predictions. -system.cpu0.BPredUnit.condIncorrect 686228 # Number of conditional branches incorrect -system.cpu0.BPredUnit.condPredicted 10431445 # Number of conditional branches predicted -system.cpu0.BPredUnit.lookups 12491766 # Number of BP lookups -system.cpu0.BPredUnit.usedRAS 881103 # Number of times the RAS was used to get a target. -system.cpu0.commit.COM:branches 7527502 # Number of branches committed -system.cpu0.commit.COM:bw_lim_events 920717 # number cycles where commit BW limit reached +system.cpu0.BPredUnit.BTBHits 5873671 # Number of BTB hits +system.cpu0.BPredUnit.BTBLookups 11166529 # Number of BTB lookups +system.cpu0.BPredUnit.RASInCorrect 27790 # Number of incorrect RAS predictions. +system.cpu0.BPredUnit.condIncorrect 685267 # Number of conditional branches incorrect +system.cpu0.BPredUnit.condPredicted 10432996 # Number of conditional branches predicted +system.cpu0.BPredUnit.lookups 12491450 # Number of BP lookups +system.cpu0.BPredUnit.usedRAS 879904 # Number of times the RAS was used to get a target. +system.cpu0.commit.COM:branches 7524834 # Number of branches committed +system.cpu0.commit.COM:bw_lim_events 923111 # number cycles where commit BW limit reached system.cpu0.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.commit.COM:committed_per_cycle::samples 78591026 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::mean 0.633671 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::stdev 1.400615 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::samples 78256773 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::mean 0.636207 # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::stdev 1.403151 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::0 57312142 72.92% 72.92% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::1 9330889 11.87% 84.80% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::2 5427191 6.91% 91.70% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::3 2440699 3.11% 94.81% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::4 1862016 2.37% 97.18% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::5 630346 0.80% 97.98% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::6 341230 0.43% 98.41% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::7 325796 0.41% 98.83% # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::8 920717 1.17% 100.00% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::0 56995845 72.83% 72.83% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::1 9310416 11.90% 84.73% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::2 5430205 6.94% 91.67% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::3 2440245 3.12% 94.79% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::4 1860572 2.38% 97.16% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::5 630930 0.81% 97.97% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::6 344016 0.44% 98.41% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::7 321433 0.41% 98.82% # Number of insts commited each cycle +system.cpu0.commit.COM:committed_per_cycle::8 923111 1.18% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.COM:committed_per_cycle::total 78591026 # Number of insts commited each cycle -system.cpu0.commit.COM:count 49800850 # Number of instructions committed -system.cpu0.commit.COM:loads 8090667 # Number of loads committed +system.cpu0.commit.COM:committed_per_cycle::total 78256773 # Number of insts commited each cycle +system.cpu0.commit.COM:count 49787514 # Number of instructions committed +system.cpu0.commit.COM:loads 7895784 # Number of loads committed system.cpu0.commit.COM:membars 191655 # Number of memory barriers committed -system.cpu0.commit.COM:refs 13515444 # Number of memory references committed +system.cpu0.commit.COM:refs 13320151 # Number of memory references committed system.cpu0.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.branchMispredicts 653618 # The number of times a branch was mispredicted -system.cpu0.commit.commitCommittedInsts 49800850 # The number of committed instructions -system.cpu0.commit.commitNonSpecStalls 564747 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.commitSquashedInsts 7272798 # The number of squashed insts skipped by commit -system.cpu0.committedInsts 46939821 # Number of Instructions Simulated -system.cpu0.committedInsts_total 46939821 # Number of Instructions Simulated -system.cpu0.cpi 2.403302 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.403302 # CPI: Total CPI of All Threads -system.cpu0.dcache.LoadLockedReq_accesses::0 178200 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 178200 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14347.227969 # average LoadLockedReq miss latency +system.cpu0.commit.branchMispredicts 652659 # The number of times a branch was mispredicted +system.cpu0.commit.commitCommittedInsts 49787514 # The number of committed instructions +system.cpu0.commit.commitNonSpecStalls 564772 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.commitSquashedInsts 7271893 # The number of squashed insts skipped by commit +system.cpu0.committedInsts 46926700 # Number of Instructions Simulated +system.cpu0.committedInsts_total 46926700 # Number of Instructions Simulated +system.cpu0.cpi 2.403270 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.403270 # CPI: Total CPI of All Threads +system.cpu0.dcache.LoadLockedReq_accesses::0 178277 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 178277 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14385.010585 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10538.474362 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_hits::0 158864 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 158864 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_miss_latency 277418000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108507 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_misses::0 19336 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 19336 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_mshr_hits 4339 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158045500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084158 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 10557.129525 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_hits::0 158910 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 158910 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_miss_latency 278594500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.108634 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_misses::0 19367 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 19367 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_mshr_hits 4366 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 158367500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.084144 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_misses 14997 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.ReadReq_accesses::0 8021076 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8021076 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.144269 # average ReadReq miss latency +system.cpu0.dcache.LoadLockedReq_mshr_misses 15001 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.ReadReq_accesses::0 8018710 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 8018710 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_avg_miss_latency::0 23752.163525 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23767.790910 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23766.972926 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_hits::0 6644033 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6644033 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 32707724000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate::0 0.171678 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses::0 1377043 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 1377043 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_hits 391877 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_miss_latency 23415219500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122822 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_hits::0 6640866 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6640866 # number of ReadReq hits +system.cpu0.dcache.ReadReq_miss_latency 32726776000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_rate::0 0.171829 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_misses::0 1377844 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 1377844 # number of ReadReq misses +system.cpu0.dcache.ReadReq_mshr_hits 392731 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_miss_latency 23413154000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122852 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 985166 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920846500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.StoreCondReq_accesses::0 185095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 185095 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13168.588688 # average StoreCondReq miss latency +system.cpu0.dcache.ReadReq_mshr_misses 985113 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 920830500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_accesses::0 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 185114 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 13300.547196 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10165.293795 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_hits::0 181453 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 181453 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_miss_latency 47960000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019676 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_misses::0 3642 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 3642 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37022000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019676 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 10297.264022 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_hits::0 181459 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 181459 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_miss_latency 48613500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_rate::0 0.019745 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_misses::0 3655 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 3655 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_mshr_miss_latency 37636500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.019745 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_misses 3642 # number of StoreCondReq MSHR misses -system.cpu0.dcache.WriteReq_accesses::0 5224623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5224623 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency::0 32385.164412 # average WriteReq miss latency +system.cpu0.dcache.StoreCondReq_mshr_misses 3655 # number of StoreCondReq MSHR misses +system.cpu0.dcache.WriteReq_accesses::0 5224193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5224193 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_avg_miss_latency::0 32390.296487 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30570.974366 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 30580.318877 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_hits::0 3608317 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3608317 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 52344335550 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate::0 0.309363 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses::0 1616306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1616306 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_hits 1352902 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_miss_latency 8052516932 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050416 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_hits::0 3607335 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3607335 # number of WriteReq hits +system.cpu0.dcache.WriteReq_miss_latency 52370509997 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_rate::0 0.309494 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_misses::0 1616858 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1616858 # number of WriteReq misses +system.cpu0.dcache.WriteReq_mshr_hits 1353465 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_miss_latency 8054641930 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.050418 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 263404 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320254998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8777.270227 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21937.500000 # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 8.502455 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 83541 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 8 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 733261932 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 175500 # number of cycles access was blocked +system.cpu0.dcache.WriteReq_mshr_misses 263393 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1320665498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8775.921635 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21500 # average number of cycles each access was blocked +system.cpu0.dcache.avg_refs 8.499931 # Average number of references to valid blocks. +system.cpu0.dcache.blocked::no_mshrs 83634 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 7 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_mshrs 733965430 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 150500 # number of cycles access was blocked system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses::0 13245699 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::0 13242903 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 13245699 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency::0 28413.679644 # average overall miss latency +system.cpu0.dcache.demand_accesses::total 13242903 # number of demand (read+write) accesses +system.cpu0.dcache.demand_avg_miss_latency::0 28415.944557 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 25203.021402 # average overall mshr miss latency -system.cpu0.dcache.demand_hits::0 10252350 # number of demand (read+write) hits +system.cpu0.dcache.demand_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency +system.cpu0.dcache.demand_hits::0 10248201 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 10252350 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 85052059550 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate::0 0.225986 # miss rate for demand accesses +system.cpu0.dcache.demand_hits::total 10248201 # number of demand (read+write) hits +system.cpu0.dcache.demand_miss_latency 85097285997 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_rate::0 0.226136 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.dcache.demand_misses::0 2993349 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::0 2994702 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2993349 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 1744779 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 31467736432 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate::0 0.094262 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_misses::total 2994702 # number of demand (read+write) misses +system.cpu0.dcache.demand_mshr_hits 1746196 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_miss_latency 31467795930 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_rate::0 0.094277 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 1248570 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses 1248506 # number of demand (read+write) MSHR misses system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.973042 # Average percentage of cache occupancy +system.cpu0.dcache.occ_%::0 0.973616 # Average percentage of cache occupancy system.cpu0.dcache.occ_%::1 -0.001953 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 498.197480 # Average occupied blocks per context +system.cpu0.dcache.occ_blocks::0 498.491480 # Average occupied blocks per context system.cpu0.dcache.occ_blocks::1 -1.000000 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses::0 13245699 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::0 13242903 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 13245699 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency::0 28413.679644 # average overall miss latency +system.cpu0.dcache.overall_accesses::total 13242903 # number of overall (read+write) accesses +system.cpu0.dcache.overall_avg_miss_latency::0 28415.944557 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 25203.021402 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency 25204.360996 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits::0 10252350 # number of overall hits +system.cpu0.dcache.overall_hits::0 10248201 # number of overall hits system.cpu0.dcache.overall_hits::1 0 # number of overall hits -system.cpu0.dcache.overall_hits::total 10252350 # number of overall hits -system.cpu0.dcache.overall_miss_latency 85052059550 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate::0 0.225986 # miss rate for overall accesses +system.cpu0.dcache.overall_hits::total 10248201 # number of overall hits +system.cpu0.dcache.overall_miss_latency 85097285997 # number of overall miss cycles +system.cpu0.dcache.overall_miss_rate::0 0.226136 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.dcache.overall_misses::0 2993349 # number of overall misses +system.cpu0.dcache.overall_misses::0 2994702 # number of overall misses system.cpu0.dcache.overall_misses::1 0 # number of overall misses -system.cpu0.dcache.overall_misses::total 2993349 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 1744779 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 31467736432 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate::0 0.094262 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_misses::total 2994702 # number of overall misses +system.cpu0.dcache.overall_mshr_hits 1746196 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_miss_latency 31467795930 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_rate::0 0.094277 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 1248570 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 2241101498 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_misses 1248506 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_uncacheable_latency 2241495998 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 1246736 # number of replacements -system.cpu0.dcache.sampled_refs 1247248 # Sample count of references to valid blocks. +system.cpu0.dcache.replacements 1246705 # number of replacements +system.cpu0.dcache.sampled_refs 1247217 # Sample count of references to valid blocks. system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 497.197481 # Cycle average of tags in use -system.cpu0.dcache.total_refs 10604670 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 497.491481 # Cycle average of tags in use +system.cpu0.dcache.total_refs 10601259 # Total number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 721609 # number of writebacks -system.cpu0.decode.DECODE:BlockedCycles 34091757 # Number of cycles decode is blocked -system.cpu0.decode.DECODE:BranchMispred 33333 # Number of times decode detected a branch misprediction -system.cpu0.decode.DECODE:BranchResolved 521194 # Number of times decode resolved a branch -system.cpu0.decode.DECODE:DecodedInsts 62604059 # Number of instructions handled by decode -system.cpu0.decode.DECODE:IdleCycles 32208044 # Number of cycles decode is idle -system.cpu0.decode.DECODE:RunCycles 11309029 # Number of cycles decode is running -system.cpu0.decode.DECODE:SquashCycles 1270122 # Number of cycles decode is squashing -system.cpu0.decode.DECODE:SquashedInsts 100597 # Number of squashed instructions handled by decode -system.cpu0.decode.DECODE:UnblockCycles 982195 # Number of cycles decode is unblocking -system.cpu0.dtb.data_accesses 794086 # DTB accesses -system.cpu0.dtb.data_acv 680 # DTB access violations -system.cpu0.dtb.data_hits 14244186 # DTB hits -system.cpu0.dtb.data_misses 32160 # DTB misses +system.cpu0.dcache.writebacks 721554 # number of writebacks +system.cpu0.decode.DECODE:BlockedCycles 33796856 # Number of cycles decode is blocked +system.cpu0.decode.DECODE:BranchMispred 33338 # Number of times decode detected a branch misprediction +system.cpu0.decode.DECODE:BranchResolved 520908 # Number of times decode resolved a branch +system.cpu0.decode.DECODE:DecodedInsts 62600964 # Number of instructions handled by decode +system.cpu0.decode.DECODE:IdleCycles 32174872 # Number of cycles decode is idle +system.cpu0.decode.DECODE:RunCycles 11303760 # Number of cycles decode is running +system.cpu0.decode.DECODE:SquashCycles 1270160 # Number of cycles decode is squashing +system.cpu0.decode.DECODE:SquashedInsts 100637 # Number of squashed instructions handled by decode +system.cpu0.decode.DECODE:UnblockCycles 981284 # Number of cycles decode is unblocking +system.cpu0.dtb.data_accesses 794683 # DTB accesses +system.cpu0.dtb.data_acv 699 # DTB access violations +system.cpu0.dtb.data_hits 14241389 # DTB hits +system.cpu0.dtb.data_misses 32519 # DTB misses system.cpu0.dtb.fetch_accesses 0 # ITB accesses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_hits 0 # ITB hits system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 598785 # DTB read accesses -system.cpu0.dtb.read_acv 509 # DTB read access violations -system.cpu0.dtb.read_hits 8659679 # DTB read hits -system.cpu0.dtb.read_misses 26490 # DTB read misses -system.cpu0.dtb.write_accesses 195301 # DTB write accesses -system.cpu0.dtb.write_acv 171 # DTB write access violations -system.cpu0.dtb.write_hits 5584507 # DTB write hits -system.cpu0.dtb.write_misses 5670 # DTB write misses -system.cpu0.fetch.Branches 12491766 # Number of branches that fetch encountered -system.cpu0.fetch.CacheLines 7797156 # Number of cache lines fetched -system.cpu0.fetch.Cycles 20279244 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.IcacheSquashes 375144 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.Insts 63684763 # Number of instructions fetch has processed -system.cpu0.fetch.MiscStallCycles 883 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.SquashCycles 746145 # Number of cycles fetch has spent squashing -system.cpu0.fetch.branchRate 0.110732 # Number of branch fetches per cycle -system.cpu0.fetch.icacheStallCycles 7797156 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.predictedBranches 6757330 # Number of branches that fetch has predicted taken -system.cpu0.fetch.rate 0.564528 # Number of inst fetches per cycle -system.cpu0.fetch.rateDist::samples 79861148 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.797444 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.100172 # Number of instructions fetched each cycle (Total) +system.cpu0.dtb.read_accesses 599310 # DTB read accesses +system.cpu0.dtb.read_acv 523 # DTB read access violations +system.cpu0.dtb.read_hits 8657125 # DTB read hits +system.cpu0.dtb.read_misses 26727 # DTB read misses +system.cpu0.dtb.write_accesses 195373 # DTB write accesses +system.cpu0.dtb.write_acv 176 # DTB write access violations +system.cpu0.dtb.write_hits 5584264 # DTB write hits +system.cpu0.dtb.write_misses 5792 # DTB write misses +system.cpu0.fetch.Branches 12491450 # Number of branches that fetch encountered +system.cpu0.fetch.CacheLines 7791215 # Number of cache lines fetched +system.cpu0.fetch.Cycles 20268333 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.IcacheSquashes 374565 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.Insts 63688508 # Number of instructions fetch has processed +system.cpu0.fetch.MiscStallCycles 1103 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.SquashCycles 745343 # Number of cycles fetch has spent squashing +system.cpu0.fetch.branchRate 0.110762 # Number of branch fetches per cycle +system.cpu0.fetch.icacheStallCycles 7791215 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.predictedBranches 6753575 # Number of branches that fetch has predicted taken +system.cpu0.fetch.rate 0.564727 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::samples 79526933 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.800842 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.104211 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67408745 84.41% 84.41% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 900507 1.13% 85.54% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 1775612 2.22% 87.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 807193 1.01% 88.77% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 2749132 3.44% 92.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 585022 0.73% 92.94% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 680161 0.85% 93.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 829359 1.04% 94.83% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4125417 5.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67079407 84.35% 84.35% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 896436 1.13% 85.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 1772079 2.23% 87.70% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 811632 1.02% 88.72% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2745328 3.45% 92.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 585266 0.74% 92.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 679619 0.85% 93.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 829666 1.04% 94.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4127500 5.19% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 79861148 # Number of instructions fetched each cycle (Total) -system.cpu0.icache.ReadReq_accesses::0 7797156 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 7797156 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency::0 15068.131136 # average ReadReq miss latency +system.cpu0.fetch.rateDist::total 79526933 # Number of instructions fetched each cycle (Total) +system.cpu0.icache.ReadReq_accesses::0 7791215 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7791215 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_avg_miss_latency::0 15067.927393 # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.324658 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits::0 6939758 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 6939758 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 12919385500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate::0 0.109963 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses::0 857398 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 857398 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_hits 36516 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_miss_latency 9864805500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105280 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12017.913224 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_hits::0 6933667 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 6933667 # number of ReadReq hits +system.cpu0.icache.ReadReq_miss_latency 12921471000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_rate::0 0.110066 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_misses::0 857548 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 857548 # number of ReadReq misses +system.cpu0.icache.ReadReq_mshr_hits 36674 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_miss_latency 9865192500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.105359 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 820882 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs 11596.153846 # average number of cycles each access was blocked +system.cpu0.icache.ReadReq_mshr_misses 820874 # number of ReadReq MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 12107.843137 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 8.455231 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 52 # number of cycles access was blocked +system.cpu0.icache.avg_refs 8.447903 # Average number of references to valid blocks. +system.cpu0.icache.blocked::no_mshrs 51 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 603000 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_mshrs 617500 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses::0 7797156 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::0 7791215 # number of demand (read+write) accesses system.cpu0.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 7797156 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency::0 15068.131136 # average overall miss latency +system.cpu0.icache.demand_accesses::total 7791215 # number of demand (read+write) accesses +system.cpu0.icache.demand_avg_miss_latency::0 15067.927393 # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 12017.324658 # average overall mshr miss latency -system.cpu0.icache.demand_hits::0 6939758 # number of demand (read+write) hits +system.cpu0.icache.demand_avg_mshr_miss_latency 12017.913224 # average overall mshr miss latency +system.cpu0.icache.demand_hits::0 6933667 # number of demand (read+write) hits system.cpu0.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 6939758 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 12919385500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate::0 0.109963 # miss rate for demand accesses +system.cpu0.icache.demand_hits::total 6933667 # number of demand (read+write) hits +system.cpu0.icache.demand_miss_latency 12921471000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_rate::0 0.110066 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu0.icache.demand_misses::0 857398 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::0 857548 # number of demand (read+write) misses system.cpu0.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 857398 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 36516 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 9864805500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate::0 0.105280 # mshr miss rate for demand accesses +system.cpu0.icache.demand_misses::total 857548 # number of demand (read+write) misses +system.cpu0.icache.demand_mshr_hits 36674 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_miss_latency 9865192500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_rate::0 0.105359 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 820882 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses 820874 # number of demand (read+write) MSHR misses system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.occ_%::0 0.995823 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 509.861438 # Average occupied blocks per context -system.cpu0.icache.overall_accesses::0 7797156 # number of overall (read+write) accesses +system.cpu0.icache.occ_blocks::0 509.861243 # Average occupied blocks per context +system.cpu0.icache.overall_accesses::0 7791215 # number of overall (read+write) accesses system.cpu0.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 7797156 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency::0 15068.131136 # average overall miss latency +system.cpu0.icache.overall_accesses::total 7791215 # number of overall (read+write) accesses +system.cpu0.icache.overall_avg_miss_latency::0 15067.927393 # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 12017.324658 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency 12017.913224 # average overall mshr miss latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits::0 6939758 # number of overall hits +system.cpu0.icache.overall_hits::0 6933667 # number of overall hits system.cpu0.icache.overall_hits::1 0 # number of overall hits -system.cpu0.icache.overall_hits::total 6939758 # number of overall hits -system.cpu0.icache.overall_miss_latency 12919385500 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate::0 0.109963 # miss rate for overall accesses +system.cpu0.icache.overall_hits::total 6933667 # number of overall hits +system.cpu0.icache.overall_miss_latency 12921471000 # number of overall miss cycles +system.cpu0.icache.overall_miss_rate::0 0.110066 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu0.icache.overall_misses::0 857398 # number of overall misses +system.cpu0.icache.overall_misses::0 857548 # number of overall misses system.cpu0.icache.overall_misses::1 0 # number of overall misses -system.cpu0.icache.overall_misses::total 857398 # number of overall misses -system.cpu0.icache.overall_mshr_hits 36516 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 9864805500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate::0 0.105280 # mshr miss rate for overall accesses +system.cpu0.icache.overall_misses::total 857548 # number of overall misses +system.cpu0.icache.overall_mshr_hits 36674 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_miss_latency 9865192500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_rate::0 0.105359 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 820882 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses 820874 # number of overall MSHR misses system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 820254 # number of replacements -system.cpu0.icache.sampled_refs 820765 # Sample count of references to valid blocks. +system.cpu0.icache.replacements 820245 # number of replacements +system.cpu0.icache.sampled_refs 820756 # Sample count of references to valid blocks. system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 509.861438 # Cycle average of tags in use -system.cpu0.icache.total_refs 6939758 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 24435354000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 108 # number of writebacks -system.cpu0.idleCycles 32949400 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.iew.EXEC:branches 8094203 # Number of branches executed -system.cpu0.iew.EXEC:nop 3189422 # number of nop insts executed -system.cpu0.iew.EXEC:rate 0.446630 # Inst execution rate -system.cpu0.iew.EXEC:refs 14505244 # number of memory reference insts executed -system.cpu0.iew.EXEC:stores 5602935 # Number of stores executed +system.cpu0.icache.tagsinuse 509.861243 # Cycle average of tags in use +system.cpu0.icache.total_refs 6933667 # Total number of references to valid blocks. +system.cpu0.icache.warmup_cycle 24435382000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.writebacks 109 # number of writebacks +system.cpu0.idleCycles 33250612 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.iew.EXEC:branches 8091553 # Number of branches executed +system.cpu0.iew.EXEC:nop 3189610 # number of nop insts executed +system.cpu0.iew.EXEC:rate 0.446670 # Inst execution rate +system.cpu0.iew.EXEC:refs 14308443 # number of memory reference insts executed +system.cpu0.iew.EXEC:stores 5602810 # Number of stores executed system.cpu0.iew.EXEC:swp 0 # number of swp insts executed -system.cpu0.iew.WB:consumers 31589475 # num instructions consuming a value -system.cpu0.iew.WB:count 50006148 # cumulative count of insts written-back -system.cpu0.iew.WB:fanout 0.758030 # average fanout of values written-back +system.cpu0.iew.WB:consumers 31619553 # num instructions consuming a value +system.cpu0.iew.WB:count 49998381 # cumulative count of insts written-back +system.cpu0.iew.WB:fanout 0.757763 # average fanout of values written-back system.cpu0.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu0.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.iew.WB:producers 23945765 # num instructions producing a value -system.cpu0.iew.WB:rate 0.443275 # insts written-back per cycle -system.cpu0.iew.WB:sent 50087986 # cumulative count of insts sent to commit -system.cpu0.iew.branchMispredicts 712279 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewBlockCycles 9112948 # Number of cycles IEW is blocking -system.cpu0.iew.iewDispLoadInsts 9340675 # Number of dispatched load instructions -system.cpu0.iew.iewDispNonSpecInsts 1511795 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewDispSquashedInsts 758903 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispStoreInsts 5843423 # Number of dispatched store instructions -system.cpu0.iew.iewDispatchedInsts 57183881 # Number of instructions dispatched to IQ -system.cpu0.iew.iewExecLoadInsts 8902309 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 466602 # Number of squashed instructions skipped in execute -system.cpu0.iew.iewExecutedInsts 50384547 # Number of executed instructions -system.cpu0.iew.iewIQFullEvents 59804 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.WB:producers 23960113 # num instructions producing a value +system.cpu0.iew.WB:rate 0.443336 # insts written-back per cycle +system.cpu0.iew.WB:sent 50080785 # cumulative count of insts sent to commit +system.cpu0.iew.branchMispredicts 711622 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewBlockCycles 9015836 # Number of cycles IEW is blocking +system.cpu0.iew.iewDispLoadInsts 9134167 # Number of dispatched load instructions +system.cpu0.iew.iewDispNonSpecInsts 1511990 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewDispSquashedInsts 755493 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispStoreInsts 5841972 # Number of dispatched store instructions +system.cpu0.iew.iewDispatchedInsts 57170075 # Number of instructions dispatched to IQ +system.cpu0.iew.iewExecLoadInsts 8705633 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 463276 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 50374391 # Number of executed instructions +system.cpu0.iew.iewIQFullEvents 59438 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewLSQFullEvents 6983 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.iewSquashCycles 1270122 # Number of cycles IEW is squashing -system.cpu0.iew.iewUnblockCycles 547925 # Number of cycles IEW is unblocking +system.cpu0.iew.iewLSQFullEvents 6976 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.iewSquashCycles 1270160 # Number of cycles IEW is squashing +system.cpu0.iew.iewUnblockCycles 547257 # Number of cycles IEW is unblocking system.cpu0.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread.0.cacheBlocked 121839 # Number of times an access to memory failed due to the cache being blocked -system.cpu0.iew.lsq.thread.0.forwLoads 411299 # Number of loads that had data forwarded from stores -system.cpu0.iew.lsq.thread.0.ignoredResponses 11485 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread.0.cacheBlocked 121631 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread.0.forwLoads 411302 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread.0.ignoredResponses 10774 # Number of memory responses ignored because the instruction is squashed system.cpu0.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu0.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu0.iew.lsq.thread.0.memOrderViolation 38596 # Number of memory ordering violations -system.cpu0.iew.lsq.thread.0.rescheduledLoads 18609 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread.0.squashedLoads 1250008 # Number of loads squashed -system.cpu0.iew.lsq.thread.0.squashedStores 418646 # Number of stores squashed -system.cpu0.iew.memOrderViolationEvents 38596 # Number of memory order violations -system.cpu0.iew.predictedNotTakenIncorrect 332551 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.predictedTakenIncorrect 379728 # Number of branches that were predicted taken incorrectly -system.cpu0.ipc 0.416094 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.416094 # IPC: Total IPC of All Threads -system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3763 0.01% 0.01% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35146664 69.12% 69.12% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntMult 56139 0.11% 69.23% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.23% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.26% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.26% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.26% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.26% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.27% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.27% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemRead 9202305 18.10% 87.36% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645893 11.10% 98.47% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779184 1.53% 100.00% # Type of FU issued +system.cpu0.iew.lsq.thread.0.memOrderViolation 38966 # Number of memory ordering violations +system.cpu0.iew.lsq.thread.0.rescheduledLoads 18610 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread.0.squashedLoads 1238383 # Number of loads squashed +system.cpu0.iew.lsq.thread.0.squashedStores 417605 # Number of stores squashed +system.cpu0.iew.memOrderViolationEvents 38966 # Number of memory order violations +system.cpu0.iew.predictedNotTakenIncorrect 331944 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 379678 # Number of branches that were predicted taken incorrectly +system.cpu0.ipc 0.416100 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.416100 # IPC: Total IPC of All Threads +system.cpu0.iq.ISSUE:FU_type_0::No_OpClass 3762 0.01% 0.01% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntAlu 35331602 69.50% 69.51% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntMult 55961 0.11% 69.62% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 69.62% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatAdd 15323 0.03% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatDiv 1880 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 69.65% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemRead 9004352 17.71% 87.36% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::MemWrite 5645593 11.11% 98.47% # Type of FU issued +system.cpu0.iq.ISSUE:FU_type_0::IprAccess 779196 1.53% 100.00% # Type of FU issued system.cpu0.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.ISSUE:FU_type_0::total 50851151 # Type of FU issued -system.cpu0.iq.ISSUE:fu_busy_cnt 379787 # FU busy when requested -system.cpu0.iq.ISSUE:fu_busy_rate 0.007469 # FU busy rate (busy events/executed inst) +system.cpu0.iq.ISSUE:FU_type_0::total 50837669 # Type of FU issued +system.cpu0.iq.ISSUE:fu_busy_cnt 379948 # FU busy when requested +system.cpu0.iq.ISSUE:fu_busy_rate 0.007474 # FU busy rate (busy events/executed inst) system.cpu0.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntAlu 40748 10.73% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.73% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemRead 225975 59.50% 70.23% # attempts to use FU when none available -system.cpu0.iq.ISSUE:fu_full::MemWrite 113064 29.77% 100.00% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntAlu 41291 10.87% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntMult 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.87% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemRead 225058 59.23% 70.10% # attempts to use FU when none available +system.cpu0.iq.ISSUE:fu_full::MemWrite 113599 29.90% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.ISSUE:issued_per_cycle::samples 79861148 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.636745 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.207484 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::samples 79526933 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::mean 0.639251 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::stdev 1.210486 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::0 55051799 68.93% 68.93% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::1 12151486 15.22% 84.15% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::2 5444442 6.82% 90.97% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::3 3407774 4.27% 95.23% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::4 2222623 2.78% 98.02% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::5 997342 1.25% 99.27% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::6 433832 0.54% 99.81% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::7 107535 0.13% 99.94% # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::8 44315 0.06% 100.00% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::0 54768546 68.87% 68.87% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::1 12090793 15.20% 84.07% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::2 5440746 6.84% 90.91% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::3 3421929 4.30% 95.22% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::4 2219727 2.79% 98.01% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::5 991235 1.25% 99.25% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::6 436578 0.55% 99.80% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::7 113986 0.14% 99.95% # Number of insts issued each cycle +system.cpu0.iq.ISSUE:issued_per_cycle::8 43393 0.05% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:issued_per_cycle::total 79861148 # Number of insts issued each cycle -system.cpu0.iq.ISSUE:rate 0.450766 # Inst issue rate -system.cpu0.iq.iqInstsAdded 52272510 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqInstsIssued 50851151 # Number of instructions issued -system.cpu0.iq.iqNonSpecInstsAdded 1721949 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqSquashedInstsExamined 6732996 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedInstsIssued 24094 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedNonSpecRemoved 1157202 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.iqSquashedOperandsExamined 3425901 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.ISSUE:issued_per_cycle::total 79526933 # Number of insts issued each cycle +system.cpu0.iq.ISSUE:rate 0.450778 # Inst issue rate +system.cpu0.iq.iqInstsAdded 52258300 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqInstsIssued 50837669 # Number of instructions issued +system.cpu0.iq.iqNonSpecInstsAdded 1722165 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqSquashedInstsExamined 6733244 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedInstsIssued 24149 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedNonSpecRemoved 1157393 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.iqSquashedOperandsExamined 3421850 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.itb.data_accesses 0 # DTB accesses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_hits 0 # DTB hits system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 952090 # ITB accesses -system.cpu0.itb.fetch_acv 738 # ITB acv -system.cpu0.itb.fetch_hits 923140 # ITB hits -system.cpu0.itb.fetch_misses 28950 # ITB misses +system.cpu0.itb.fetch_accesses 951504 # ITB accesses +system.cpu0.itb.fetch_acv 721 # ITB acv +system.cpu0.itb.fetch_hits 922631 # ITB hits +system.cpu0.itb.fetch_misses 28873 # ITB misses system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.read_acv 0 # DTB read access violations system.cpu0.itb.read_hits 0 # DTB read hits @@ -460,7 +460,7 @@ system.cpu0.kern.callpal::swpctx 3287 2.03% 2.25% # number of callpals executed system.cpu0.kern.callpal::tbi 43 0.03% 2.27% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.00% 2.28% # number of callpals executed -system.cpu0.kern.callpal::swpipl 147044 90.75% 93.03% # number of callpals executed +system.cpu0.kern.callpal::swpipl 147045 90.75% 93.03% # number of callpals executed system.cpu0.kern.callpal::rdps 6369 3.93% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.96% # number of callpals executed system.cpu0.kern.callpal::wrusp 3 0.00% 96.96% # number of callpals executed @@ -469,45 +469,45 @@ system.cpu0.kern.callpal::rti 4450 2.75% 99.71% # number of callpals executed system.cpu0.kern.callpal::callsys 330 0.20% 99.91% # number of callpals executed system.cpu0.kern.callpal::imb 138 0.09% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 162036 # number of callpals executed +system.cpu0.kern.callpal::total 162037 # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 176105 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6623 # number of quiesce instructions executed +system.cpu0.kern.inst.hwrei 176107 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6625 # number of quiesce instructions executed system.cpu0.kern.ipl_count::0 62137 40.37% 40.37% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 238 0.15% 40.53% # number of times we switched to this ipl system.cpu0.kern.ipl_count::22 1925 1.25% 41.78% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 254 0.17% 41.94% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 89358 58.06% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 153912 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 89359 58.06% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 153913 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 61267 49.13% 49.13% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 238 0.19% 49.32% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1925 1.54% 50.87% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 254 0.20% 51.07% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 61013 48.93% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 124697 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1862678817000 97.99% 97.99% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 96273000 0.01% 98.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 398546000 0.02% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::30 103367000 0.01% 98.02% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 37550788000 1.98% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1900827791000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1862714429000 97.99% 97.99% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 96239500 0.01% 98.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 398463500 0.02% 98.02% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::30 103371000 0.01% 98.03% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 37530876000 1.97% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1900843379000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.985999 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.682793 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good::kernel 1171 -system.cpu0.kern.mode_good::user 1172 +system.cpu0.kern.ipl_used::31 0.682785 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good::kernel 1172 +system.cpu0.kern.mode_good::user 1173 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch::kernel 6890 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1172 # number of protection mode switches +system.cpu0.kern.mode_switch::kernel 6892 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1173 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good::kernel 0.169956 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.170052 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1898857065000 99.90% 99.90% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 1970718000 0.10% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::kernel 1898870092500 99.90% 99.90% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 1973278500 0.10% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 3288 # number of times the context was actually changed system.cpu0.kern.syscall::2 6 2.99% 2.99% # number of syscalls executed @@ -540,463 +540,463 @@ system.cpu0.kern.syscall::144 1 0.50% 99.00% # number of syscalls executed system.cpu0.kern.syscall::147 2 1.00% 100.00% # number of syscalls executed system.cpu0.kern.syscall::total 201 # number of syscalls executed -system.cpu0.memDep0.conflictingLoads 2328642 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1937858 # Number of conflicting stores. -system.cpu0.memDep0.insertedLoads 9340675 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5843423 # Number of stores inserted to the mem dependence unit. -system.cpu0.numCycles 112810548 # number of cpu cycles simulated -system.cpu0.rename.RENAME:BlockCycles 12992019 # Number of cycles rename is blocking -system.cpu0.rename.RENAME:CommittedMaps 33999562 # Number of HB maps that are committed -system.cpu0.rename.RENAME:IQFullEvents 1006246 # Number of times rename has blocked due to IQ full -system.cpu0.rename.RENAME:IdleCycles 33622049 # Number of cycles rename is idle -system.cpu0.rename.RENAME:LSQFullEvents 1438466 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.RENAME:ROBFullEvents 43293 # Number of times rename has blocked due to ROB full -system.cpu0.rename.RENAME:RenameLookups 72562175 # Number of register rename lookups that rename has made -system.cpu0.rename.RENAME:RenamedInsts 59339637 # Number of instructions processed by rename -system.cpu0.rename.RENAME:RenamedOperands 39991159 # Number of destination operands rename has renamed -system.cpu0.rename.RENAME:RunCycles 11032673 # Number of cycles rename is running -system.cpu0.rename.RENAME:SquashCycles 1270122 # Number of cycles rename is squashing -system.cpu0.rename.RENAME:UnblockCycles 4054916 # Number of cycles rename is unblocking -system.cpu0.rename.RENAME:UndoneMaps 5991595 # Number of HB maps that are undone due to squashing -system.cpu0.rename.RENAME:serializeStallCycles 16889367 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RENAME:serializingInsts 1393634 # count of serializing insts renamed -system.cpu0.rename.RENAME:skidInsts 10149085 # count of insts added to the skid buffer -system.cpu0.rename.RENAME:tempSerializingInsts 207632 # count of temporary serializing insts renamed -system.cpu0.timesIdled 1187372 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.memDep0.conflictingLoads 2303690 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1915346 # Number of conflicting stores. +system.cpu0.memDep0.insertedLoads 9134167 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5841972 # Number of stores inserted to the mem dependence unit. +system.cpu0.numCycles 112777545 # number of cpu cycles simulated +system.cpu0.rename.RENAME:BlockCycles 12780906 # Number of cycles rename is blocking +system.cpu0.rename.RENAME:CommittedMaps 33989447 # Number of HB maps that are committed +system.cpu0.rename.RENAME:IQFullEvents 1008250 # Number of times rename has blocked due to IQ full +system.cpu0.rename.RENAME:IdleCycles 33579404 # Number of cycles rename is idle +system.cpu0.rename.RENAME:LSQFullEvents 1370622 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RENAME:ROBFullEvents 43227 # Number of times rename has blocked due to ROB full +system.cpu0.rename.RENAME:RenameLookups 72557706 # Number of register rename lookups that rename has made +system.cpu0.rename.RENAME:RenamedInsts 59333926 # Number of instructions processed by rename +system.cpu0.rename.RENAME:RenamedOperands 39987201 # Number of destination operands rename has renamed +system.cpu0.rename.RENAME:RunCycles 11036329 # Number of cycles rename is running +system.cpu0.rename.RENAME:SquashCycles 1270160 # Number of cycles rename is squashing +system.cpu0.rename.RENAME:UnblockCycles 3988199 # Number of cycles rename is unblocking +system.cpu0.rename.RENAME:UndoneMaps 5997752 # Number of HB maps that are undone due to squashing +system.cpu0.rename.RENAME:serializeStallCycles 16871933 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RENAME:serializingInsts 1393572 # count of serializing insts renamed +system.cpu0.rename.RENAME:skidInsts 10085816 # count of insts added to the skid buffer +system.cpu0.rename.RENAME:tempSerializingInsts 207581 # count of temporary serializing insts renamed +system.cpu0.timesIdled 1187611 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.BTBHits 1155732 # Number of BTB hits -system.cpu1.BPredUnit.BTBLookups 2684041 # Number of BTB lookups -system.cpu1.BPredUnit.RASInCorrect 8261 # Number of incorrect RAS predictions. -system.cpu1.BPredUnit.condIncorrect 171129 # Number of conditional branches incorrect -system.cpu1.BPredUnit.condPredicted 2476500 # Number of conditional branches predicted -system.cpu1.BPredUnit.lookups 2988933 # Number of BP lookups -system.cpu1.BPredUnit.usedRAS 209112 # Number of times the RAS was used to get a target. -system.cpu1.commit.COM:branches 1513156 # Number of branches committed -system.cpu1.commit.COM:bw_lim_events 195927 # number cycles where commit BW limit reached +system.cpu1.BPredUnit.BTBHits 1157962 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 2699963 # Number of BTB lookups +system.cpu1.BPredUnit.RASInCorrect 8335 # Number of incorrect RAS predictions. +system.cpu1.BPredUnit.condIncorrect 172116 # Number of conditional branches incorrect +system.cpu1.BPredUnit.condPredicted 2481640 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 2995076 # Number of BP lookups +system.cpu1.BPredUnit.usedRAS 209806 # Number of times the RAS was used to get a target. +system.cpu1.commit.COM:branches 1517916 # Number of branches committed +system.cpu1.commit.COM:bw_lim_events 197525 # number cycles where commit BW limit reached system.cpu1.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.commit.COM:committed_per_cycle::samples 17812439 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::mean 0.593209 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::stdev 1.404519 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::samples 17848598 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::mean 0.593368 # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::stdev 1.404700 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::0 13432656 75.41% 75.41% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::1 2071277 11.63% 87.04% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::2 798332 4.48% 91.52% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::3 569921 3.20% 94.72% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::4 392752 2.20% 96.93% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::5 150104 0.84% 97.77% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::6 110432 0.62% 98.39% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::7 91038 0.51% 98.90% # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::8 195927 1.10% 100.00% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::0 13459755 75.41% 75.41% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::1 2076221 11.63% 87.04% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::2 798391 4.47% 91.52% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::3 569134 3.19% 94.70% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::4 394612 2.21% 96.92% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::5 153567 0.86% 97.78% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::6 111850 0.63% 98.40% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::7 87543 0.49% 98.89% # Number of insts commited each cycle +system.cpu1.commit.COM:committed_per_cycle::8 197525 1.11% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.COM:committed_per_cycle::total 17812439 # Number of insts commited each cycle -system.cpu1.commit.COM:count 10566506 # Number of instructions committed -system.cpu1.commit.COM:loads 1991573 # Number of loads committed -system.cpu1.commit.COM:membars 52753 # Number of memory barriers committed -system.cpu1.commit.COM:refs 3374641 # Number of memory references committed +system.cpu1.commit.COM:committed_per_cycle::total 17848598 # Number of insts commited each cycle +system.cpu1.commit.COM:count 10590789 # Number of instructions committed +system.cpu1.commit.COM:loads 1991065 # Number of loads committed +system.cpu1.commit.COM:membars 52740 # Number of memory barriers committed +system.cpu1.commit.COM:refs 3374997 # Number of memory references committed system.cpu1.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.branchMispredicts 163273 # The number of times a branch was mispredicted -system.cpu1.commit.commitCommittedInsts 10566506 # The number of committed instructions -system.cpu1.commit.commitNonSpecStalls 163051 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.commitSquashedInsts 1705232 # The number of squashed insts skipped by commit -system.cpu1.committedInsts 10039690 # Number of Instructions Simulated -system.cpu1.committedInsts_total 10039690 # Number of Instructions Simulated -system.cpu1.cpi 1.952682 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 1.952682 # CPI: Total CPI of All Threads -system.cpu1.dcache.LoadLockedReq_accesses::0 46395 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 46395 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11084.323923 # average LoadLockedReq miss latency +system.cpu1.commit.branchMispredicts 164251 # The number of times a branch was mispredicted +system.cpu1.commit.commitCommittedInsts 10590789 # The number of committed instructions +system.cpu1.commit.commitNonSpecStalls 163017 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.commitSquashedInsts 1716683 # The number of squashed insts skipped by commit +system.cpu1.committedInsts 10063537 # Number of Instructions Simulated +system.cpu1.committedInsts_total 10063537 # Number of Instructions Simulated +system.cpu1.cpi 1.953144 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 1.953144 # CPI: Total CPI of All Threads +system.cpu1.dcache.LoadLockedReq_accesses::0 46385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 46385 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11093.156176 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8010.474275 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_hits::0 39665 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 39665 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_miss_latency 74597500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145059 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_misses::0 6730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 6730 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_mshr_hits 763 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47798500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128613 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8017.085427 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_hits::0 39649 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 39649 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_miss_latency 74723500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.145219 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_misses::0 6736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 6736 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_mshr_hits 766 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 47862000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.128705 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_misses 5967 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.ReadReq_accesses::0 2059923 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 2059923 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency::0 15005.371131 # average ReadReq miss latency +system.cpu1.dcache.LoadLockedReq_mshr_misses 5970 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.ReadReq_accesses::0 2063183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 2063183 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_avg_miss_latency::0 15106.279717 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11669.279162 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11684.123629 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_hits::0 1864992 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 1864992 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 2925012000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate::0 0.094630 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses::0 194931 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 194931 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_hits 99875 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_miss_latency 1109235000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046145 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_hits::0 1870531 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 1870531 # number of ReadReq hits +system.cpu1.dcache.ReadReq_miss_latency 2910255000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_rate::0 0.093376 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_misses::0 192652 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 192652 # number of ReadReq misses +system.cpu1.dcache.ReadReq_mshr_hits 97561 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_miss_latency 1111055000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.046089 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 95056 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.StoreCondReq_accesses::0 43203 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 43203 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13176.417292 # average StoreCondReq miss latency +system.cpu1.dcache.ReadReq_mshr_misses 95091 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 17677000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.StoreCondReq_accesses::0 43197 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 43197 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 13112.263417 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10174.605229 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10114.107884 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_hits::0 39340 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 39340 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_miss_latency 50900500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089415 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_misses::0 3863 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 3863 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39304500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089415 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_latency 50574000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_rate::0 0.089289 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_misses::0 3857 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 3857 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_mshr_miss_latency 39000000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.089265 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_misses 3863 # number of StoreCondReq MSHR misses -system.cpu1.dcache.WriteReq_accesses::0 1333474 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 1333474 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency::0 21222.665351 # average WriteReq miss latency +system.cpu1.dcache.StoreCondReq_mshr_misses 3856 # number of StoreCondReq MSHR misses +system.cpu1.dcache.WriteReq_accesses::0 1334344 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1334344 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_avg_miss_latency::0 21202.003457 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18784.142303 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 18758.167110 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_hits::0 1083830 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 1083830 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 5298111069 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate::0 0.187213 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses::0 249644 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 249644 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_hits 201142 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_miss_latency 911068470 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036373 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_hits::0 1085015 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1085015 # number of WriteReq hits +system.cpu1.dcache.WriteReq_miss_latency 5286274320 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_rate::0 0.186855 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_misses::0 249329 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 249329 # number of WriteReq misses +system.cpu1.dcache.WriteReq_mshr_hits 200876 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_miss_latency 908889471 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.036312 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 48502 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377673500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9931.219300 # average number of cycles each access was blocked +system.cpu1.dcache.WriteReq_mshr_misses 48453 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 377675000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10123.559438 # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 22.846422 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 5285 # number of cycles access was blocked +system.cpu1.dcache.avg_refs 22.895667 # Average number of references to valid blocks. +system.cpu1.dcache.blocked::no_mshrs 5123 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 52486494 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_mshrs 51862995 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses::0 3393397 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::0 3397527 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 3393397 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency::0 18496.593531 # average overall miss latency +system.cpu1.dcache.demand_accesses::total 3397527 # number of demand (read+write) accesses +system.cpu1.dcache.demand_avg_miss_latency::0 18544.981164 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 14073.081751 # average overall mshr miss latency -system.cpu1.dcache.demand_hits::0 2948822 # number of demand (read+write) hits +system.cpu1.dcache.demand_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency +system.cpu1.dcache.demand_hits::0 2955546 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 2948822 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 8223123069 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate::0 0.131012 # miss rate for demand accesses +system.cpu1.dcache.demand_hits::total 2955546 # number of demand (read+write) hits +system.cpu1.dcache.demand_miss_latency 8196529320 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_rate::0 0.130089 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.dcache.demand_misses::0 444575 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::0 441981 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 444575 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 301017 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 2020303470 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate::0 0.042305 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_misses::total 441981 # number of demand (read+write) misses +system.cpu1.dcache.demand_mshr_hits 298437 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_miss_latency 2019944471 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_rate::0 0.042250 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 143558 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses 143544 # number of demand (read+write) MSHR misses system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.932894 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 477.641661 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses::0 3393397 # number of overall (read+write) accesses +system.cpu1.dcache.occ_%::0 0.933247 # Average percentage of cache occupancy +system.cpu1.dcache.occ_blocks::0 477.822541 # Average occupied blocks per context +system.cpu1.dcache.overall_accesses::0 3397527 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 3393397 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency::0 18496.593531 # average overall miss latency +system.cpu1.dcache.overall_accesses::total 3397527 # number of overall (read+write) accesses +system.cpu1.dcache.overall_avg_miss_latency::0 18544.981164 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 14073.081751 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency 14071.953345 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits::0 2948822 # number of overall hits +system.cpu1.dcache.overall_hits::0 2955546 # number of overall hits system.cpu1.dcache.overall_hits::1 0 # number of overall hits -system.cpu1.dcache.overall_hits::total 2948822 # number of overall hits -system.cpu1.dcache.overall_miss_latency 8223123069 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate::0 0.131012 # miss rate for overall accesses +system.cpu1.dcache.overall_hits::total 2955546 # number of overall hits +system.cpu1.dcache.overall_miss_latency 8196529320 # number of overall miss cycles +system.cpu1.dcache.overall_miss_rate::0 0.130089 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.dcache.overall_misses::0 444575 # number of overall misses +system.cpu1.dcache.overall_misses::0 441981 # number of overall misses system.cpu1.dcache.overall_misses::1 0 # number of overall misses -system.cpu1.dcache.overall_misses::total 444575 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 301017 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 2020303470 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate::0 0.042305 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_misses::total 441981 # number of overall misses +system.cpu1.dcache.overall_mshr_hits 298437 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_miss_latency 2019944471 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_rate::0 0.042250 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 143558 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 395351000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_misses 143544 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_uncacheable_latency 395352000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 132490 # number of replacements -system.cpu1.dcache.sampled_refs 132884 # Sample count of references to valid blocks. +system.cpu1.dcache.replacements 132498 # number of replacements +system.cpu1.dcache.sampled_refs 132892 # Sample count of references to valid blocks. system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 477.641661 # Cycle average of tags in use -system.cpu1.dcache.total_refs 3035924 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 1877659074000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 88699 # number of writebacks -system.cpu1.decode.DECODE:BlockedCycles 6971990 # Number of cycles decode is blocked -system.cpu1.decode.DECODE:BranchMispred 7938 # Number of times decode detected a branch misprediction -system.cpu1.decode.DECODE:BranchResolved 127719 # Number of times decode resolved a branch -system.cpu1.decode.DECODE:DecodedInsts 13891801 # Number of instructions handled by decode -system.cpu1.decode.DECODE:IdleCycles 8246933 # Number of cycles decode is idle -system.cpu1.decode.DECODE:RunCycles 2493797 # Number of cycles decode is running -system.cpu1.decode.DECODE:SquashCycles 302659 # Number of cycles decode is squashing -system.cpu1.decode.DECODE:SquashedInsts 23688 # Number of squashed instructions handled by decode -system.cpu1.decode.DECODE:UnblockCycles 99718 # Number of cycles decode is unblocking -system.cpu1.dtb.data_accesses 452227 # DTB accesses +system.cpu1.dcache.tagsinuse 477.822541 # Cycle average of tags in use +system.cpu1.dcache.total_refs 3042651 # Total number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 1877659701000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.writebacks 88702 # number of writebacks +system.cpu1.decode.DECODE:BlockedCycles 6987029 # Number of cycles decode is blocked +system.cpu1.decode.DECODE:BranchMispred 7945 # Number of times decode detected a branch misprediction +system.cpu1.decode.DECODE:BranchResolved 127739 # Number of times decode resolved a branch +system.cpu1.decode.DECODE:DecodedInsts 13932578 # Number of instructions handled by decode +system.cpu1.decode.DECODE:IdleCycles 8260937 # Number of cycles decode is idle +system.cpu1.decode.DECODE:RunCycles 2501859 # Number of cycles decode is running +system.cpu1.decode.DECODE:SquashCycles 305063 # Number of cycles decode is squashing +system.cpu1.decode.DECODE:SquashedInsts 23694 # Number of squashed instructions handled by decode +system.cpu1.decode.DECODE:UnblockCycles 98772 # Number of cycles decode is unblocking +system.cpu1.dtb.data_accesses 453342 # DTB accesses system.cpu1.dtb.data_acv 183 # DTB access violations -system.cpu1.dtb.data_hits 3607185 # DTB hits -system.cpu1.dtb.data_misses 12842 # DTB misses +system.cpu1.dtb.data_hits 3613400 # DTB hits +system.cpu1.dtb.data_misses 12964 # DTB misses system.cpu1.dtb.fetch_accesses 0 # ITB accesses system.cpu1.dtb.fetch_acv 0 # ITB acv system.cpu1.dtb.fetch_hits 0 # ITB hits system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 320739 # DTB read accesses -system.cpu1.dtb.read_acv 82 # DTB read access violations -system.cpu1.dtb.read_hits 2181924 # DTB read hits -system.cpu1.dtb.read_misses 10502 # DTB read misses -system.cpu1.dtb.write_accesses 131488 # DTB write accesses -system.cpu1.dtb.write_acv 101 # DTB write access violations -system.cpu1.dtb.write_hits 1425261 # DTB write hits -system.cpu1.dtb.write_misses 2340 # DTB write misses -system.cpu1.fetch.Branches 2988933 # Number of branches that fetch encountered -system.cpu1.fetch.CacheLines 1669639 # Number of cache lines fetched -system.cpu1.fetch.Cycles 4303594 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.IcacheSquashes 104390 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.Insts 14140107 # Number of instructions fetch has processed -system.cpu1.fetch.MiscStallCycles 288 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.SquashCycles 190275 # Number of cycles fetch has spent squashing -system.cpu1.fetch.branchRate 0.152463 # Number of branch fetches per cycle -system.cpu1.fetch.icacheStallCycles 1669639 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.predictedBranches 1364844 # Number of branches that fetch has predicted taken -system.cpu1.fetch.rate 0.721275 # Number of inst fetches per cycle -system.cpu1.fetch.rateDist::samples 18115098 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.780570 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.128559 # Number of instructions fetched each cycle (Total) +system.cpu1.dtb.read_accesses 321975 # DTB read accesses +system.cpu1.dtb.read_acv 83 # DTB read access violations +system.cpu1.dtb.read_hits 2187186 # DTB read hits +system.cpu1.dtb.read_misses 10487 # DTB read misses +system.cpu1.dtb.write_accesses 131367 # DTB write accesses +system.cpu1.dtb.write_acv 100 # DTB write access violations +system.cpu1.dtb.write_hits 1426214 # DTB write hits +system.cpu1.dtb.write_misses 2477 # DTB write misses +system.cpu1.fetch.Branches 2995076 # Number of branches that fetch encountered +system.cpu1.fetch.CacheLines 1674453 # Number of cache lines fetched +system.cpu1.fetch.Cycles 4316686 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.IcacheSquashes 103652 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.Insts 14184875 # Number of instructions fetch has processed +system.cpu1.fetch.MiscStallCycles 463 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.SquashCycles 191233 # Number of cycles fetch has spent squashing +system.cpu1.fetch.branchRate 0.152378 # Number of branch fetches per cycle +system.cpu1.fetch.icacheStallCycles 1674453 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.predictedBranches 1367768 # Number of branches that fetch has predicted taken +system.cpu1.fetch.rate 0.721673 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::samples 18153661 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.781378 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.130034 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 15489559 85.51% 85.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 208264 1.15% 86.66% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 323571 1.79% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 199234 1.10% 89.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 375752 2.07% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 125718 0.69% 92.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 169462 0.94% 93.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 249675 1.38% 94.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 973863 5.38% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 15520231 85.49% 85.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 211004 1.16% 86.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 323759 1.78% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 198428 1.09% 89.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 375870 2.07% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 125712 0.69% 92.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 169249 0.93% 93.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 251729 1.39% 94.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 977679 5.39% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 18115098 # Number of instructions fetched each cycle (Total) -system.cpu1.icache.ReadReq_accesses::0 1669639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 1669639 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency::0 14675.575285 # average ReadReq miss latency +system.cpu1.fetch.rateDist::total 18153661 # Number of instructions fetched each cycle (Total) +system.cpu1.icache.ReadReq_accesses::0 1674453 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1674453 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_avg_miss_latency::0 14671.340426 # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11632.875773 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits::0 1406074 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 1406074 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 3867968000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate::0 0.157857 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses::0 263565 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 263565 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_hits 8225 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_miss_latency 2970338500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152931 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11628.734234 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_hits::0 1410604 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1410604 # number of ReadReq hits +system.cpu1.icache.ReadReq_miss_latency 3871018500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_rate::0 0.157573 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_misses::0 263849 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 263849 # number of ReadReq misses +system.cpu1.icache.ReadReq_mshr_hits 8241 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_miss_latency 2972397500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.152652 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 255340 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs 5055.555556 # average number of cycles each access was blocked +system.cpu1.icache.ReadReq_mshr_misses 255608 # number of ReadReq MSHR misses +system.cpu1.icache.avg_blocked_cycles::no_mshrs 4444.444444 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 5.507925 # Average number of references to valid blocks. +system.cpu1.icache.avg_refs 5.519875 # Average number of references to valid blocks. system.cpu1.icache.blocked::no_mshrs 9 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 45500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_mshrs 40000 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses::0 1669639 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::0 1674453 # number of demand (read+write) accesses system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 1669639 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency::0 14675.575285 # average overall miss latency +system.cpu1.icache.demand_accesses::total 1674453 # number of demand (read+write) accesses +system.cpu1.icache.demand_avg_miss_latency::0 14671.340426 # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 11632.875773 # average overall mshr miss latency -system.cpu1.icache.demand_hits::0 1406074 # number of demand (read+write) hits +system.cpu1.icache.demand_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency +system.cpu1.icache.demand_hits::0 1410604 # number of demand (read+write) hits system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 1406074 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 3867968000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate::0 0.157857 # miss rate for demand accesses +system.cpu1.icache.demand_hits::total 1410604 # number of demand (read+write) hits +system.cpu1.icache.demand_miss_latency 3871018500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_rate::0 0.157573 # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu1.icache.demand_misses::0 263565 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::0 263849 # number of demand (read+write) misses system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 263565 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 8225 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 2970338500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate::0 0.152931 # mshr miss rate for demand accesses +system.cpu1.icache.demand_misses::total 263849 # number of demand (read+write) misses +system.cpu1.icache.demand_mshr_hits 8241 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_miss_latency 2972397500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_rate::0 0.152652 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 255340 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses 255608 # number of demand (read+write) MSHR misses system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.occ_%::0 0.900435 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 461.022508 # Average occupied blocks per context -system.cpu1.icache.overall_accesses::0 1669639 # number of overall (read+write) accesses +system.cpu1.icache.occ_blocks::0 461.022947 # Average occupied blocks per context +system.cpu1.icache.overall_accesses::0 1674453 # number of overall (read+write) accesses system.cpu1.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 1669639 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency::0 14675.575285 # average overall miss latency +system.cpu1.icache.overall_accesses::total 1674453 # number of overall (read+write) accesses +system.cpu1.icache.overall_avg_miss_latency::0 14671.340426 # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 11632.875773 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency 11628.734234 # average overall mshr miss latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits::0 1406074 # number of overall hits +system.cpu1.icache.overall_hits::0 1410604 # number of overall hits system.cpu1.icache.overall_hits::1 0 # number of overall hits -system.cpu1.icache.overall_hits::total 1406074 # number of overall hits -system.cpu1.icache.overall_miss_latency 3867968000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate::0 0.157857 # miss rate for overall accesses +system.cpu1.icache.overall_hits::total 1410604 # number of overall hits +system.cpu1.icache.overall_miss_latency 3871018500 # number of overall miss cycles +system.cpu1.icache.overall_miss_rate::0 0.157573 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu1.icache.overall_misses::0 263565 # number of overall misses +system.cpu1.icache.overall_misses::0 263849 # number of overall misses system.cpu1.icache.overall_misses::1 0 # number of overall misses -system.cpu1.icache.overall_misses::total 263565 # number of overall misses -system.cpu1.icache.overall_mshr_hits 8225 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 2970338500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate::0 0.152931 # mshr miss rate for overall accesses +system.cpu1.icache.overall_misses::total 263849 # number of overall misses +system.cpu1.icache.overall_mshr_hits 8241 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_miss_latency 2972397500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_rate::0 0.152652 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 255340 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses 255608 # number of overall MSHR misses system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 254770 # number of replacements -system.cpu1.icache.sampled_refs 255282 # Sample count of references to valid blocks. +system.cpu1.icache.replacements 255038 # number of replacements +system.cpu1.icache.sampled_refs 255550 # Sample count of references to valid blocks. system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 461.022508 # Cycle average of tags in use -system.cpu1.icache.total_refs 1406074 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 1897916485000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 12 # number of writebacks -system.cpu1.idleCycles 1489226 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.iew.EXEC:branches 1621685 # Number of branches executed -system.cpu1.iew.EXEC:nop 600518 # number of nop insts executed -system.cpu1.iew.EXEC:rate 0.550648 # Inst execution rate -system.cpu1.iew.EXEC:refs 3638770 # number of memory reference insts executed -system.cpu1.iew.EXEC:stores 1434645 # Number of stores executed +system.cpu1.icache.tagsinuse 461.022947 # Cycle average of tags in use +system.cpu1.icache.total_refs 1410604 # Total number of references to valid blocks. +system.cpu1.icache.warmup_cycle 1897916451000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.writebacks 13 # number of writebacks +system.cpu1.idleCycles 1501880 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.iew.EXEC:branches 1627207 # Number of branches executed +system.cpu1.iew.EXEC:nop 601288 # number of nop insts executed +system.cpu1.iew.EXEC:rate 0.550852 # Inst execution rate +system.cpu1.iew.EXEC:refs 3642900 # number of memory reference insts executed +system.cpu1.iew.EXEC:stores 1435734 # Number of stores executed system.cpu1.iew.EXEC:swp 0 # number of swp insts executed -system.cpu1.iew.WB:consumers 6221893 # num instructions consuming a value -system.cpu1.iew.WB:count 10690151 # cumulative count of insts written-back -system.cpu1.iew.WB:fanout 0.737580 # average fanout of values written-back +system.cpu1.iew.WB:consumers 6254497 # num instructions consuming a value +system.cpu1.iew.WB:count 10719851 # cumulative count of insts written-back +system.cpu1.iew.WB:fanout 0.736543 # average fanout of values written-back system.cpu1.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu1.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.iew.WB:producers 4589145 # num instructions producing a value -system.cpu1.iew.WB:rate 0.545296 # insts written-back per cycle -system.cpu1.iew.WB:sent 10713297 # cumulative count of insts sent to commit -system.cpu1.iew.branchMispredicts 177050 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewBlockCycles 257506 # Number of cycles IEW is blocking -system.cpu1.iew.iewDispLoadInsts 2306314 # Number of dispatched load instructions -system.cpu1.iew.iewDispNonSpecInsts 500674 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewDispSquashedInsts 208241 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispStoreInsts 1509678 # Number of dispatched store instructions -system.cpu1.iew.iewDispatchedInsts 12354884 # Number of instructions dispatched to IQ -system.cpu1.iew.iewExecLoadInsts 2204125 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 106415 # Number of squashed instructions skipped in execute -system.cpu1.iew.iewExecutedInsts 10795075 # Number of executed instructions -system.cpu1.iew.iewIQFullEvents 2676 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.WB:producers 4606706 # num instructions producing a value +system.cpu1.iew.WB:rate 0.545386 # insts written-back per cycle +system.cpu1.iew.WB:sent 10743061 # cumulative count of insts sent to commit +system.cpu1.iew.branchMispredicts 178420 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewBlockCycles 265381 # Number of cycles IEW is blocking +system.cpu1.iew.iewDispLoadInsts 2308328 # Number of dispatched load instructions +system.cpu1.iew.iewDispNonSpecInsts 500549 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewDispSquashedInsts 208852 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispStoreInsts 1509637 # Number of dispatched store instructions +system.cpu1.iew.iewDispatchedInsts 12390699 # Number of instructions dispatched to IQ +system.cpu1.iew.iewExecLoadInsts 2207166 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 106974 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 10827293 # Number of executed instructions +system.cpu1.iew.iewIQFullEvents 2483 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewLSQFullEvents 4880 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.iewSquashCycles 302659 # Number of cycles IEW is squashing -system.cpu1.iew.iewUnblockCycles 10387 # Number of cycles IEW is unblocking +system.cpu1.iew.iewLSQFullEvents 4852 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.iewSquashCycles 305063 # Number of cycles IEW is squashing +system.cpu1.iew.iewUnblockCycles 10314 # Number of cycles IEW is unblocking system.cpu1.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread.0.cacheBlocked 20658 # Number of times an access to memory failed due to the cache being blocked -system.cpu1.iew.lsq.thread.0.forwLoads 67397 # Number of loads that had data forwarded from stores -system.cpu1.iew.lsq.thread.0.ignoredResponses 2150 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread.0.cacheBlocked 22342 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread.0.forwLoads 67469 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread.0.ignoredResponses 2212 # Number of memory responses ignored because the instruction is squashed system.cpu1.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu1.iew.lsq.thread.0.memOrderViolation 10614 # Number of memory ordering violations -system.cpu1.iew.lsq.thread.0.rescheduledLoads 379 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread.0.squashedLoads 314741 # Number of loads squashed -system.cpu1.iew.lsq.thread.0.squashedStores 126610 # Number of stores squashed -system.cpu1.iew.memOrderViolationEvents 10614 # Number of memory order violations -system.cpu1.iew.predictedNotTakenIncorrect 104614 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.predictedTakenIncorrect 72436 # Number of branches that were predicted taken incorrectly -system.cpu1.ipc 0.512116 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.512116 # IPC: Total IPC of All Threads +system.cpu1.iew.lsq.thread.0.memOrderViolation 10592 # Number of memory ordering violations +system.cpu1.iew.lsq.thread.0.rescheduledLoads 380 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread.0.squashedLoads 317263 # Number of loads squashed +system.cpu1.iew.lsq.thread.0.squashedStores 125705 # Number of stores squashed +system.cpu1.iew.memOrderViolationEvents 10592 # Number of memory order violations +system.cpu1.iew.predictedNotTakenIncorrect 104736 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.predictedTakenIncorrect 73684 # Number of branches that were predicted taken incorrectly +system.cpu1.ipc 0.511995 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.511995 # IPC: Total IPC of All Threads system.cpu1.iq.ISSUE:FU_type_0::No_OpClass 3525 0.03% 0.03% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6828006 62.63% 62.67% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntMult 17554 0.16% 62.83% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.83% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 62.93% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 62.93% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 62.93% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 62.93% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 62.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemRead 2279720 20.91% 83.86% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1451557 13.32% 97.18% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307934 2.82% 100.00% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntAlu 6856403 62.71% 62.74% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntMult 17935 0.16% 62.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatAdd 11432 0.10% 63.01% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 63.01% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 63.01% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 63.01% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatDiv 1762 0.02% 63.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 63.02% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemRead 2282654 20.88% 83.90% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::MemWrite 1452686 13.29% 97.18% # Type of FU issued +system.cpu1.iq.ISSUE:FU_type_0::IprAccess 307870 2.82% 100.00% # Type of FU issued system.cpu1.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.ISSUE:FU_type_0::total 10901490 # Type of FU issued -system.cpu1.iq.ISSUE:fu_busy_cnt 154119 # FU busy when requested -system.cpu1.iq.ISSUE:fu_busy_rate 0.014137 # FU busy rate (busy events/executed inst) +system.cpu1.iq.ISSUE:FU_type_0::total 10934267 # Type of FU issued +system.cpu1.iq.ISSUE:fu_busy_cnt 157620 # FU busy when requested +system.cpu1.iq.ISSUE:fu_busy_rate 0.014415 # FU busy rate (busy events/executed inst) system.cpu1.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntAlu 3997 2.59% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.59% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemRead 90686 58.84% 61.43% # attempts to use FU when none available -system.cpu1.iq.ISSUE:fu_full::MemWrite 59436 38.57% 100.00% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntAlu 4070 2.58% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntMult 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::IntDiv 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatAdd 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCmp 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatCvt 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatMult 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatDiv 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 2.58% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemRead 93965 59.61% 62.20% # attempts to use FU when none available +system.cpu1.iq.ISSUE:fu_full::MemWrite 59585 37.80% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.ISSUE:issued_per_cycle::samples 18115098 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.601790 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.204979 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::samples 18153661 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::mean 0.602317 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::stdev 1.206394 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::0 12897978 71.20% 71.20% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::1 2566961 14.17% 85.37% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::2 1067808 5.89% 91.27% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::3 689821 3.81% 95.07% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::4 522358 2.88% 97.96% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::5 233805 1.29% 99.25% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::6 92642 0.51% 99.76% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::7 34659 0.19% 99.95% # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::8 9066 0.05% 100.00% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::0 12924725 71.20% 71.20% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::1 2574747 14.18% 85.38% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::2 1068107 5.88% 91.26% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::3 685428 3.78% 95.04% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::4 525394 2.89% 97.93% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::5 238254 1.31% 99.25% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::6 93756 0.52% 99.76% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::7 34360 0.19% 99.95% # Number of insts issued each cycle +system.cpu1.iq.ISSUE:issued_per_cycle::8 8890 0.05% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:issued_per_cycle::total 18115098 # Number of insts issued each cycle -system.cpu1.iq.ISSUE:rate 0.556076 # Inst issue rate -system.cpu1.iq.iqInstsAdded 11198244 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqInstsIssued 10901490 # Number of instructions issued -system.cpu1.iq.iqNonSpecInstsAdded 556122 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqSquashedInstsExamined 1641267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedInstsIssued 10273 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedNonSpecRemoved 393071 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.iqSquashedOperandsExamined 839516 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.ISSUE:issued_per_cycle::total 18153661 # Number of insts issued each cycle +system.cpu1.iq.ISSUE:rate 0.556294 # Inst issue rate +system.cpu1.iq.iqInstsAdded 11233407 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqInstsIssued 10934267 # Number of instructions issued +system.cpu1.iq.iqNonSpecInstsAdded 556004 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqSquashedInstsExamined 1651489 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedInstsIssued 10261 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedNonSpecRemoved 392987 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.iqSquashedOperandsExamined 847945 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.itb.data_accesses 0 # DTB accesses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_hits 0 # DTB hits system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 447863 # ITB accesses -system.cpu1.itb.fetch_acv 278 # ITB acv -system.cpu1.itb.fetch_hits 439724 # ITB hits -system.cpu1.itb.fetch_misses 8139 # ITB misses +system.cpu1.itb.fetch_accesses 448239 # ITB accesses +system.cpu1.itb.fetch_acv 291 # ITB acv +system.cpu1.itb.fetch_hits 439727 # ITB hits +system.cpu1.itb.fetch_misses 8512 # ITB misses system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.read_acv 0 # DTB read access violations system.cpu1.itb.read_hits 0 # DTB read hits @@ -1006,14 +1006,14 @@ system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu1.kern.callpal::wripir 254 0.44% 0.45% # number of callpals executed +system.cpu1.kern.callpal::wripir 254 0.45% 0.45% # number of callpals executed system.cpu1.kern.callpal::wrmces 1 0.00% 0.45% # number of callpals executed system.cpu1.kern.callpal::wrfen 1 0.00% 0.45% # number of callpals executed system.cpu1.kern.callpal::swpctx 1450 2.54% 2.99% # number of callpals executed system.cpu1.kern.callpal::tbi 12 0.02% 3.01% # number of callpals executed system.cpu1.kern.callpal::wrent 7 0.01% 3.02% # number of callpals executed -system.cpu1.kern.callpal::swpipl 49382 86.51% 89.53% # number of callpals executed -system.cpu1.kern.callpal::rdps 2383 4.17% 93.71% # number of callpals executed +system.cpu1.kern.callpal::swpipl 49367 86.50% 89.53% # number of callpals executed +system.cpu1.kern.callpal::rdps 2383 4.18% 93.70% # number of callpals executed system.cpu1.kern.callpal::wrkgp 1 0.00% 93.71% # number of callpals executed system.cpu1.kern.callpal::wrusp 4 0.01% 93.71% # number of callpals executed system.cpu1.kern.callpal::rdusp 2 0.00% 93.72% # number of callpals executed @@ -1022,42 +1022,42 @@ system.cpu1.kern.callpal::callsys 187 0.33% 99.92% # number of callpals executed system.cpu1.kern.callpal::imb 43 0.08% 100.00% # number of callpals executed system.cpu1.kern.callpal::rdunique 1 0.00% 100.00% # number of callpals executed -system.cpu1.kern.callpal::total 57084 # number of callpals executed +system.cpu1.kern.callpal::total 57069 # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 64923 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 64908 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2510 # number of quiesce instructions executed -system.cpu1.kern.ipl_count::0 20673 37.58% 37.58% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::22 1922 3.49% 41.08% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::0 20666 37.58% 37.58% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::22 1922 3.49% 41.07% # number of times we switched to this ipl system.cpu1.kern.ipl_count::30 351 0.64% 41.71% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::31 32062 58.29% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_count::total 55008 # number of times we switched to this ipl -system.cpu1.kern.ipl_good::0 20166 47.73% 47.73% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::22 1922 4.55% 52.27% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count::31 32054 58.29% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_count::total 54993 # number of times we switched to this ipl +system.cpu1.kern.ipl_good::0 20159 47.72% 47.72% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::22 1922 4.55% 52.28% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::30 351 0.83% 53.11% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::31 19815 46.89% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good::total 42254 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1870782192000 98.44% 98.44% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 347977500 0.02% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::30 137627500 0.01% 98.46% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 29209741000 1.54% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1900477538000 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used::0 0.975475 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_good::31 19808 46.89% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good::total 42240 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks::0 1870788653000 98.44% 98.44% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 347996000 0.02% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::30 137644000 0.01% 98.46% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 29218866000 1.54% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1900493159000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used::0 0.975467 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used::31 0.618021 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.mode_good::kernel 849 -system.cpu1.kern.mode_good::user 573 +system.cpu1.kern.ipl_used::31 0.617957 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.mode_good::kernel 848 +system.cpu1.kern.mode_good::user 572 system.cpu1.kern.mode_good::idle 276 -system.cpu1.kern.mode_switch::kernel 1769 # number of protection mode switches -system.cpu1.kern.mode_switch::user 573 # number of protection mode switches -system.cpu1.kern.mode_switch::idle 2540 # number of protection mode switches -system.cpu1.kern.mode_switch_good::kernel 0.479932 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch::kernel 1766 # number of protection mode switches +system.cpu1.kern.mode_switch::user 572 # number of protection mode switches +system.cpu1.kern.mode_switch::idle 2543 # number of protection mode switches +system.cpu1.kern.mode_switch_good::kernel 0.480181 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::idle 0.108661 # fraction of useful protection mode switches -system.cpu1.kern.mode_switch_good::total 1.588594 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 6304093000 0.33% 0.33% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1020319500 0.05% 0.39% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1893140641500 99.61% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_switch_good::idle 0.108533 # fraction of useful protection mode switches +system.cpu1.kern.mode_switch_good::total 1.588714 # fraction of useful protection mode switches +system.cpu1.kern.mode_ticks::kernel 6310117500 0.33% 0.33% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1035001500 0.05% 0.39% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1893135458000 99.61% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 1451 # number of times the context was actually changed system.cpu1.kern.syscall::2 2 1.60% 1.60% # number of syscalls executed system.cpu1.kern.syscall::3 13 10.40% 12.00% # number of syscalls executed @@ -1082,29 +1082,29 @@ system.cpu1.kern.syscall::132 3 2.40% 99.20% # number of syscalls executed system.cpu1.kern.syscall::144 1 0.80% 100.00% # number of syscalls executed system.cpu1.kern.syscall::total 125 # number of syscalls executed -system.cpu1.memDep0.conflictingLoads 493721 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 420829 # Number of conflicting stores. -system.cpu1.memDep0.insertedLoads 2306314 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 1509678 # Number of stores inserted to the mem dependence unit. -system.cpu1.numCycles 19604324 # number of cpu cycles simulated -system.cpu1.rename.RENAME:BlockCycles 523322 # Number of cycles rename is blocking -system.cpu1.rename.RENAME:CommittedMaps 7130376 # Number of HB maps that are committed -system.cpu1.rename.RENAME:IQFullEvents 34965 # Number of times rename has blocked due to IQ full -system.cpu1.rename.RENAME:IdleCycles 8479727 # Number of cycles rename is idle -system.cpu1.rename.RENAME:LSQFullEvents 256792 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RENAME:ROBFullEvents 15396 # Number of times rename has blocked due to ROB full -system.cpu1.rename.RENAME:RenameLookups 15372563 # Number of register rename lookups that rename has made -system.cpu1.rename.RENAME:RenamedInsts 12869198 # Number of instructions processed by rename -system.cpu1.rename.RENAME:RenamedOperands 8442140 # Number of destination operands rename has renamed -system.cpu1.rename.RENAME:RunCycles 2348315 # Number of cycles rename is running -system.cpu1.rename.RENAME:SquashCycles 302659 # Number of cycles rename is squashing -system.cpu1.rename.RENAME:UnblockCycles 803488 # Number of cycles rename is unblocking -system.cpu1.rename.RENAME:UndoneMaps 1311764 # Number of HB maps that are undone due to squashing -system.cpu1.rename.RENAME:serializeStallCycles 5657585 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RENAME:serializingInsts 515686 # count of serializing insts renamed -system.cpu1.rename.RENAME:skidInsts 2307049 # count of insts added to the skid buffer -system.cpu1.rename.RENAME:tempSerializingInsts 52733 # count of temporary serializing insts renamed -system.cpu1.timesIdled 194546 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.memDep0.conflictingLoads 486173 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 418032 # Number of conflicting stores. +system.cpu1.memDep0.insertedLoads 2308328 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1509637 # Number of stores inserted to the mem dependence unit. +system.cpu1.numCycles 19655541 # number of cpu cycles simulated +system.cpu1.rename.RENAME:BlockCycles 539966 # Number of cycles rename is blocking +system.cpu1.rename.RENAME:CommittedMaps 7148793 # Number of HB maps that are committed +system.cpu1.rename.RENAME:IQFullEvents 37026 # Number of times rename has blocked due to IQ full +system.cpu1.rename.RENAME:IdleCycles 8494445 # Number of cycles rename is idle +system.cpu1.rename.RENAME:LSQFullEvents 255442 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RENAME:ROBFullEvents 15493 # Number of times rename has blocked due to ROB full +system.cpu1.rename.RENAME:RenameLookups 15440476 # Number of register rename lookups that rename has made +system.cpu1.rename.RENAME:RenamedInsts 12911511 # Number of instructions processed by rename +system.cpu1.rename.RENAME:RenamedOperands 8475661 # Number of destination operands rename has renamed +system.cpu1.rename.RENAME:RunCycles 2354555 # Number of cycles rename is running +system.cpu1.rename.RENAME:SquashCycles 305063 # Number of cycles rename is squashing +system.cpu1.rename.RENAME:UnblockCycles 804143 # Number of cycles rename is unblocking +system.cpu1.rename.RENAME:UndoneMaps 1326868 # Number of HB maps that are undone due to squashing +system.cpu1.rename.RENAME:serializeStallCycles 5655487 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RENAME:serializingInsts 515592 # count of serializing insts renamed +system.cpu1.rename.RENAME:skidInsts 2314825 # count of insts added to the skid buffer +system.cpu1.rename.RENAME:tempSerializingInsts 52743 # count of temporary serializing insts renamed +system.cpu1.timesIdled 195289 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -1135,37 +1135,37 @@ system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137710.430449 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137698.469532 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85706.873219 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722143806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85694.888285 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5721646806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561291996 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3560793998 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6177.017118 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6175.166651 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.blocked::no_mshrs 10457 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 10459 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64593068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64586068 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41724 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41724 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137617.913048 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137606.001438 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85614.370482 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5741969804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5741472804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -1173,7 +1173,7 @@ system.iocache.demand_misses::1 41724 # number of demand (read+write) misses system.iocache.demand_misses::total 41724 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572173994 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3571675996 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -1181,20 +1181,20 @@ system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.029205 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 0.467285 # Average occupied blocks per context +system.iocache.occ_%::1 0.029213 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 0.467409 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41724 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41724 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137617.913048 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137606.001438 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85614.370482 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85602.434954 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5741969804 # number of overall miss cycles +system.iocache.overall_miss_latency 5741472804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -1202,7 +1202,7 @@ system.iocache.overall_misses::1 41724 # number of overall misses system.iocache.overall_misses::total 41724 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572173994 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3571675996 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -1212,196 +1212,196 @@ system.iocache.replacements 41692 # number of replacements system.iocache.sampled_refs 41708 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 0.467285 # Cycle average of tags in use +system.iocache.tagsinuse 0.467409 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711286407000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711286220000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41520 # number of writebacks -system.l2c.ReadExReq_accesses::0 257280 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 42301 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 299581 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 55984.106319 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 837903.858521 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 257299 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 42275 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 299574 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 55985.285399 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 837699.087169 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::2 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40324.237567 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 140913 # number of ReadExReq hits -system.l2c.ReadExReq_hits::1 34526 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 175439 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6514702500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.452297 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 0.183802 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 116367 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 7775 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 124142 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 5005931500 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.482517 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 2.934730 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40323.891140 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 140918 # number of ReadExReq hits +system.l2c.ReadExReq_hits::1 34497 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 175415 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6515623500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.452318 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::1 0.183986 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 116381 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 7778 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 124159 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 5006574000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.482548 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 2.936937 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::2 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 124142 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 1807521 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 343124 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2150645 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52801.759863 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 3686733.249197 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 124159 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 1807451 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 343425 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2150876 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52799.873154 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 3686022.252810 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::2 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40018.781571 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40018.119229 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1503236 # number of ReadReq hits -system.l2c.ReadReq_hits::1 338766 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1842002 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16066783500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.168344 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.012701 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 304285 # number of ReadReq misses -system.l2c.ReadReq_misses::1 4358 # number of ReadReq misses -system.l2c.ReadReq_misses::total 308643 # number of ReadReq misses +system.l2c.ReadReq_hits::0 1503144 # number of ReadReq hits +system.l2c.ReadReq_hits::1 339066 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1842210 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16067371000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.168363 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.012693 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 304307 # number of ReadReq misses +system.l2c.ReadReq_misses::1 4359 # number of ReadReq misses +system.l2c.ReadReq_misses::total 308666 # number of ReadReq misses system.l2c.ReadReq_mshr_hits 16 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 12350876500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.170746 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 0.899462 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_latency 12351592500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.170765 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 0.898741 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::2 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 308627 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 840467500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 597 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::1 609 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1206 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_avg_miss_latency::0 4976.234004 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::1 4685.025818 # average SCUpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 308650 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 840468500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 609 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::1 601 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1210 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_avg_miss_latency::0 4894.075404 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::1 4740.869565 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::2 inf # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total inf # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40010.195035 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_hits::0 50 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::1 28 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40013.692580 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_hits::0 52 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::1 26 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 78 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_miss_latency 2722000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_rate::0 0.916248 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::1 0.954023 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_misses::0 547 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::1 581 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1128 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_mshr_miss_latency 45131500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.889447 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.852217 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_latency 2726000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_rate::0 0.914614 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::1 0.956739 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_misses::0 557 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::1 575 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1132 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_mshr_miss_latency 45295500 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_rate::0 1.858785 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::1 1.883527 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_misses 1128 # number of SCUpgradeReq MSHR misses -system.l2c.UpgradeReq_accesses::0 2889 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 1652 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 4541 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 5869.326501 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 12325.134512 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_mshr_misses 1132 # number of SCUpgradeReq MSHR misses +system.l2c.UpgradeReq_accesses::0 2884 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 1624 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 4508 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 5854.945055 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 12526.645768 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::2 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.488966 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 157 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::1 351 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 508 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 16035000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.945656 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::1 0.787530 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2732 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 1301 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 4033 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 161386500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 1.395985 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 2.441283 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 40016.724913 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 154 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::1 348 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 502 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 15984000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.946602 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::1 0.785714 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 2730 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 1276 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 4006 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 160307000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 1.389043 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 2.466749 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::2 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 4033 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 4006 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1532909498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 810428 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 810428 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 810428 # number of Writeback hits -system.l2c.Writeback_hits::total 810428 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1533340998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 810378 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 810378 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 810378 # number of Writeback hits +system.l2c.Writeback_hits::total 810378 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.655479 # Average number of references to valid blocks. +system.l2c.avg_refs 5.650924 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2064801 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 385425 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2064750 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 385700 # number of demand (read+write) accesses system.l2c.demand_accesses::2 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2450226 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 53682.107776 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 1861162.614358 # average overall miss latency +system.l2c.demand_accesses::total 2450450 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 53681.099770 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 1860673.518992 # average overall miss latency system.l2c.demand_avg_miss_latency::2 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40106.403185 # average overall mshr miss latency -system.l2c.demand_hits::0 1644149 # number of demand (read+write) hits -system.l2c.demand_hits::1 373292 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency +system.l2c.demand_hits::0 1644062 # number of demand (read+write) hits +system.l2c.demand_hits::1 373563 # number of demand (read+write) hits system.l2c.demand_hits::2 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 2017441 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22581486000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.203725 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.031480 # miss rate for demand accesses +system.l2c.demand_hits::total 2017625 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22582994500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.203748 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.031467 # miss rate for demand accesses system.l2c.demand_miss_rate::2 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 420652 # number of demand (read+write) misses -system.l2c.demand_misses::1 12133 # number of demand (read+write) misses +system.l2c.demand_misses::0 420688 # number of demand (read+write) misses +system.l2c.demand_misses::1 12137 # number of demand (read+write) misses system.l2c.demand_misses::2 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 432785 # number of demand (read+write) misses +system.l2c.demand_misses::total 432825 # number of demand (read+write) misses system.l2c.demand_mshr_hits 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17356808000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.209594 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 1.122836 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_latency 17358166500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.209618 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 1.122139 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::2 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 432769 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 432809 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187903 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.005747 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.351863 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12314.431078 # Average occupied blocks per context -system.l2c.occ_blocks::1 376.630124 # Average occupied blocks per context -system.l2c.occ_blocks::2 23059.694781 # Average occupied blocks per context -system.l2c.overall_accesses::0 2064801 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 385425 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.187928 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.005741 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.351843 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12316.075760 # Average occupied blocks per context +system.l2c.occ_blocks::1 376.251227 # Average occupied blocks per context +system.l2c.occ_blocks::2 23058.372205 # Average occupied blocks per context +system.l2c.overall_accesses::0 2064750 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 385700 # number of overall (read+write) accesses system.l2c.overall_accesses::2 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2450226 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 53682.107776 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 1861162.614358 # average overall miss latency +system.l2c.overall_accesses::total 2450450 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 53681.099770 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 1860673.518992 # average overall miss latency system.l2c.overall_avg_miss_latency::2 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40106.403185 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40105.835368 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1644149 # number of overall hits -system.l2c.overall_hits::1 373292 # number of overall hits +system.l2c.overall_hits::0 1644062 # number of overall hits +system.l2c.overall_hits::1 373563 # number of overall hits system.l2c.overall_hits::2 0 # number of overall hits -system.l2c.overall_hits::total 2017441 # number of overall hits -system.l2c.overall_miss_latency 22581486000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.203725 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.031480 # miss rate for overall accesses +system.l2c.overall_hits::total 2017625 # number of overall hits +system.l2c.overall_miss_latency 22582994500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.203748 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.031467 # miss rate for overall accesses system.l2c.overall_miss_rate::2 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 420652 # number of overall misses -system.l2c.overall_misses::1 12133 # number of overall misses +system.l2c.overall_misses::0 420688 # number of overall misses +system.l2c.overall_misses::1 12137 # number of overall misses system.l2c.overall_misses::2 0 # number of overall misses -system.l2c.overall_misses::total 432785 # number of overall misses +system.l2c.overall_misses::total 432825 # number of overall misses system.l2c.overall_mshr_hits 16 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17356808000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.209594 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 1.122836 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency 17358166500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.209618 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 1.122139 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::2 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 432769 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 2373376998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 432809 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 2373809498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 395546 # number of replacements -system.l2c.sampled_refs 431605 # Sample count of references to valid blocks. +system.l2c.replacements 395557 # number of replacements +system.l2c.sampled_refs 431639 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 35750.755983 # Cycle average of tags in use -system.l2c.total_refs 2440933 # Total number of references to valid blocks. +system.l2c.tagsinuse 35750.699192 # Cycle average of tags in use +system.l2c.total_refs 2439159 # Total number of references to valid blocks. system.l2c.warmup_cycle 9270445000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 121345 # number of writebacks +system.l2c.writebacks 121360 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -356,7 +356,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -376,7 +376,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -502,7 +502,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,12 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:17:56 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/opt/long/10.linux-boot/alpha/linux/tsunami-o3 +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:00:25 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3 Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1865720303500 because m5_exit instruction encountered +Exiting @ tick 1866702027500 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,447 +1,447 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 159619 # Simulator instruction rate (inst/s) -host_mem_usage 280620 # Number of bytes of host memory used -host_seconds 332.38 # Real time elapsed on the host -host_tick_rate 5613142222 # Simulator tick rate (ticks/s) +host_inst_rate 198948 # Simulator instruction rate (inst/s) +host_mem_usage 325560 # Number of bytes of host memory used +host_seconds 266.67 # Real time elapsed on the host +host_tick_rate 7000163701 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 53054978 # Number of instructions simulated -sim_seconds 1.865720 # Number of seconds simulated -sim_ticks 1865720303500 # Number of ticks simulated +sim_insts 53052455 # Number of instructions simulated +sim_seconds 1.866702 # Number of seconds simulated +sim_ticks 1866702027500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 6622960 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 12821186 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 40564 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 813627 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 11934155 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 14336611 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1015763 # Number of times the RAS was used to get a target. -system.cpu.commit.COM:branches 8457975 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 1007897 # number cycles where commit BW limit reached +system.cpu.BPredUnit.BTBHits 6621213 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 12790882 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 40565 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 813829 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 11937472 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 14341052 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1015322 # Number of times the RAS was used to get a target. +system.cpu.commit.COM:branches 8457404 # Number of branches committed +system.cpu.commit.COM:bw_lim_events 1008788 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 89507255 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 0.628419 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.391887 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 89226144 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 0.630371 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.393749 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 65378590 73.04% 73.04% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 10678414 11.93% 84.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 6017811 6.72% 91.70% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 2845727 3.18% 94.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2113660 2.36% 97.24% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 688870 0.77% 98.01% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 399291 0.45% 98.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 376995 0.42% 98.87% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 1007897 1.13% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 65115177 72.98% 72.98% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 10635450 11.92% 84.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 6055707 6.79% 91.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 2838740 3.18% 94.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2097041 2.35% 97.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 703016 0.79% 98.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 396600 0.44% 98.45% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 375625 0.42% 98.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 1008788 1.13% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 89507255 # Number of insts commited each cycle -system.cpu.commit.COM:count 56248094 # Number of instructions committed -system.cpu.commit.COM:loads 9303211 # Number of loads committed -system.cpu.commit.COM:membars 227966 # Number of memory barriers committed -system.cpu.commit.COM:refs 15692722 # Number of memory references committed +system.cpu.commit.COM:committed_per_cycle::total 89226144 # Number of insts commited each cycle +system.cpu.commit.COM:count 56245607 # Number of instructions committed +system.cpu.commit.COM:loads 9107515 # Number of loads committed +system.cpu.commit.COM:membars 227978 # Number of memory barriers committed +system.cpu.commit.COM:refs 15496786 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 772391 # The number of times a branch was mispredicted -system.cpu.commit.commitCommittedInsts 56248094 # The number of committed instructions -system.cpu.commit.commitNonSpecStalls 667633 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8673540 # The number of squashed insts skipped by commit -system.cpu.committedInsts 53054978 # Number of Instructions Simulated -system.cpu.committedInsts_total 53054978 # Number of Instructions Simulated -system.cpu.cpi 2.357684 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.357684 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses::0 215825 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 215825 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14729.331951 # average LoadLockedReq miss latency +system.cpu.commit.branchMispredicts 772588 # The number of times a branch was mispredicted +system.cpu.commit.commitCommittedInsts 56245607 # The number of committed instructions +system.cpu.commit.commitNonSpecStalls 667624 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.commitSquashedInsts 8707015 # The number of squashed insts skipped by commit +system.cpu.committedInsts 53052455 # Number of Instructions Simulated +system.cpu.committedInsts_total 53052455 # Number of Instructions Simulated +system.cpu.cpi 2.357033 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.357033 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses::0 215727 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 215727 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14718.915641 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11874.503483 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_hits::0 193641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 193641 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_miss_latency 326755500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.102787 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_misses::0 22184 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22184 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_mshr_hits 4813 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206272000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080487 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11880.303464 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_hits::0 193465 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 193465 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_miss_latency 327672500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_rate::0 0.103195 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_misses::0 22262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 22262 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_mshr_hits 4797 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_miss_latency 207489500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.080959 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_misses 17371 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses::0 9299177 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 9299177 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency::0 22716.761778 # average ReadReq miss latency +system.cpu.dcache.LoadLockedReq_mshr_misses 17465 # number of LoadLockedReq MSHR misses +system.cpu.dcache.ReadReq_accesses::0 9301609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 9301609 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency::0 22726.604176 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22778.216619 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22780.008433 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_hits::0 7724529 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7724529 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 35770903500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate::0 0.169332 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses::0 1574648 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1574648 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 490606 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 24692543500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116574 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_hits::0 7726221 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7726221 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 35803219500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate::0 0.169367 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses::0 1575388 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1575388 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 491526 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 24690385500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.116524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1084042 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906118000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.StoreCondReq_accesses::0 219742 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 219742 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.ReadReq_mshr_misses 1083862 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906011000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.StoreCondReq_accesses::0 219693 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 219693 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14000 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_hits::0 219738 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 219738 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_miss_latency 56000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_rate::0 0.000018 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_misses::0 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_mshr_miss_latency 44000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000018 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_hits::0 219690 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 219690 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_miss_latency 42000 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_rate::0 0.000014 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_misses::0 3 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 3 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_mshr_miss_latency 33000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000014 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_misses 4 # number of StoreCondReq MSHR misses -system.cpu.dcache.WriteReq_accesses::0 6154612 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6154612 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency::0 29779.159103 # average WriteReq miss latency +system.cpu.dcache.StoreCondReq_mshr_misses 3 # number of StoreCondReq MSHR misses +system.cpu.dcache.WriteReq_accesses::0 6154417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 6154417 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_avg_miss_latency::0 29746.241624 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28090.813701 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28089.562806 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_hits::0 4298505 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4298505 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 55273305665 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate::0 0.301580 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses::0 1856107 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1856107 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 1556374 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 8419743863 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048701 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_hits::0 4299174 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 4299174 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 55186506550 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate::0 0.301449 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses::0 1855243 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 1855243 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 1555600 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 8416840868 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048687 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 299733 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235249998 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8585.120096 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 8.876782 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 86206 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 740088863 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 29000 # number of cycles access was blocked +system.cpu.dcache.WriteReq_mshr_misses 299643 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1235850498 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.avg_blocked_cycles::no_mshrs 8970.438750 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 8.879414 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 83323 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 747443868 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses::0 15453789 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::0 15456026 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 15453789 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency::0 26537.659834 # average overall miss latency +system.cpu.dcache.demand_accesses::total 15456026 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency::0 26522.737668 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23928.953307 # average overall mshr miss latency -system.cpu.dcache.demand_hits::0 12023034 # number of demand (read+write) hits +system.cpu.dcache.demand_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency +system.cpu.dcache.demand_hits::0 12025395 # number of demand (read+write) hits system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 12023034 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 91044209165 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate::0 0.222001 # miss rate for demand accesses +system.cpu.dcache.demand_hits::total 12025395 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 90989726050 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate::0 0.221961 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.demand_misses::0 3430755 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::0 3430631 # number of demand (read+write) misses system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3430755 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 2046980 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 33112287363 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate::0 0.089543 # mshr miss rate for demand accesses +system.cpu.dcache.demand_misses::total 3430631 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2047126 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 33107226368 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate::0 0.089512 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1383775 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 1383505 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999991 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 511.995487 # Average occupied blocks per context -system.cpu.dcache.overall_accesses::0 15453789 # number of overall (read+write) accesses +system.cpu.dcache.occ_blocks::0 511.995490 # Average occupied blocks per context +system.cpu.dcache.overall_accesses::0 15456026 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 15453789 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency::0 26537.659834 # average overall miss latency +system.cpu.dcache.overall_accesses::total 15456026 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency::0 26522.737668 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23928.953307 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 23929.965102 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits::0 12023034 # number of overall hits +system.cpu.dcache.overall_hits::0 12025395 # number of overall hits system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 12023034 # number of overall hits -system.cpu.dcache.overall_miss_latency 91044209165 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate::0 0.222001 # miss rate for overall accesses +system.cpu.dcache.overall_hits::total 12025395 # number of overall hits +system.cpu.dcache.overall_miss_latency 90989726050 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate::0 0.221961 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.overall_misses::0 3430755 # number of overall misses +system.cpu.dcache.overall_misses::0 3430631 # number of overall misses system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 3430755 # number of overall misses -system.cpu.dcache.overall_mshr_hits 2046980 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 33112287363 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate::0 0.089543 # mshr miss rate for overall accesses +system.cpu.dcache.overall_misses::total 3430631 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2047126 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 33107226368 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate::0 0.089512 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1383775 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 2141367998 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_misses 1383505 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_uncacheable_latency 2141861498 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1400502 # number of replacements -system.cpu.dcache.sampled_refs 1401014 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1400326 # number of replacements +system.cpu.dcache.sampled_refs 1400838 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 511.995487 # Cycle average of tags in use -system.cpu.dcache.total_refs 12436496 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 511.995490 # Cycle average of tags in use +system.cpu.dcache.total_refs 12438621 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 21271000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 832844 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 38077949 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 42141 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 613000 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 71339111 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 37499395 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 12847543 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1512175 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 134289 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1082367 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 1229801 # DTB accesses -system.cpu.dtb.data_acv 813 # DTB access violations -system.cpu.dtb.data_hits 16587007 # DTB hits -system.cpu.dtb.data_misses 46930 # DTB misses +system.cpu.dcache.writebacks 832750 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 37798869 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 42152 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 613702 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 71408267 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 37495225 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 12847618 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1517170 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 134367 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1084431 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 1236579 # DTB accesses +system.cpu.dtb.data_acv 821 # DTB access violations +system.cpu.dtb.data_hits 16598484 # DTB hits +system.cpu.dtb.data_misses 46851 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 909497 # DTB read accesses -system.cpu.dtb.read_acv 578 # DTB read access violations -system.cpu.dtb.read_hits 10001234 # DTB read hits -system.cpu.dtb.read_misses 38618 # DTB read misses -system.cpu.dtb.write_accesses 320304 # DTB write accesses -system.cpu.dtb.write_acv 235 # DTB write access violations -system.cpu.dtb.write_hits 6585773 # DTB write hits -system.cpu.dtb.write_misses 8312 # DTB write misses -system.cpu.fetch.Branches 14336611 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 8856375 # Number of cache lines fetched -system.cpu.fetch.Cycles 23007170 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 453326 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 72609191 # Number of instructions fetch has processed -system.cpu.fetch.MiscStallCycles 3119 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.SquashCycles 881894 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.114613 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 8856375 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 7638723 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 0.580470 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 91019430 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.797733 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.106251 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_accesses 911643 # DTB read accesses +system.cpu.dtb.read_acv 587 # DTB read access violations +system.cpu.dtb.read_hits 10010922 # DTB read hits +system.cpu.dtb.read_misses 38585 # DTB read misses +system.cpu.dtb.write_accesses 324936 # DTB write accesses +system.cpu.dtb.write_acv 234 # DTB write access violations +system.cpu.dtb.write_hits 6587562 # DTB write hits +system.cpu.dtb.write_misses 8266 # DTB write misses +system.cpu.fetch.Branches 14341052 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 8858763 # Number of cache lines fetched +system.cpu.fetch.Cycles 23012166 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 454758 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 72677531 # Number of instructions fetch has processed +system.cpu.fetch.MiscStallCycles 2805 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.SquashCycles 885401 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.114686 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 8858763 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 7636535 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 0.581205 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 90743314 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.800913 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.110485 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 76908614 84.50% 84.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1045900 1.15% 85.65% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1970690 2.17% 87.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 922798 1.01% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2985749 3.28% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 648659 0.71% 92.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 777022 0.85% 93.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1074890 1.18% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 4685108 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 76629913 84.45% 84.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1043583 1.15% 85.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1968273 2.17% 87.77% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 922995 1.02% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2983072 3.29% 92.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 649341 0.72% 92.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 774162 0.85% 93.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1071348 1.18% 94.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 4700627 5.18% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 91019430 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses::0 8856375 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 8856375 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency::0 14955.618992 # average ReadReq miss latency +system.cpu.fetch.rateDist::total 90743314 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses::0 8858763 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 8858763 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency::0 14954.289774 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.509769 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits::0 7815975 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 7815975 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 15559825999 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate::0 0.117475 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses::0 1040400 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1040400 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 47600 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 11852552499 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112100 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11938.526205 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits::0 7818580 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7818580 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 15555198000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate::0 0.117419 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses::0 1040183 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1040183 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 47630 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 11849620000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::0 0.112042 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 992800 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs 12245.264151 # average number of cycles each access was blocked +system.cpu.icache.ReadReq_mshr_misses 992553 # number of ReadReq MSHR misses +system.cpu.icache.avg_blocked_cycles::no_mshrs 12638.888889 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 7.874156 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 53 # number of cycles access was blocked +system.cpu.icache.avg_refs 7.878725 # Average number of references to valid blocks. +system.cpu.icache.blocked::no_mshrs 54 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 648999 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_mshrs 682500 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses::0 8856375 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::0 8858763 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 8856375 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency::0 14955.618992 # average overall miss latency +system.cpu.icache.demand_accesses::total 8858763 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency::0 14954.289774 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11938.509769 # average overall mshr miss latency -system.cpu.icache.demand_hits::0 7815975 # number of demand (read+write) hits +system.cpu.icache.demand_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency +system.cpu.icache.demand_hits::0 7818580 # number of demand (read+write) hits system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 7815975 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 15559825999 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate::0 0.117475 # miss rate for demand accesses +system.cpu.icache.demand_hits::total 7818580 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 15555198000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate::0 0.117419 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.demand_misses::0 1040400 # number of demand (read+write) misses +system.cpu.icache.demand_misses::0 1040183 # number of demand (read+write) misses system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1040400 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 47600 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 11852552499 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate::0 0.112100 # mshr miss rate for demand accesses +system.cpu.icache.demand_misses::total 1040183 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 47630 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 11849620000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate::0 0.112042 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 992800 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 992553 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.995724 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 509.810488 # Average occupied blocks per context -system.cpu.icache.overall_accesses::0 8856375 # number of overall (read+write) accesses +system.cpu.icache.occ_%::0 0.995726 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 509.811580 # Average occupied blocks per context +system.cpu.icache.overall_accesses::0 8858763 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 8856375 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency::0 14955.618992 # average overall miss latency +system.cpu.icache.overall_accesses::total 8858763 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency::0 14954.289774 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11938.509769 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11938.526205 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits::0 7815975 # number of overall hits +system.cpu.icache.overall_hits::0 7818580 # number of overall hits system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 7815975 # number of overall hits -system.cpu.icache.overall_miss_latency 15559825999 # number of overall miss cycles -system.cpu.icache.overall_miss_rate::0 0.117475 # miss rate for overall accesses +system.cpu.icache.overall_hits::total 7818580 # number of overall hits +system.cpu.icache.overall_miss_latency 15555198000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate::0 0.117419 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.overall_misses::0 1040400 # number of overall misses +system.cpu.icache.overall_misses::0 1040183 # number of overall misses system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1040400 # number of overall misses -system.cpu.icache.overall_mshr_hits 47600 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 11852552499 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate::0 0.112100 # mshr miss rate for overall accesses +system.cpu.icache.overall_misses::total 1040183 # number of overall misses +system.cpu.icache.overall_mshr_hits 47630 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 11849620000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate::0 0.112042 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 992800 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 992553 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 992100 # number of replacements -system.cpu.icache.sampled_refs 992611 # Sample count of references to valid blocks. +system.cpu.icache.replacements 991855 # number of replacements +system.cpu.icache.sampled_refs 992366 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 509.810488 # Cycle average of tags in use -system.cpu.icache.total_refs 7815974 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 24432976000 # Cycle when the warmup percentage was hit. +system.cpu.icache.tagsinuse 509.811580 # Cycle average of tags in use +system.cpu.icache.total_refs 7818579 # Total number of references to valid blocks. +system.cpu.icache.warmup_cycle 24432989000 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 92 # number of writebacks -system.cpu.idleCycles 34067458 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 9122615 # Number of branches executed -system.cpu.iew.EXEC:nop 3587548 # number of nop insts executed -system.cpu.iew.EXEC:rate 0.456821 # Inst execution rate -system.cpu.iew.EXEC:refs 16872636 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 6608998 # Number of stores executed +system.cpu.idleCycles 34303057 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 9120771 # Number of branches executed +system.cpu.iew.EXEC:nop 3587259 # number of nop insts executed +system.cpu.iew.EXEC:rate 0.457031 # Inst execution rate +system.cpu.iew.EXEC:refs 16688341 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 6610740 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 35235161 # num instructions consuming a value -system.cpu.iew.WB:count 56707736 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.757346 # average fanout of values written-back +system.cpu.iew.WB:consumers 35263770 # num instructions consuming a value +system.cpu.iew.WB:count 56701745 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.757231 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 26685206 # num instructions producing a value -system.cpu.iew.WB:rate 0.453347 # insts written-back per cycle -system.cpu.iew.WB:sent 56809510 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 839127 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 9343071 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 10818405 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 1790311 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 888014 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 6925516 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 65053041 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 10263638 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 522865 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 57142298 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 63050 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 26702819 # num instructions producing a value +system.cpu.iew.WB:rate 0.453446 # insts written-back per cycle +system.cpu.iew.WB:sent 56803907 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 838873 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 9248148 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 10633496 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 1790322 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 888125 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 6942976 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 65083615 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 10077601 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 523401 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 57150006 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 61281 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 11753 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1512175 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 559162 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 11748 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1517170 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 557912 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 127334 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 439799 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 8819 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 131935 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 439695 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 9709 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 42451 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 17646 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 1515194 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 536005 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 42451 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 406021 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 433106 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 0.424145 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.424145 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 42652 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 17619 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 1525981 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 553705 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 42652 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 406121 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 432752 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 0.424262 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.424262 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7281 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 39339623 68.22% 68.23% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 62341 0.11% 68.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.34% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.39% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 10615152 18.41% 86.80% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 6658629 11.55% 98.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IprAccess 952896 1.65% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 39530216 68.54% 68.55% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 62377 0.11% 68.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 68.66% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 25607 0.04% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 3636 0.01% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 68.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 10431492 18.09% 86.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 6659819 11.55% 98.35% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IprAccess 952981 1.65% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 57665165 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 433439 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.007516 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 57673409 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 436908 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.007576 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 48806 11.26% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.26% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 267453 61.70% 72.97% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 117180 27.03% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 51858 11.87% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.87% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 268470 61.45% 73.32% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 116580 26.68% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 91019430 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 0.633548 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.199187 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 90743314 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 0.635566 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.200958 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 62621832 68.80% 68.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 14091892 15.48% 84.28% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 6228717 6.84% 91.13% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 3803889 4.18% 95.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 2535360 2.79% 98.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 1092488 1.20% 99.29% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 467011 0.51% 99.80% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 127702 0.14% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 50539 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 62371115 68.73% 68.73% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 14052012 15.49% 84.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 6227116 6.86% 91.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 3817489 4.21% 95.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 2534919 2.79% 98.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 1095821 1.21% 99.29% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 467371 0.52% 99.80% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 128077 0.14% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 49394 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 91019430 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 0.461001 # Inst issue rate -system.cpu.iq.iqInstsAdded 59425779 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 57665165 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 2039714 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 8033204 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 30047 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 1372081 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 4119513 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 90743314 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 0.461216 # Inst issue rate +system.cpu.iq.iqInstsAdded 59456475 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 57673409 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 2039881 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 8066144 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 29810 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 1372257 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 4171431 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 1291442 # ITB accesses -system.cpu.itb.fetch_acv 931 # ITB acv -system.cpu.itb.fetch_hits 1252390 # ITB hits -system.cpu.itb.fetch_misses 39052 # ITB misses +system.cpu.itb.fetch_accesses 1294967 # ITB accesses +system.cpu.itb.fetch_acv 915 # ITB acv +system.cpu.itb.fetch_hits 1255877 # ITB hits +system.cpu.itb.fetch_misses 39090 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -457,51 +457,51 @@ system.cpu.kern.callpal::swpctx 4176 2.17% 2.17% # number of callpals executed system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175588 91.19% 93.39% # number of callpals executed -system.cpu.kern.callpal::rdps 6792 3.53% 96.92% # number of callpals executed +system.cpu.kern.callpal::swpipl 175602 91.19% 93.39% # number of callpals executed +system.cpu.kern.callpal::rdps 6793 3.53% 96.92% # number of callpals executed system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed -system.cpu.kern.callpal::rti 5222 2.71% 99.64% # number of callpals executed +system.cpu.kern.callpal::rti 5223 2.71% 99.64% # number of callpals executed system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192558 # number of callpals executed +system.cpu.kern.callpal::total 192574 # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 211717 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6422 # number of quiesce instructions executed -system.cpu.kern.ipl_count::0 74912 40.95% 40.95% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 242 0.13% 41.08% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1889 1.03% 42.11% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 105896 57.89% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 182939 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73545 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 242 0.16% 49.45% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1889 1.27% 50.71% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73548 49.29% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149224 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1826190656000 97.88% 97.88% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 98153500 0.01% 97.89% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 391767500 0.02% 97.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 39038852000 2.09% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1865719429000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981752 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.inst.hwrei 211736 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6428 # number of quiesce instructions executed +system.cpu.kern.ipl_count::0 74918 40.95% 40.95% # number of times we switched to this ipl +system.cpu.kern.ipl_count::21 241 0.13% 41.08% # number of times we switched to this ipl +system.cpu.kern.ipl_count::22 1890 1.03% 42.11% # number of times we switched to this ipl +system.cpu.kern.ipl_count::31 105906 57.89% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_count::total 182955 # number of times we switched to this ipl +system.cpu.kern.ipl_good::0 73551 49.29% 49.29% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::21 241 0.16% 49.45% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::22 1890 1.27% 50.71% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::31 73553 49.29% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good::total 149235 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks::0 1827169522000 97.88% 97.88% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::21 98068500 0.01% 97.89% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 392034000 0.02% 97.91% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 39041528500 2.09% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1866701153000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_used::0 0.981753 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.694530 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_used::31 0.694512 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.mode_good::kernel 1909 system.cpu.kern.mode_good::user 1739 system.cpu.kern.mode_good::idle 170 -system.cpu.kern.mode_switch::kernel 5960 # number of protection mode switches +system.cpu.kern.mode_switch::kernel 5963 # number of protection mode switches system.cpu.kern.mode_switch::user 1739 # number of protection mode switches -system.cpu.kern.mode_switch::idle 2106 # number of protection mode switches -system.cpu.kern.mode_switch_good::kernel 0.320302 # fraction of useful protection mode switches +system.cpu.kern.mode_switch::idle 2108 # number of protection mode switches +system.cpu.kern.mode_switch_good::kernel 0.320141 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle 0.080722 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total 1.401024 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 30084580500 1.61% 1.61% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3003065000 0.16% 1.77% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1832631775500 98.23% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_switch_good::idle 0.080645 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good::total 1.400786 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks::kernel 30087907500 1.61% 1.61% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 2984190000 0.16% 1.77% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1833629047500 98.23% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4177 # number of times the context was actually changed system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed @@ -534,29 +534,29 @@ system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.memDep0.conflictingLoads 2912046 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2554541 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 10818405 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 6925516 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 125086888 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 13518840 # Number of cycles rename is blocking -system.cpu.rename.RENAME:CommittedMaps 38230175 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1063400 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 39070962 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1708241 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 58560 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 82154290 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 67531938 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 45272379 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 12498732 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1512175 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 4709748 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 7042202 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 19708971 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 1694119 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 11797121 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 247227 # count of temporary serializing insts renamed -system.cpu.timesIdled 1311679 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.memDep0.conflictingLoads 3017684 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2588344 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 10633496 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 6942976 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 125046371 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 13291099 # Number of cycles rename is blocking +system.cpu.rename.RENAME:CommittedMaps 38228333 # Number of HB maps that are committed +system.cpu.rename.RENAME:IQFullEvents 1062884 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 39061405 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1660710 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 58609 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 82224860 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 67584077 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 45304633 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 12511976 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1517170 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 4651674 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 7076298 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 19709988 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 1694270 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 11738773 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 247232 # count of temporary serializing insts renamed +system.cpu.timesIdled 1310674 # Number of times that the entire CPU went into an idle state and unscheduled itself system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). @@ -572,14 +572,14 @@ system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115248.543353 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::1 115254.323699 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353 # average ReadReq mshr miss latency -system.iocache.ReadReq_miss_latency 19937998 # number of ReadReq miss cycles +system.iocache.ReadReq_avg_mshr_miss_latency 63254.323699 # average ReadReq mshr miss latency +system.iocache.ReadReq_miss_latency 19938998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses system.iocache.ReadReq_misses::1 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.ReadReq_mshr_miss_latency 10941998 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency 10942998 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses @@ -587,37 +587,37 @@ system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137713.414661 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::1 137728.913313 # average WriteReq miss latency system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85709.809347 # average WriteReq mshr miss latency -system.iocache.WriteReq_miss_latency 5722267806 # number of WriteReq miss cycles +system.iocache.WriteReq_avg_mshr_miss_latency 85725.355699 # average WriteReq mshr miss latency +system.iocache.WriteReq_miss_latency 5722911806 # number of WriteReq miss cycles system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.WriteReq_mshr_miss_latency 3561413998 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency 3562059980 # number of WriteReq MSHR miss cycles system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.avg_blocked_cycles::no_mshrs 6169.345934 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6166.098893 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.blocked_cycles::no_mshrs 64630068 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 64596052 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.cache_copies 0 # number of cache copies performed system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137620.270917 # average overall miss latency +system.iocache.demand_avg_miss_latency::1 137635.729275 # average overall miss latency system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.demand_avg_mshr_miss_latency 85616.680551 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency system.iocache.demand_hits::0 0 # number of demand (read+write) hits system.iocache.demand_hits::1 0 # number of demand (read+write) hits system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.demand_miss_latency 5742205804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency 5742850804 # number of demand (read+write) miss cycles system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses @@ -625,7 +625,7 @@ system.iocache.demand_misses::1 41725 # number of demand (read+write) misses system.iocache.demand_misses::total 41725 # number of demand (read+write) misses system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.demand_mshr_miss_latency 3572355996 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency 3573002978 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses @@ -633,20 +633,20 @@ system.iocache.fast_writes 0 # number of fast writes performed system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.occ_%::1 0.081045 # Average percentage of cache occupancy -system.iocache.occ_blocks::1 1.296712 # Average occupied blocks per context +system.iocache.occ_%::1 0.081527 # Average percentage of cache occupancy +system.iocache.occ_blocks::1 1.304436 # Average occupied blocks per context system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137620.270917 # average overall miss latency +system.iocache.overall_avg_miss_latency::1 137635.729275 # average overall miss latency system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_mshr_miss_latency 85616.680551 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency 85632.186411 # average overall mshr miss latency system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.iocache.overall_hits::0 0 # number of overall hits system.iocache.overall_hits::1 0 # number of overall hits system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.overall_miss_latency 5742205804 # number of overall miss cycles +system.iocache.overall_miss_latency 5742850804 # number of overall miss cycles system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses @@ -654,7 +654,7 @@ system.iocache.overall_misses::1 41725 # number of overall misses system.iocache.overall_misses::total 41725 # number of overall misses system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.overall_mshr_miss_latency 3572355996 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency 3573002978 # number of overall MSHR miss cycles system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses @@ -664,144 +664,145 @@ system.iocache.replacements 41685 # number of replacements system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.tagsinuse 1.296712 # Cycle average of tags in use +system.iocache.tagsinuse 1.304436 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.warmup_cycle 1711281276000 # Cycle when the warmup percentage was hit. +system.iocache.warmup_cycle 1711281439000 # Cycle when the warmup percentage was hit. system.iocache.writebacks 41512 # number of writebacks -system.l2c.ReadExReq_accesses::0 300943 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 300943 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 52461.384650 # average ReadExReq miss latency +system.l2c.ReadExReq_accesses::0 300869 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 300869 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 52487.240298 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40312.785193 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_hits::0 183917 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 183917 # number of ReadExReq hits -system.l2c.ReadExReq_miss_latency 6139346000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 0.388864 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 117026 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 117026 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 4717644000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 0.388864 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_avg_mshr_miss_latency 40337.781709 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_hits::0 183860 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 183860 # number of ReadExReq hits +system.l2c.ReadExReq_miss_latency 6141479500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_rate::0 0.388903 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_misses::0 117009 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 117009 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_miss_latency 4719883500 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 0.388903 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 117026 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 2092753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2092753 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 52046.663805 # average ReadReq miss latency +system.l2c.ReadExReq_mshr_misses 117009 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 2092408 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2092408 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 52046.041420 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40015.758954 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40014.986194 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 1785277 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1785277 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 16003100000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.146924 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 307476 # number of ReadReq misses -system.l2c.ReadReq_misses::total 307476 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 12303885500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.146924 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_hits::0 1784924 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1784924 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 16003325000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.146952 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 307484 # number of ReadReq misses +system.l2c.ReadReq_misses::total 307484 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 12303928000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 0.146952 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 307476 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 811482500 # number of ReadReq MSHR uncacheable cycles -system.l2c.SCUpgradeReq_accesses::0 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_hits::0 4 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 4 # number of SCUpgradeReq hits -system.l2c.UpgradeReq_accesses::0 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 27 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 20722.222222 # average UpgradeReq miss latency +system.l2c.ReadReq_mshr_misses 307483 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 811377500 # number of ReadReq MSHR uncacheable cycles +system.l2c.SCUpgradeReq_accesses::0 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 3 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_hits::0 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.UpgradeReq_accesses::0 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 25 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 21400 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 43333.333333 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_hits::0 9 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 9 # number of UpgradeReq hits -system.l2c.UpgradeReq_miss_latency 373000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_rate::0 0.666667 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_miss_latency 780000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 0.666667 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency 44000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_hits::0 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 10 # number of UpgradeReq hits +system.l2c.UpgradeReq_miss_latency 321000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_rate::0 0.600000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_misses::0 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 15 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_miss_latency 660000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 0.600000 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses 15 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1115672498 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 832936 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 832936 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 832936 # number of Writeback hits -system.l2c.Writeback_hits::total 832936 # number of Writeback hits +system.l2c.WriteReq_mshr_uncacheable_latency 1116250998 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 832842 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 832842 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 832842 # number of Writeback hits +system.l2c.Writeback_hits::total 832842 # number of Writeback hits system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 5.637084 # Average number of references to valid blocks. +system.l2c.avg_refs 5.630753 # Average number of references to valid blocks. system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 2393696 # number of demand (read+write) accesses +system.l2c.demand_accesses::0 2393277 # number of demand (read+write) accesses system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2393696 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 52160.993352 # average overall miss latency +system.l2c.demand_accesses::total 2393277 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 52167.655297 # average overall miss latency system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40097.642650 # average overall mshr miss latency -system.l2c.demand_hits::0 1969194 # number of demand (read+write) hits +system.l2c.demand_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency +system.l2c.demand_hits::0 1968784 # number of demand (read+write) hits system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1969194 # number of demand (read+write) hits -system.l2c.demand_miss_latency 22142446000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.177342 # miss rate for demand accesses +system.l2c.demand_hits::total 1968784 # number of demand (read+write) hits +system.l2c.demand_miss_latency 22144804500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.177369 # miss rate for demand accesses system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.demand_misses::0 424502 # number of demand (read+write) misses +system.l2c.demand_misses::0 424493 # number of demand (read+write) misses system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 424502 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 17021529500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0.177342 # mshr miss rate for demand accesses +system.l2c.demand_misses::total 424493 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 17023811500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 0.177369 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 424502 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses 424492 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.187192 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.344481 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 12267.817300 # Average occupied blocks per context -system.l2c.occ_blocks::1 22575.879516 # Average occupied blocks per context -system.l2c.overall_accesses::0 2393696 # number of overall (read+write) accesses +system.l2c.occ_%::0 0.186929 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.344699 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 12250.608437 # Average occupied blocks per context +system.l2c.occ_blocks::1 22590.202953 # Average occupied blocks per context +system.l2c.overall_accesses::0 2393277 # number of overall (read+write) accesses system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2393696 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 52160.993352 # average overall miss latency +system.l2c.overall_accesses::total 2393277 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 52167.655297 # average overall miss latency system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40097.642650 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency 40103.963090 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 1969194 # number of overall hits +system.l2c.overall_hits::0 1968784 # number of overall hits system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1969194 # number of overall hits -system.l2c.overall_miss_latency 22142446000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.177342 # miss rate for overall accesses +system.l2c.overall_hits::total 1968784 # number of overall hits +system.l2c.overall_miss_latency 22144804500 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.177369 # miss rate for overall accesses system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.overall_misses::0 424502 # number of overall misses +system.l2c.overall_misses::0 424493 # number of overall misses system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 424502 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 17021529500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0.177342 # mshr miss rate for overall accesses +system.l2c.overall_misses::total 424493 # number of overall misses +system.l2c.overall_mshr_hits 1 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 17023811500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 0.177369 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 424502 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 1927154998 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_misses 424492 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 1927628498 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 391012 # number of replacements -system.l2c.sampled_refs 423751 # Sample count of references to valid blocks. +system.l2c.replacements 390990 # number of replacements +system.l2c.sampled_refs 423735 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 34843.696815 # Cycle average of tags in use -system.l2c.total_refs 2388720 # Total number of references to valid blocks. +system.l2c.tagsinuse 34840.811390 # Cycle average of tags in use +system.l2c.total_refs 2385947 # Total number of references to valid blocks. system.l2c.warmup_cycle 5637119000 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 117653 # number of writebacks +system.l2c.writebacks 117624 # number of writebacks system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/o3-timing/simout --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,15 +7,15 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:04:52 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:32:27 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.133333 -Exiting @ tick 134780256500 because target called exit() +Exiting @ tick 136326909500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,112 +1,112 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 209084 # Simulator instruction rate (inst/s) -host_mem_usage 200220 # Number of bytes of host memory used -host_seconds 1796.28 # Real time elapsed on the host -host_tick_rate 75032789 # Simulator tick rate (ticks/s) +host_inst_rate 228388 # Simulator instruction rate (inst/s) +host_mem_usage 246968 # Number of bytes of host memory used +host_seconds 1644.46 # Real time elapsed on the host +host_tick_rate 82900633 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 375574819 # Number of instructions simulated -sim_seconds 0.134780 # Number of seconds simulated -sim_ticks 134780256500 # Number of ticks simulated +sim_seconds 0.136327 # Number of seconds simulated +sim_ticks 136326909500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 34013245 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 43763729 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1420 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 5537198 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 35178330 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 62077463 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 12488414 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 35459307 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 43810174 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1426 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 5614078 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 35351284 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 62456368 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 12662154 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 44587532 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 13095097 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 12699878 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 254238271 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.568075 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.238705 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 256761438 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.552665 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.229770 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 122261214 48.09% 48.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 50419868 19.83% 67.92% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 19851999 7.81% 75.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 19999442 7.87% 83.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 10886968 4.28% 87.88% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 9291241 3.65% 91.53% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 5249545 2.06% 93.60% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 3182897 1.25% 94.85% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 13095097 5.15% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 124458766 48.47% 48.47% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 50855968 19.81% 68.28% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 19650568 7.65% 75.93% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 20252396 7.89% 83.82% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 10775172 4.20% 88.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 8940653 3.48% 91.50% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 5548934 2.16% 93.66% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 3579103 1.39% 95.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 12699878 4.95% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 254238271 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 256761438 # Number of insts commited each cycle system.cpu.commit.COM:count 398664594 # Number of instructions committed -system.cpu.commit.COM:loads 100651995 # Number of loads committed +system.cpu.commit.COM:loads 94754489 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 174183397 # Number of memory references committed +system.cpu.commit.COM:refs 168275218 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 5532855 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 5609735 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 398664594 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 94873241 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 98058240 # The number of squashed insts skipped by commit system.cpu.committedInsts 375574819 # Number of Instructions Simulated system.cpu.committedInsts_total 375574819 # Number of Instructions Simulated -system.cpu.cpi 0.717728 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.717728 # CPI: Total CPI of All Threads +system.cpu.cpi 0.725964 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.725964 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 3 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 95565604 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 33374.015748 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31987.257900 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 95563953 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 55100500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_accesses 96258234 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 33424.104432 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31993.883792 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 96256587 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 55049500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000017 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1651 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 670 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 31379500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 1647 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 666 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 31386000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 981 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 73520729 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 30116.133558 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35471.048513 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 73502909 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 536669500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 30170.708432 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35486.697966 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 73502915 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 537461000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.000242 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 17820 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 14625 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 113330000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 17814 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 14619 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 113380000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000043 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 3195 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 40485.360393 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 40651.222462 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 169086333 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30392.378409 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency -system.cpu.dcache.demand_hits 169066862 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 591770000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 169778963 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 30446.045938 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency +system.cpu.dcache.demand_hits 169759502 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 592510500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000115 # miss rate for demand accesses -system.cpu.dcache.demand_misses 19471 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 15295 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 144709500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 19461 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 15285 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 144766000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 4176 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.804225 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 3294.106020 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 169086333 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30392.378409 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34652.658046 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.804250 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 3294.209288 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 169778963 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 30446.045938 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34666.187739 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 169066862 # number of overall hits -system.cpu.dcache.overall_miss_latency 591770000 # number of overall miss cycles +system.cpu.dcache.overall_hits 169759502 # number of overall hits +system.cpu.dcache.overall_miss_latency 592510500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000115 # miss rate for overall accesses -system.cpu.dcache.overall_misses 19471 # number of overall misses -system.cpu.dcache.overall_mshr_hits 15295 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 144709500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 19461 # number of overall misses +system.cpu.dcache.overall_mshr_hits 15285 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 144766000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 4176 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -114,227 +114,227 @@ system.cpu.dcache.replacements 781 # number of replacements system.cpu.dcache.sampled_refs 4176 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 3294.106020 # Cycle average of tags in use -system.cpu.dcache.total_refs 169066865 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 3294.209288 # Cycle average of tags in use +system.cpu.dcache.total_refs 169759505 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 662 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 22152007 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 4419 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 11286796 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 532040738 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 132274950 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 98625859 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 15181213 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 13245 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 1185455 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 184734537 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 184683089 # DTB hits -system.cpu.dtb.data_misses 51448 # DTB misses +system.cpu.decode.DECODE:BlockedCycles 21274693 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 4421 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 11335478 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 536362282 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 133648516 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 100614513 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 15751437 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 13226 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 1223716 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 185361756 # DTB accesses +system.cpu.dtb.data_acv 1 # DTB access violations +system.cpu.dtb.data_hits 185333824 # DTB hits +system.cpu.dtb.data_misses 27932 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 104442295 # DTB read accesses +system.cpu.dtb.read_accesses 105061264 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 104392308 # DTB read hits -system.cpu.dtb.read_misses 49987 # DTB read misses -system.cpu.dtb.write_accesses 80292242 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 80290781 # DTB write hits -system.cpu.dtb.write_misses 1461 # DTB write misses -system.cpu.fetch.Branches 62077463 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 63755206 # Number of cache lines fetched -system.cpu.fetch.Cycles 165857748 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 1527822 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 544006695 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 5884776 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.230291 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 63755206 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 46501659 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.018125 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 269419484 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.019181 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.021968 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_hits 105034802 # DTB read hits +system.cpu.dtb.read_misses 26462 # DTB read misses +system.cpu.dtb.write_accesses 80300492 # DTB write accesses +system.cpu.dtb.write_acv 1 # DTB write access violations +system.cpu.dtb.write_hits 80299022 # DTB write hits +system.cpu.dtb.write_misses 1470 # DTB write misses +system.cpu.fetch.Branches 62456368 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 64427463 # Number of cache lines fetched +system.cpu.fetch.Cycles 168595579 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 1484985 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 548969588 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 6021463 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.229068 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 64427463 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 48121461 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.013431 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 272512875 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.014472 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.018403 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 167317249 62.10% 62.10% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 9830332 3.65% 65.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 10264297 3.81% 69.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 7467850 2.77% 72.33% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 14528793 5.39% 77.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 9632139 3.58% 81.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 7095921 2.63% 83.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 3870398 1.44% 85.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 39412505 14.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 168345063 61.78% 61.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 11153110 4.09% 65.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 11633749 4.27% 70.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 6179991 2.27% 72.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 14406846 5.29% 77.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 9876694 3.62% 81.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 7175383 2.63% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 3990457 1.46% 85.41% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 39751582 14.59% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 269419484 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 63755206 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 32282.788581 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 30880.348450 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 63750372 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 156055000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000076 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 4834 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 931 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120526000 # number of ReadReq MSHR miss cycles +system.cpu.fetch.rateDist::total 272512875 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 64427463 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 32238.031366 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 30836.486832 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 64422617 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 156225500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000075 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 4846 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 935 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120601500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000061 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 3903 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 3911 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 16333.684858 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 16472.159806 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 63755206 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 32282.788581 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency -system.cpu.icache.demand_hits 63750372 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 156055000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000076 # miss rate for demand accesses -system.cpu.icache.demand_misses 4834 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 931 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120526000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_accesses 64427463 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 32238.031366 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency +system.cpu.icache.demand_hits 64422617 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 156225500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000075 # miss rate for demand accesses +system.cpu.icache.demand_misses 4846 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 935 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120601500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000061 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 3903 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 3911 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.891530 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1825.852920 # Average occupied blocks per context -system.cpu.icache.overall_accesses 63755206 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 32282.788581 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 30880.348450 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.891874 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1826.557172 # Average occupied blocks per context +system.cpu.icache.overall_accesses 64427463 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 32238.031366 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 30836.486832 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 63750372 # number of overall hits -system.cpu.icache.overall_miss_latency 156055000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000076 # miss rate for overall accesses -system.cpu.icache.overall_misses 4834 # number of overall misses -system.cpu.icache.overall_mshr_hits 931 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120526000 # number of overall MSHR miss cycles +system.cpu.icache.overall_hits 64422617 # number of overall hits +system.cpu.icache.overall_miss_latency 156225500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000075 # miss rate for overall accesses +system.cpu.icache.overall_misses 4846 # number of overall misses +system.cpu.icache.overall_mshr_hits 935 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120601500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000061 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 3903 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 3911 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 1981 # number of replacements -system.cpu.icache.sampled_refs 3903 # Sample count of references to valid blocks. +system.cpu.icache.replacements 1989 # number of replacements +system.cpu.icache.sampled_refs 3911 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1825.852920 # Cycle average of tags in use -system.cpu.icache.total_refs 63750372 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1826.557172 # Cycle average of tags in use +system.cpu.icache.total_refs 64422617 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 141032 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 50928648 # Number of branches executed -system.cpu.iew.EXEC:nop 27198310 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.554098 # Inst execution rate -system.cpu.iew.EXEC:refs 191466035 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 80302922 # Number of stores executed +system.cpu.idleCycles 140947 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 51277692 # Number of branches executed +system.cpu.iew.EXEC:nop 27475837 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.546858 # Inst execution rate +system.cpu.iew.EXEC:refs 185361805 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 80300524 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 288648946 # num instructions consuming a value -system.cpu.iew.WB:count 415155943 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.699341 # average fanout of values written-back +system.cpu.iew.WB:consumers 290508552 # num instructions consuming a value +system.cpu.iew.WB:count 417530576 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.697486 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 201863998 # num instructions producing a value -system.cpu.iew.WB:rate 1.540121 # insts written-back per cycle -system.cpu.iew.WB:sent 415846665 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 6072161 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3214599 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 125039862 # Number of dispatched load instructions +system.cpu.iew.WB:producers 202625525 # num instructions producing a value +system.cpu.iew.WB:rate 1.531358 # insts written-back per cycle +system.cpu.iew.WB:sent 418298724 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 6117740 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3299737 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 117580442 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 241 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 6489838 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 92505583 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 493538259 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 111163113 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 8697897 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 418923368 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 138014 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 6436127 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 92914841 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 496723261 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 105061281 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 8627247 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 421756759 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 169659 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 28455 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 15181213 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 561595 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 28133 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 15751437 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 607162 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 8650010 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 47350 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 8600585 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 30861 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 540044 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 176691 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 24387867 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 18974181 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 540044 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 1086448 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 4985713 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.393286 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.393286 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 663165 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 175980 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 22825953 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 19394112 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 663165 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 1101512 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 5016228 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.377479 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.377479 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 33581 0.01% 0.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 166094034 38.84% 38.85% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 2150895 0.50% 39.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 39.35% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34767843 8.13% 47.48% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7837636 1.83% 49.32% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2956341 0.69% 50.01% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 16811834 3.93% 53.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1571362 0.37% 54.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 54.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 113187864 26.47% 80.78% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 82209875 19.22% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 175581687 40.80% 40.80% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 2149994 0.50% 41.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 41.30% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 34727338 8.07% 49.37% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 7823215 1.82% 51.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2961066 0.69% 51.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 16836878 3.91% 55.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 1569908 0.36% 56.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 106389727 24.72% 80.88% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 82310612 19.12% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 427621265 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 9425623 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.022042 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 430384006 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 8629906 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.020052 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 22465 0.24% 0.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 44257 0.47% 0.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 507 0.01% 0.71% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 7079 0.08% 0.79% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 1310742 13.91% 14.69% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 1081807 11.48% 26.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.17% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 5661778 60.07% 86.24% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1296988 13.76% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 24317 0.28% 0.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.28% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 44159 0.51% 0.79% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 3134 0.04% 0.83% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 6690 0.08% 0.91% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 1184776 13.73% 14.64% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 981942 11.38% 26.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 26.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 5222594 60.52% 86.53% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1162294 13.47% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 269419484 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.587195 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.714658 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 272512875 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.579316 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.717067 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 98807587 36.67% 36.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 58261038 21.62% 58.30% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 40917124 15.19% 73.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 29020181 10.77% 84.26% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 23205890 8.61% 92.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 11236315 4.17% 97.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 5001720 1.86% 98.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 2307051 0.86% 99.75% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 662578 0.25% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 101003308 37.06% 37.06% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 58496079 21.47% 58.53% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 41698303 15.30% 73.83% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 27977806 10.27% 84.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 23760656 8.72% 92.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 11524865 4.23% 97.05% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 5162499 1.89% 98.94% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 2198912 0.81% 99.75% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 690447 0.25% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 269419484 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.586365 # Inst issue rate -system.cpu.iq.iqInstsAdded 466339708 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 427621265 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 272512875 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.578500 # Inst issue rate +system.cpu.iq.iqInstsAdded 469247183 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 430384006 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 241 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 89739850 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 704910 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 92662056 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 866219 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 26 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 69710487 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 70475093 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 63755513 # ITB accesses +system.cpu.itb.fetch_accesses 64427767 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 63755206 # ITB hits -system.cpu.itb.fetch_misses 307 # ITB misses +system.cpu.itb.fetch_hits 64427463 # ITB hits +system.cpu.itb.fetch_misses 304 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -344,97 +344,97 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 3199 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34585.272553 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31456.646478 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 34601.370736 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31458.240357 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 62 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 108494000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 108544500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.980619 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 3137 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 98679500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 98684500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.980619 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 3137 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 4880 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34357.396450 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.467456 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 655 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 145160000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.865779 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 4225 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 131691000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.865779 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 4225 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 4888 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34357.345635 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31169.742134 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 661 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 145228500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.864771 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 4227 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 131754500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864771 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 4227 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 662 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 662 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.152443 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.153637 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 8079 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34454.496061 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 717 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 253654000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.911251 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 7362 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 8087 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34461.298207 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 723 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 253773000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.910597 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 7364 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 230370500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.911251 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 7362 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 230439000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.910597 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 7364 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.108627 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.011574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3559.477751 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 379.255991 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 8079 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34454.496061 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31291.836457 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.108677 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.011575 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3561.129355 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 379.284506 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 8087 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34461.298207 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31292.639870 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 717 # number of overall hits -system.cpu.l2cache.overall_miss_latency 253654000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.911251 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 7362 # number of overall misses +system.cpu.l2cache.overall_hits 723 # number of overall hits +system.cpu.l2cache.overall_miss_latency 253773000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.910597 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 7364 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 230370500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.911251 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 7362 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 230439000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.910597 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 7364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 13 # number of replacements -system.cpu.l2cache.sampled_refs 4769 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 4771 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 3938.733742 # Cycle average of tags in use -system.cpu.l2cache.total_refs 727 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 3940.413861 # Cycle average of tags in use +system.cpu.l2cache.total_refs 733 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 72822522 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 52763057 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 125039862 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 92505583 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 269560516 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 11010620 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 71937561 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 54246192 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 117580442 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 92914841 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 272653822 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 10643219 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 259532341 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 2256823 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 137290050 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 7674469 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:IQFullEvents 2331141 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 138476212 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 7076079 # Number of times rename has blocked due to LSQ full system.cpu.rename.RENAME:ROBFullEvents 2 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 683176131 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 518444566 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 335488186 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 94400681 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 15181213 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 11169785 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 75955845 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 367135 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 37569 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 24308277 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 261 # count of temporary serializing insts renamed -system.cpu.timesIdled 3095 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:RenameLookups 688559814 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 522801702 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 337940166 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 96677987 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 15751437 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 10596756 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 78407825 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 367264 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 37559 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 23060243 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 258 # count of temporary serializing insts renamed +system.cpu.timesIdled 3093 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -46,3 +46,6 @@ 12 8 14 13 8 14 14 8 14 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:33:35 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:31:02 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -16,3 +18,4 @@ Eon, Version 1.1 info: Increasing stack size by one page. OO-style eon Time= 0.183333 +Exiting @ tick 199332411500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1825585 # Simulator instruction rate (inst/s) -host_mem_usage 190564 # Number of bytes of host memory used -host_seconds 218.38 # Real time elapsed on the host -host_tick_rate 912792158 # Simulator tick rate (ticks/s) +host_inst_rate 4732897 # Simulator instruction rate (inst/s) +host_mem_usage 238480 # Number of bytes of host memory used +host_seconds 84.23 # Real time elapsed on the host +host_tick_rate 2366444186 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664595 # Number of instructions simulated sim_seconds 0.199332 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 398664824 # number of cpu cycles simulated system.cpu.num_insts 398664595 # Number of instructions executed -system.cpu.num_refs 174183453 # Number of memory references +system.cpu.num_refs 168275274 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook -cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/eon +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/eon gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-timing/simout --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:42:55 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:41:16 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/30.eon/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/30.eon/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1240949 # Simulator instruction rate (inst/s) -host_mem_usage 199424 # Number of bytes of host memory used -host_seconds 321.26 # Real time elapsed on the host -host_tick_rate 1766004728 # Simulator tick rate (ticks/s) +host_inst_rate 2252516 # Simulator instruction rate (inst/s) +host_mem_usage 246196 # Number of bytes of host memory used +host_seconds 176.99 # Real time elapsed on the host +host_tick_rate 3205571054 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 398664609 # Number of instructions simulated sim_seconds 0.567343 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1134686340 # number of cpu cycles simulated system.cpu.num_insts 398664609 # Number of instructions executed -system.cpu.num_refs 174183455 # Number of memory references +system.cpu.num_refs 168275276 # Number of memory references system.cpu.workload.PROG:num_syscalls 215 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:48:50 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:48:16 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -1390,4 +1392,4 @@ 2000: 760651391 1000: 4031656975 0: 2206428413 -Exiting @ tick 702197148500 because target called exit() +Exiting @ tick 699853545500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,295 +1,295 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 211797 # Simulator instruction rate (inst/s) -host_mem_usage 200548 # Number of bytes of host memory used -host_seconds 8607.50 # Real time elapsed on the host -host_tick_rate 81579716 # Simulator tick rate (ticks/s) +host_inst_rate 223208 # Simulator instruction rate (inst/s) +host_mem_usage 247308 # Number of bytes of host memory used +host_seconds 8167.46 # Real time elapsed on the host +host_tick_rate 85688066 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1823043370 # Number of instructions simulated -sim_seconds 0.702197 # Number of seconds simulated -sim_ticks 702197148500 # Number of ticks simulated +sim_seconds 0.699854 # Number of seconds simulated +sim_ticks 699853545500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 239361289 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 292350506 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 817 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 28355767 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 232672074 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 346972918 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 49326443 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 236956975 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 289938750 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 831 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 28355381 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 231810934 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 346110000 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 49326422 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 266706457 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 67076252 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 69159882 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1304193061 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.540407 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.191824 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1301001982 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.544185 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.202693 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 594441372 45.58% 45.58% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 274309752 21.03% 66.61% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 176336103 13.52% 80.13% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 68165188 5.23% 85.36% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 46116026 3.54% 88.90% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 34003883 2.61% 91.50% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 19794848 1.52% 93.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 23949637 1.84% 94.86% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 67076252 5.14% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 594587557 45.70% 45.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 273537466 21.03% 66.73% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 173768132 13.36% 80.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 65535935 5.04% 85.12% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 48802734 3.75% 88.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 34016841 2.61% 91.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 18422173 1.42% 92.90% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 23171262 1.78% 94.68% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 69159882 5.32% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1304193061 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1301001982 # Number of insts commited each cycle system.cpu.commit.COM:count 2008987604 # Number of instructions committed -system.cpu.commit.COM:loads 511595302 # Number of loads committed +system.cpu.commit.COM:loads 511070026 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 722390433 # Number of memory references committed +system.cpu.commit.COM:refs 721864922 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 28343948 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 28343547 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 694286197 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 686655102 # The number of squashed insts skipped by commit system.cpu.committedInsts 1823043370 # Number of Instructions Simulated system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated -system.cpu.cpi 0.770357 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.770357 # CPI: Total CPI of All Threads +system.cpu.cpi 0.767786 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.767786 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 9 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 9 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 463422916 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37046.413098 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34119.469160 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 461494441 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 71443081500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.004161 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 1928475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 469203 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 49789586000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_accesses 463432344 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 37080.555893 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34168.158766 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 461506110 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 71425827500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004156 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 1926234 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 467104 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 49855785500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.003149 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 1459272 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses 1459130 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 37873.224315 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34361.981856 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 210247567 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 20729113991 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 37974.555169 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34786.244627 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 210247535 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 20785790492 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_rate 0.002597 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 547329 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 475679 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 2462036000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_misses 547361 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 475709 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2492504000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000340 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 71650 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 6041.666667 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 71652 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 6045.454545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 14500 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 438.782653 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 12 # number of cycles access was blocked +system.cpu.dcache.avg_refs 438.830385 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 72500 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 66500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 14500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 674217812 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 37229.197259 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency -system.cpu.dcache.demand_hits 671742008 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 92172195491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.003672 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2475804 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 944882 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 52251622000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002271 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 1530922 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 674227240 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 37278.381462 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency +system.cpu.dcache.demand_hits 671753645 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 92211617992 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.003669 # miss rate for demand accesses +system.cpu.dcache.demand_misses 2473595 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 942813 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 52348289500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.002270 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 1530782 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.occ_%::0 0.999781 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4095.103693 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 674217812 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 37229.197259 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34130.819206 # average overall mshr miss latency +system.cpu.dcache.occ_blocks::0 4095.102160 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 674227240 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 37278.381462 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34197.089788 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 671742008 # number of overall hits -system.cpu.dcache.overall_miss_latency 92172195491 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.003672 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2475804 # number of overall misses -system.cpu.dcache.overall_mshr_hits 944882 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 52251622000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002271 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 1530922 # number of overall MSHR misses +system.cpu.dcache.overall_hits 671753645 # number of overall hits +system.cpu.dcache.overall_miss_latency 92211617992 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.003669 # miss rate for overall accesses +system.cpu.dcache.overall_misses 2473595 # number of overall misses +system.cpu.dcache.overall_mshr_hits 942813 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 52348289500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.002270 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 1530782 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 1526826 # number of replacements -system.cpu.dcache.sampled_refs 1530922 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 1526686 # number of replacements +system.cpu.dcache.sampled_refs 1530782 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4095.103693 # Cycle average of tags in use -system.cpu.dcache.total_refs 671742017 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 274011000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 107349 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 30546765 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 11879 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 30415983 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2934070840 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 711662273 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 561899990 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 100055757 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 45705 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 84033 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 772892535 # DTB accesses +system.cpu.dcache.tagsinuse 4095.102160 # Cycle average of tags in use +system.cpu.dcache.total_refs 671753654 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 273600000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 107376 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 31383327 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 11899 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 30414248 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2922892540 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 711748047 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 557786525 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 98570758 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 45781 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 84083 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 772896747 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 772261224 # DTB hits -system.cpu.dtb.data_misses 631311 # DTB misses +system.cpu.dtb.data_hits 772274639 # DTB hits +system.cpu.dtb.data_misses 622108 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 514571381 # DTB read accesses +system.cpu.dtb.read_accesses 514573141 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 513977951 # DTB read hits -system.cpu.dtb.read_misses 593430 # DTB read misses -system.cpu.dtb.write_accesses 258321154 # DTB write accesses +system.cpu.dtb.read_hits 513988912 # DTB read hits +system.cpu.dtb.read_misses 584229 # DTB read misses +system.cpu.dtb.write_accesses 258323606 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 258283273 # DTB write hits -system.cpu.dtb.write_misses 37881 # DTB write misses -system.cpu.fetch.Branches 346972918 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 347200626 # Number of cache lines fetched -system.cpu.fetch.Cycles 925414333 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 4548226 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 3016464690 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28792576 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.247062 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 347200626 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 288687732 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.147876 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1404248818 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.148098 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.027750 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 258285727 # DTB write hits +system.cpu.dtb.write_misses 37879 # DTB write misses +system.cpu.fetch.Branches 346110000 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 346350693 # Number of cache lines fetched +system.cpu.fetch.Cycles 922065710 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 4322310 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 3016744002 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28792194 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.247273 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 346350693 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 286283397 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.155268 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1399572740 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.155475 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.033799 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 826035319 58.82% 58.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 54061013 3.85% 62.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 40121660 2.86% 65.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 63576700 4.53% 70.06% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 121382183 8.64% 78.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 34599008 2.46% 81.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 37926839 2.70% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 7023317 0.50% 84.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 219522779 15.63% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 823857927 58.86% 58.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53203147 3.80% 62.67% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 38576379 2.76% 65.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 62027989 4.43% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 120526716 8.61% 78.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 36144136 2.58% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 38696119 2.76% 83.81% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 7022744 0.50% 84.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 219517583 15.68% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1404248818 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 347200626 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15854.453498 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11638.008587 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 347189949 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 169278000 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1399572740 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 346350693 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15859.786377 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11646.165644 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 346340020 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 169271500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000031 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 10677 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 895 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 113843000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 10673 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 893 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 113899500 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000028 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 9782 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 9780 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 35496.365300 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 35416.711320 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 347200626 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15854.453498 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency -system.cpu.icache.demand_hits 347189949 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 169278000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 346350693 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15859.786377 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency +system.cpu.icache.demand_hits 346340020 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 169271500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000031 # miss rate for demand accesses -system.cpu.icache.demand_misses 10677 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 895 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 113843000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 10673 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 893 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 113899500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000028 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 9782 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 9780 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.787157 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1612.097956 # Average occupied blocks per context -system.cpu.icache.overall_accesses 347200626 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15854.453498 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11638.008587 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.787644 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1613.094407 # Average occupied blocks per context +system.cpu.icache.overall_accesses 346350693 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15859.786377 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11646.165644 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 347189949 # number of overall hits -system.cpu.icache.overall_miss_latency 169278000 # number of overall miss cycles +system.cpu.icache.overall_hits 346340020 # number of overall hits +system.cpu.icache.overall_miss_latency 169271500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000031 # miss rate for overall accesses -system.cpu.icache.overall_misses 10677 # number of overall misses -system.cpu.icache.overall_mshr_hits 895 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 113843000 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 10673 # number of overall misses +system.cpu.icache.overall_mshr_hits 893 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 113899500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000028 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 9782 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 9780 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8111 # number of replacements -system.cpu.icache.sampled_refs 9781 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8107 # number of replacements +system.cpu.icache.sampled_refs 9779 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1612.097956 # Cycle average of tags in use -system.cpu.icache.total_refs 347189949 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1613.094407 # Cycle average of tags in use +system.cpu.icache.total_refs 346340020 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 145480 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 274684945 # Number of branches executed -system.cpu.iew.EXEC:nop 329038670 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.425383 # Inst execution rate -system.cpu.iew.EXEC:refs 773428063 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 258322146 # Number of stores executed +system.cpu.idleCycles 134352 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 273830635 # Number of branches executed +system.cpu.iew.EXEC:nop 328407505 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.428327 # Inst execution rate +system.cpu.iew.EXEC:refs 772897467 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 258324248 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1632528882 # num instructions consuming a value -system.cpu.iew.WB:count 2000778402 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.695828 # average fanout of values written-back +system.cpu.iew.WB:consumers 1628729095 # num instructions consuming a value +system.cpu.iew.WB:count 1998228085 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.696311 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1135959868 # num instructions producing a value -system.cpu.iew.WB:rate 1.424656 # insts written-back per cycle -system.cpu.iew.WB:sent 2001740023 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 30875630 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 3371474 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 655915316 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 69 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 46568 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 302840686 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2713549765 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 515105917 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 84189444 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2001799378 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 130178 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1134102180 # num instructions producing a value +system.cpu.iew.WB:rate 1.427604 # insts written-back per cycle +system.cpu.iew.WB:sent 1999182270 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 30874102 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 3363341 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 651766159 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 67 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 47334 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 302842543 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2705917270 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 514573219 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 84025502 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 1999238951 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 131775 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 1349 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 100055757 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 139189 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 2470 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 98570758 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 141708 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 16 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 50550937 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 225 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 50552549 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 226 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 3543 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 4083 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 144320014 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 92045555 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 3543 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 788016 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 30087614 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.298099 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.298099 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 3569 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 4004 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 140696133 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 92047647 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 3569 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 787992 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 30086110 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.302446 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.302446 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 2752 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1203839026 57.71% 57.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1202273174 57.71% 57.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntMult 18400 0.00% 57.71% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 57.71% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850839 1.34% 59.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254698 0.40% 59.44% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204647 0.35% 59.79% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 27850829 1.34% 59.05% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 8254690 0.40% 59.45% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 7204648 0.35% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatMult 4 0.00% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 59.79% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 59.79% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 555691648 26.64% 86.43% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 283126808 13.57% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 554531536 26.62% 86.41% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 283128420 13.59% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2085988822 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 36673966 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.017581 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2083264453 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 36972943 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.017748 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 5496 0.01% 0.01% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 5487 0.01% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 0.01% # attempts to use FU when none available @@ -298,43 +298,43 @@ system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 0.01% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 0.01% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 27909398 76.10% 76.12% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 8759072 23.88% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 27783755 75.15% 75.16% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 9183701 24.84% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1404248818 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.485484 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.638010 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1399572740 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.488500 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.636855 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 532242124 37.90% 37.90% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 283422756 20.18% 58.09% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 275702525 19.63% 77.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 156569721 11.15% 88.87% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 62891882 4.48% 93.35% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 46986104 3.35% 96.69% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 33054153 2.35% 99.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 10407537 0.74% 99.79% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2972016 0.21% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 529155150 37.81% 37.81% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 284031316 20.29% 58.10% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 272535453 19.47% 77.58% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 155737122 11.13% 88.70% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 63080149 4.51% 93.21% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 50551840 3.61% 96.82% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 32415692 2.32% 99.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 9151227 0.65% 99.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 2914791 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1404248818 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.485330 # Inst issue rate -system.cpu.iq.iqInstsAdded 2384511026 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2085988822 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 69 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 561440182 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 12400568 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 30 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 517571269 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1399572740 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.488357 # Inst issue rate +system.cpu.iq.iqInstsAdded 2377509698 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2083264453 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 67 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 554439445 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 12400290 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 28 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 512014253 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 347200834 # ITB accesses +system.cpu.itb.fetch_accesses 346350897 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 347200626 # ITB hits -system.cpu.itb.fetch_misses 208 # ITB misses +system.cpu.itb.fetch_hits 346350693 # ITB hits +system.cpu.itb.fetch_misses 204 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,98 +343,98 @@ system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 71650 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 35152.205453 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32141.578294 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_accesses 71652 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.301769 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32133.325356 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 4793 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 2350171000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.933105 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 66857 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148889500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933105 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 66857 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 1469054 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34210.498210 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.429333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 55232 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 48367555000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.962403 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1413822 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 43829089000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962403 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1413822 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 107349 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 107349 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 7200 # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_miss_latency 2349178000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.933107 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 66859 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2148402000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933107 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 66859 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 1468910 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34259.233914 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.653566 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 55127 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 48435122500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.962471 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1413783 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 43828197000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.962471 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1413783 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 107376 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 107376 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8625 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.041538 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 0.041462 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 36000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 34500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 1540704 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34253.019054 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 60025 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 50717726000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.961041 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 1480679 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 1540562 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34298.838274 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 59920 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 50784300500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.961105 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 1480642 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 45977978500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.961041 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 1480679 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 45976599000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.961105 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 1480642 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.881669 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.093123 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 28890.531626 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 3051.454384 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 1540704 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34253.019054 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.955556 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.881690 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.093104 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 28891.219129 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 3050.823306 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 1540562 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34298.838274 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.799827 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 60025 # number of overall hits -system.cpu.l2cache.overall_miss_latency 50717726000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.961041 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 1480679 # number of overall misses +system.cpu.l2cache.overall_hits 59920 # number of overall hits +system.cpu.l2cache.overall_miss_latency 50784300500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.961105 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 1480642 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 45977978500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.961041 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 1480679 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 45976599000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.961105 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 1480642 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 1480409 # number of replacements -system.cpu.l2cache.sampled_refs 1513096 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 1480407 # number of replacements +system.cpu.l2cache.sampled_refs 1513094 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 31941.986010 # Cycle average of tags in use -system.cpu.l2cache.total_refs 62851 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 31942.042436 # Cycle average of tags in use +system.cpu.l2cache.total_refs 62736 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 66898 # number of writebacks -system.cpu.memDep0.conflictingLoads 122494554 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 20280761 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 655915316 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 302840686 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1404394298 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 19598244 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 118268475 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 21018090 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 651766159 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 302842543 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1399707092 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 19659094 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1384969070 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 671773 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 725577995 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 10516920 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 17 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3307285723 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2838114179 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 1889955714 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 546658925 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 100055757 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 12336225 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 504986644 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 21672 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 2827 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 26425102 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 76 # count of temporary serializing insts renamed -system.cpu.timesIdled 3680 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 672257 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 725352464 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 10949822 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 13 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3294686946 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2827218564 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 1880762420 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 542782008 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 98570758 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 13186877 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 495793350 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 21539 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 2826 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 26818332 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 73 # count of temporary serializing insts renamed +system.cpu.timesIdled 3665 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -2,3 +2,6 @@ For more information see: http://www.m5sim.org/warn/d946bea6 warn: ignoring syscall sigprocmask(0, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:10:59 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:59:54 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -1390,3 +1392,4 @@ 2000: 760651391 1000: 4031656975 0: 2206428413 +Exiting @ tick 1004710587000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2073139 # Simulator instruction rate (inst/s) -host_mem_usage 190360 # Number of bytes of host memory used -host_seconds 969.06 # Real time elapsed on the host -host_tick_rate 1036792835 # Simulator tick rate (ticks/s) +host_inst_rate 5515431 # Simulator instruction rate (inst/s) +host_mem_usage 238276 # Number of bytes of host memory used +host_seconds 364.25 # Real time elapsed on the host +host_tick_rate 2758309260 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 1.004711 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 2009421175 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722823898 # Number of memory references +system.cpu.num_refs 722298387 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=perlbmk -I. -I lib lgred.makerand.pl -cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/perlbmk +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/perlbmk gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:48:17 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:06:01 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1340007 # Simulator instruction rate (inst/s) -host_mem_usage 199308 # Number of bytes of host memory used -host_seconds 1499.24 # Real time elapsed on the host -host_tick_rate 1876600376 # Simulator tick rate (ticks/s) +host_inst_rate 2134538 # Simulator instruction rate (inst/s) +host_mem_usage 246068 # Number of bytes of host memory used +host_seconds 941.18 # Real time elapsed on the host +host_tick_rate 2989292617 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2008987605 # Number of instructions simulated sim_seconds 2.813468 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5626935684 # number of cpu cycles simulated system.cpu.num_insts 2008987605 # Number of instructions executed -system.cpu.num_refs 722823898 # Number of memory references +system.cpu.num_refs 722298387 # Number of memory references system.cpu.workload.PROG:num_syscalls 39 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -186,12 +186,12 @@ [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetching currently unimplemented -For more information see: http://www.m5sim.org/warn/8028fa22 -warn: Write Hints currently unimplemented -For more information see: http://www.m5sim.org/warn/cfb3293b warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 16:19:32 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:06:02 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 58405 # Simulator instruction rate (inst/s) -host_mem_usage 209896 # Number of bytes of host memory used -host_seconds 1512.56 # Real time elapsed on the host -host_tick_rate 68868083 # Simulator tick rate (ticks/s) +host_inst_rate 67514 # Simulator instruction rate (inst/s) +host_mem_usage 256704 # Number of bytes of host memory used +host_seconds 1308.48 # Real time elapsed on the host +host_tick_rate 79609109 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.104167 # Number of seconds simulated sim_ticks 104166942500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 35224018 # Number of Address Generations +system.cpu.AGEN-Unit.agens 34890015 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 11507768 # Number of BTB lookups @@ -19,7 +19,7 @@ system.cpu.Branch-Predictor.predictedNotTaken 5723290 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 8031187 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1659774 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 53075554 # Number of Instructions Executed. +system.cpu.Execution-Unit.executions 53409557 # Number of Instructions Executed. system.cpu.Execution-Unit.mispredictPct 4.741700 # Percentage of Incorrect Branches Predicts system.cpu.Execution-Unit.mispredicted 652196 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 13102281 # Number of Branches Incorrectly Predicted @@ -34,11 +34,11 @@ system.cpu.activity 85.354290 # Percentage of cycles cpu is active system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed -system.cpu.comInts 30457224 # Number of Integer instructions committed -system.cpu.comLoads 20379399 # Number of Load instructions committed +system.cpu.comInts 30791227 # Number of Integer instructions committed +system.cpu.comLoads 20276638 # Number of Load instructions committed system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed system.cpu.comNops 8748916 # Number of Nop instructions committed -system.cpu.comStores 14844619 # Number of Store instructions committed +system.cpu.comStores 14613377 # Number of Store instructions committed system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches @@ -284,9 +284,9 @@ system.cpu.stage-2.idleCycles 118518100 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. system.cpu.stage-2.utilization 43.111463 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 173102616 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 35231270 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.910965 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 173436619 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 34897267 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 16.750644 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage-4.idleCycles 119993213 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. system.cpu.stage-4.utilization 42.403411 # Percentage of cycles stage was utilized (processing insts). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,12 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:41:46 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:35:53 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 27033689000 because target called exit() +Exiting @ tick 26961586000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 221900 # Simulator instruction rate (inst/s) -host_mem_usage 202972 # Number of bytes of host memory used -host_seconds 358.68 # Real time elapsed on the host -host_tick_rate 75369122 # Simulator tick rate (ticks/s) +host_inst_rate 245514 # Simulator instruction rate (inst/s) +host_mem_usage 249732 # Number of bytes of host memory used +host_seconds 324.18 # Real time elapsed on the host +host_tick_rate 83167459 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 79591756 # Number of instructions simulated -sim_seconds 0.027034 # Number of seconds simulated -sim_ticks 27033689000 # Number of ticks simulated +sim_seconds 0.026962 # Number of seconds simulated +sim_ticks 26961586000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 8073345 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 14152511 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 36189 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 458905 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 10574319 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 16281513 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1942543 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 8073497 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 14157572 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 36043 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 458661 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 10575039 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 16280778 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1941652 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 13754477 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 3315405 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 3390195 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 51596234 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.712153 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.330354 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 51426557 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.717803 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.342707 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 22410479 43.43% 43.43% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 11292136 21.89% 65.32% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 5122096 9.93% 75.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3547417 6.88% 82.12% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2566622 4.97% 87.10% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1508057 2.92% 90.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 1006074 1.95% 91.97% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 827948 1.60% 93.57% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 3315405 6.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 22406480 43.57% 43.57% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 11177974 21.74% 65.31% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 5100083 9.92% 75.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3515976 6.84% 82.06% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 2514692 4.89% 86.95% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1504113 2.92% 89.87% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 1005597 1.96% 91.83% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 811447 1.58% 93.41% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 3390195 6.59% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 51596234 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 51426557 # Number of insts commited each cycle system.cpu.commit.COM:count 88340672 # Number of instructions committed -system.cpu.commit.COM:loads 20379399 # Number of loads committed +system.cpu.commit.COM:loads 20276638 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 35224018 # Number of memory references committed +system.cpu.commit.COM:refs 34890015 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 362306 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 362167 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 88340672 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 4583 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 8339248 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 8347307 # The number of squashed insts skipped by commit system.cpu.committedInsts 79591756 # Number of Instructions Simulated system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated -system.cpu.cpi 0.679309 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.679309 # CPI: Total CPI of All Threads +system.cpu.cpi 0.677497 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.677497 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 44 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_hits 44 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 20462752 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30131.608065 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20434.335315 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20316340 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4411629000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.007155 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 146412 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 84834 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 1258305500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.003009 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 61578 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 20461848 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30161.580175 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20422.684261 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20315611 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4410739000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.007147 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 146237 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 84626 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 1258262000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.003011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 61611 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 31003.810080 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32919.803194 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 13581378 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 31995900999 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.070620 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1031999 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 888502 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 4723892999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.009820 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 143497 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 32533.052088 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32982.737586 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 13581415 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 33572873499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.070618 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 1031962 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 888471 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 4732725999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.009819 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 143491 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 27000 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 165.294463 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 165.269329 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 27000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 35076129 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 30895.443100 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency -system.cpu.dcache.demand_hits 33897718 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 36407529999 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.033596 # miss rate for demand accesses -system.cpu.dcache.demand_misses 1178411 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 973336 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 5982198499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_accesses 35075225 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 32238.707128 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency +system.cpu.dcache.demand_hits 33897026 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 37983612499 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.033591 # miss rate for demand accesses +system.cpu.dcache.demand_misses 1178199 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 973097 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 5990987999 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005847 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 205075 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 205102 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995480 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4077.485052 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 35076129 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 30895.443100 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 29170.783855 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.995502 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4077.575152 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 35075225 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 32238.707128 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 29209.798047 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 33897718 # number of overall hits -system.cpu.dcache.overall_miss_latency 36407529999 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.033596 # miss rate for overall accesses -system.cpu.dcache.overall_misses 1178411 # number of overall misses -system.cpu.dcache.overall_mshr_hits 973336 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 5982198499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 33897026 # number of overall hits +system.cpu.dcache.overall_miss_latency 37983612499 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.033591 # miss rate for overall accesses +system.cpu.dcache.overall_misses 1178199 # number of overall misses +system.cpu.dcache.overall_mshr_hits 973097 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 5990987999 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005847 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 205075 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 205102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 200979 # number of replacements -system.cpu.dcache.sampled_refs 205075 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 201006 # number of replacements +system.cpu.dcache.sampled_refs 205102 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4077.485052 # Cycle average of tags in use -system.cpu.dcache.total_refs 33897762 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 181365000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 161485 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 3372983 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 97431 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3660168 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 101877731 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 28530714 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 19554245 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 1300005 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 281200 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 138292 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 36642762 # DTB accesses -system.cpu.dtb.data_acv 38 # DTB access violations -system.cpu.dtb.data_hits 36466941 # DTB hits -system.cpu.dtb.data_misses 175821 # DTB misses +system.cpu.dcache.tagsinuse 4077.575152 # Cycle average of tags in use +system.cpu.dcache.total_refs 33897070 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 178565000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 161507 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 3275994 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 97418 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3660154 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 101876983 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 28458490 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 19656582 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 1300870 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 282338 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 35491 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 36639089 # DTB accesses +system.cpu.dtb.data_acv 39 # DTB access violations +system.cpu.dtb.data_hits 36464202 # DTB hits +system.cpu.dtb.data_misses 174887 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 21568925 # DTB read accesses +system.cpu.dtb.read_accesses 21567895 # DTB read accesses system.cpu.dtb.read_acv 36 # DTB read access violations -system.cpu.dtb.read_hits 21411469 # DTB read hits -system.cpu.dtb.read_misses 157456 # DTB read misses -system.cpu.dtb.write_accesses 15073837 # DTB write accesses -system.cpu.dtb.write_acv 2 # DTB write access violations -system.cpu.dtb.write_hits 15055472 # DTB write hits -system.cpu.dtb.write_misses 18365 # DTB write misses -system.cpu.fetch.Branches 16281513 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 13394440 # Number of cache lines fetched -system.cpu.fetch.Cycles 33285984 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 153835 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 103456008 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 576870 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.301134 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 13394440 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 10015888 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.913464 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 52896239 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.955829 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.944816 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.read_hits 21410565 # DTB read hits +system.cpu.dtb.read_misses 157330 # DTB read misses +system.cpu.dtb.write_accesses 15071194 # DTB write accesses +system.cpu.dtb.write_acv 3 # DTB write access violations +system.cpu.dtb.write_hits 15053637 # DTB write hits +system.cpu.dtb.write_misses 17557 # DTB write misses +system.cpu.fetch.Branches 16280778 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 13394904 # Number of cache lines fetched +system.cpu.fetch.Cycles 33285903 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 154345 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 103458756 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 576280 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.301925 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 13394904 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 10015149 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.918633 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 52727427 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.962143 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.947691 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 33031612 62.45% 62.45% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1863332 3.52% 65.97% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1548849 2.93% 68.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 1858475 3.51% 72.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 3937136 7.44% 79.85% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1852242 3.50% 83.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 690247 1.30% 84.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1146451 2.17% 86.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 6967895 13.17% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 32863334 62.33% 62.33% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1866571 3.54% 65.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1546342 2.93% 68.80% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 1858063 3.52% 72.32% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 3933633 7.46% 79.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1853024 3.51% 83.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 690881 1.31% 84.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1144258 2.17% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 6971321 13.22% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 52896239 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 13394440 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 9549.980865 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 6051.228388 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 13305596 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 848458500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.006633 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 88844 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 2837 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 520448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.006421 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 86007 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 52727427 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 13394904 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 9553.478677 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 6055.148214 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 13306149 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 847919000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.006626 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 88755 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 2832 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 520276500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.006415 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 85923 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 154.705439 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 154.863120 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 13394440 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 9549.980865 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency -system.cpu.icache.demand_hits 13305596 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 848458500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.006633 # miss rate for demand accesses -system.cpu.icache.demand_misses 88844 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 2837 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 520448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.006421 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 86007 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 13394904 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 9553.478677 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency +system.cpu.icache.demand_hits 13306149 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 847919000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.006626 # miss rate for demand accesses +system.cpu.icache.demand_misses 88755 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 2832 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 520276500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.006415 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 85923 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.936980 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1918.935161 # Average occupied blocks per context -system.cpu.icache.overall_accesses 13394440 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 9549.980865 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 6051.228388 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.937341 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1919.673560 # Average occupied blocks per context +system.cpu.icache.overall_accesses 13394904 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 9553.478677 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 6055.148214 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 13305596 # number of overall hits -system.cpu.icache.overall_miss_latency 848458500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.006633 # miss rate for overall accesses -system.cpu.icache.overall_misses 88844 # number of overall misses -system.cpu.icache.overall_mshr_hits 2837 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 520448000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.006421 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 86007 # number of overall MSHR misses +system.cpu.icache.overall_hits 13306149 # number of overall hits +system.cpu.icache.overall_miss_latency 847919000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.006626 # miss rate for overall accesses +system.cpu.icache.overall_misses 88755 # number of overall misses +system.cpu.icache.overall_mshr_hits 2832 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 520276500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.006415 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 85923 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 83959 # number of replacements -system.cpu.icache.sampled_refs 86006 # Sample count of references to valid blocks. +system.cpu.icache.replacements 83875 # number of replacements +system.cpu.icache.sampled_refs 85922 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1918.935161 # Cycle average of tags in use -system.cpu.icache.total_refs 13305596 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1919.673560 # Cycle average of tags in use +system.cpu.icache.total_refs 13306149 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 1171140 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 14765953 # Number of branches executed -system.cpu.iew.EXEC:nop 9399098 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.570651 # Inst execution rate -system.cpu.iew.EXEC:refs 36985556 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 15306955 # Number of stores executed +system.cpu.idleCycles 1195746 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 14762410 # Number of branches executed +system.cpu.iew.EXEC:nop 9405310 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.574714 # Inst execution rate +system.cpu.iew.EXEC:refs 36640920 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 15071432 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 42195611 # num instructions consuming a value -system.cpu.iew.WB:count 84441959 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.765718 # average fanout of values written-back +system.cpu.iew.WB:consumers 42200394 # num instructions consuming a value +system.cpu.iew.WB:count 84434185 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.765638 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 32309953 # num instructions producing a value -system.cpu.iew.WB:rate 1.561791 # insts written-back per cycle -system.cpu.iew.WB:sent 84679067 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 403539 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 558736 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 23014663 # Number of dispatched load instructions +system.cpu.iew.WB:producers 32310240 # num instructions producing a value +system.cpu.iew.WB:rate 1.565824 # insts written-back per cycle +system.cpu.iew.WB:sent 84670704 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 403347 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 511454 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 22901502 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 5005 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 344896 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 16344120 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 99062445 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 21678601 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 539249 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 84921008 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 9867 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispSquashedInsts 341334 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 16112849 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 99067942 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 21569488 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 539182 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 84913582 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 10145 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 8786 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 1300005 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 41358 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 16238 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 1300870 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 39828 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 947297 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 703 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 947280 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 706 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 20504 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 1356 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 2635264 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 1499501 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 20504 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 133144 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 270395 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.472085 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.472085 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 20765 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 1373 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 2624864 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 1499472 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 20765 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 133024 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 270323 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.476021 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.476021 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 47958643 56.12% 56.12% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 42972 0.05% 56.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.17% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122098 0.14% 56.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 86 0.00% 56.31% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122222 0.14% 56.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.45% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38519 0.05% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 21787306 25.49% 81.99% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 15388360 18.01% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 48294833 56.52% 56.52% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 42901 0.05% 56.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 56.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 122014 0.14% 56.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 87 0.00% 56.71% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 122228 0.14% 56.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 51 0.00% 56.85% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 38521 0.05% 56.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 56.90% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 21679241 25.37% 82.27% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 15152888 17.73% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 85460257 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 970619 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.011358 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 85452764 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 905523 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.010597 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 98326 10.13% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 10.13% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 436344 44.96% 55.09% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 435949 44.91% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 99616 11.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 11.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 404792 44.70% 55.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 401115 44.30% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 52896239 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.615621 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.720411 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 52727427 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.620651 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.723782 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 17480622 33.05% 33.05% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 13990970 26.45% 59.50% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 8059116 15.24% 74.73% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 4840128 9.15% 83.88% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 4581404 8.66% 92.54% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2086569 3.94% 96.49% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1156021 2.19% 98.67% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 475188 0.90% 99.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 226221 0.43% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 17471285 33.14% 33.14% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 13743409 26.07% 59.20% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 8117223 15.39% 74.59% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 4850961 9.20% 83.79% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 4579502 8.69% 92.48% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2116514 4.01% 96.49% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1152468 2.19% 98.68% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 461880 0.88% 99.56% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 234185 0.44% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 52896239 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.580625 # Inst issue rate -system.cpu.iq.iqInstsAdded 89658342 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 85460257 # Number of instructions issued +system.cpu.iq.ISSUE:issued_per_cycle::total 52727427 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.584713 # Inst issue rate +system.cpu.iq.iqInstsAdded 89657627 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 85452764 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 5005 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 9847468 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 48230 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 9846565 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 47771 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 422 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 6786581 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 6801202 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 13421357 # ITB accesses +system.cpu.itb.fetch_accesses 13421810 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 13394440 # ITB hits -system.cpu.itb.fetch_misses 26917 # ITB misses +system.cpu.itb.fetch_hits 13394904 # ITB hits +system.cpu.itb.fetch_misses 26906 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,98 +343,98 @@ system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143498 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34310.090850 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31208.995937 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12072 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 4509238000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.915873 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 131426 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 4101673500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915873 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 131426 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 147584 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34134.410943 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.923979 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 103938 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 1489830500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.295737 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 43646 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1354463000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295737 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 43646 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 161485 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 161485 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 143493 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34337.769357 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31245.328098 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 12069 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 4512807000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.915891 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 131424 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 4106386000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915891 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 131424 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 147532 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34134.347507 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31032.670455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 103884 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 1489896000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.295854 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 43648 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1354514000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.295854 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 43648 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 161507 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 161507 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.759972 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.759811 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 291082 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34266.293296 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 116010 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 5999068500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.601453 # miss rate for demand accesses +system.cpu.l2cache.demand_accesses 291025 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34287.053327 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 115953 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 6002703000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.601570 # miss rate for demand accesses system.cpu.l2cache.demand_misses 175072 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 5456136500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.601453 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_latency 5460900000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.601570 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_misses 175072 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.094631 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.481096 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 3100.873906 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15764.562961 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 291082 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34266.293296 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31165.100644 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.094660 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.481148 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3101.833838 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15766.259215 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 291025 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34287.053327 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31192.309450 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 116010 # number of overall hits -system.cpu.l2cache.overall_miss_latency 5999068500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.601453 # miss rate for overall accesses +system.cpu.l2cache.overall_hits 115953 # number of overall hits +system.cpu.l2cache.overall_miss_latency 6002703000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.601570 # miss rate for overall accesses system.cpu.l2cache.overall_misses 175072 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 5456136500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.601453 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_latency 5460900000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.601570 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_misses 175072 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 148714 # number of replacements +system.cpu.l2cache.replacements 148712 # number of replacements system.cpu.l2cache.sampled_refs 174071 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18865.436867 # Cycle average of tags in use -system.cpu.l2cache.total_refs 132289 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18868.093053 # Cycle average of tags in use +system.cpu.l2cache.total_refs 132261 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120514 # number of writebacks -system.cpu.memDep0.conflictingLoads 12522416 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 11202183 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 23014663 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 16344120 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 54067379 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1899423 # Number of cycles rename is blocking +system.cpu.l2cache.writebacks 120513 # number of writebacks +system.cpu.memDep0.conflictingLoads 12487229 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 11176863 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 22901502 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 16112849 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 53923173 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1782763 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 52546881 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 50756 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 28921656 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 1270692 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 25 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 121761220 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 101056260 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 60792051 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 19304913 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 1300005 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 1392613 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 8245170 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 77629 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 5282 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 2690297 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 5280 # count of temporary serializing insts renamed -system.cpu.timesIdled 40629 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 52474 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 28901078 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 1299024 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 36 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 121755454 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 101053942 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 60784194 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 19225803 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 1300870 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 1439133 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 8237313 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 77780 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 5276 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 3015491 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 5274 # count of temporary serializing insts renamed +system.cpu.timesIdled 39379 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,12 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:20:31 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:44:15 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. +Exiting @ tick 44221003000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 3163275 # Simulator instruction rate (inst/s) -host_mem_usage 192676 # Number of bytes of host memory used -host_seconds 27.93 # Real time elapsed on the host -host_tick_rate 1583437342 # Simulator tick rate (ticks/s) +host_inst_rate 5477905 # Simulator instruction rate (inst/s) +host_mem_usage 240580 # Number of bytes of host memory used +host_seconds 16.13 # Real time elapsed on the host +host_tick_rate 2742055845 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.044221 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 88442007 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references +system.cpu.num_refs 34987415 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=vortex lendian.raw -cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:47:45 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:40:34 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/50.vortex/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1350777 # Simulator instruction rate (inst/s) -host_mem_usage 201544 # Number of bytes of host memory used -host_seconds 65.40 # Real time elapsed on the host -host_tick_rate 2053162286 # Simulator tick rate (ticks/s) +host_inst_rate 2249900 # Simulator instruction rate (inst/s) +host_mem_usage 248308 # Number of bytes of host memory used +host_seconds 39.26 # Real time elapsed on the host +host_tick_rate 3419804648 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 88340673 # Number of instructions simulated sim_seconds 0.134277 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 268553976 # number of cpu cycles simulated system.cpu.num_insts 88340673 # Number of instructions executed -system.cpu.num_refs 35321418 # Number of memory references +system.cpu.num_refs 34987415 # Number of memory references system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:04:52 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:41:19 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -28,4 +30,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! -Exiting @ tick 725600064000 because target called exit() +Exiting @ tick 723991197000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 201279 # Simulator instruction rate (inst/s) -host_mem_usage 193732 # Number of bytes of host memory used -host_seconds 8625.07 # Real time elapsed on the host -host_tick_rate 84126874 # Simulator tick rate (ticks/s) +host_inst_rate 217413 # Simulator instruction rate (inst/s) +host_mem_usage 240500 # Number of bytes of host memory used +host_seconds 7985.01 # Real time elapsed on the host +host_tick_rate 90668752 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1736043781 # Number of instructions simulated -sim_seconds 0.725600 # Number of seconds simulated -sim_ticks 725600064000 # Number of ticks simulated +sim_seconds 0.723991 # Number of seconds simulated +sim_ticks 723991197000 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 297121632 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 303782824 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 142 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 19928405 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 265297852 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 344822488 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 23968882 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 297134991 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 303959521 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 162 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 19913428 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 265314839 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 344584799 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 23886075 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 214632552 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 61479856 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 63016645 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 1350419468 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.347567 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 2.103580 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 1347786892 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.350199 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 2.111631 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 709166800 52.51% 52.51% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 257980850 19.10% 71.62% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 128756395 9.53% 81.15% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 75319653 5.58% 86.73% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 50577217 3.75% 90.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 29303662 2.17% 92.65% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 27183744 2.01% 94.66% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 10651291 0.79% 95.45% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 61479856 4.55% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 706265401 52.40% 52.40% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 261524956 19.40% 71.81% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 126857294 9.41% 81.22% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 73810788 5.48% 86.69% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 49267201 3.66% 90.35% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 31663388 2.35% 92.70% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 24079219 1.79% 94.49% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 11302000 0.84% 95.32% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 63016645 4.68% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 1350419468 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 1347786892 # Number of insts commited each cycle system.cpu.commit.COM:count 1819780126 # Number of instructions committed -system.cpu.commit.COM:loads 445666361 # Number of loads committed +system.cpu.commit.COM:loads 444595663 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 606571343 # Number of memory references committed +system.cpu.commit.COM:refs 605324165 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 19927893 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 19912897 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 598409142 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 594069052 # The number of squashed insts skipped by commit system.cpu.committedInsts 1736043781 # Number of Instructions Simulated system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated -system.cpu.cpi 0.835924 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.835924 # CPI: Total CPI of All Threads +system.cpu.cpi 0.834070 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.834070 # CPI: Total CPI of All Threads system.cpu.dcache.LoadLockedReq_accesses 3 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_avg_miss_latency 38500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency @@ -59,289 +59,289 @@ system.cpu.dcache.LoadLockedReq_mshr_miss_latency 35500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate 0.333333 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses -system.cpu.dcache.ReadReq_accesses 522152433 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 16274.867726 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10956.764593 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 512203202 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 161922418500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.019054 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 9949231 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 2672880 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 79725265000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.013935 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 7276351 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_accesses 521802290 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 16279.064598 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 10961.675998 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 511855593 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 161922923000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.019062 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 9946697 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 2670317 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 79761320000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate 0.013945 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_misses 7276380 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 26917.452067 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20483.226007 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 155989745 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 127555264405 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.029483 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 4738757 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 2853938 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 38607173559 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 27145.945678 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20467.767187 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 155989397 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 128647486892 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.029485 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4739105 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 2854288 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 38577995547 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.011727 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1884819 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs 3154.492044 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_mshr_misses 1884817 # number of WriteReq MSHR misses +system.cpu.dcache.avg_blocked_cycles::no_mshrs 3153.493916 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets 30417.808324 # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 72.937504 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 37706 # number of cycles access was blocked +system.cpu.dcache.avg_refs 72.899308 # Average number of references to valid blocks. +system.cpu.dcache.blocked::no_mshrs 37723 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 65110 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 118943277 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_mshrs 118959251 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 1980503500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 682880935 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 19708.464012 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency -system.cpu.dcache.demand_hits 668192947 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 289477682905 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.021509 # miss rate for demand accesses -system.cpu.dcache.demand_misses 14687988 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 5526818 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 118332438559 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.013415 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 9161170 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_accesses 682530792 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 19785.804677 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency +system.cpu.dcache.demand_hits 667844990 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 290570409892 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.021517 # miss rate for demand accesses +system.cpu.dcache.demand_misses 14685802 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 5524605 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 118339315547 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_rate 0.013422 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_misses 9161197 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.997445 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4085.532750 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 682880935 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 19708.464012 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 12916.738644 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.997439 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4085.509480 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 682530792 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 19785.804677 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 12917.451240 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 668192947 # number of overall hits -system.cpu.dcache.overall_miss_latency 289477682905 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.021509 # miss rate for overall accesses -system.cpu.dcache.overall_misses 14687988 # number of overall misses -system.cpu.dcache.overall_mshr_hits 5526818 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 118332438559 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.013415 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 9161170 # number of overall MSHR misses +system.cpu.dcache.overall_hits 667844990 # number of overall hits +system.cpu.dcache.overall_miss_latency 290570409892 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.021517 # miss rate for overall accesses +system.cpu.dcache.overall_misses 14685802 # number of overall misses +system.cpu.dcache.overall_mshr_hits 5524605 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 118339315547 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_rate 0.013422 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_misses 9161197 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 9157075 # number of replacements -system.cpu.dcache.sampled_refs 9161171 # Sample count of references to valid blocks. +system.cpu.dcache.replacements 9157102 # number of replacements +system.cpu.dcache.sampled_refs 9161198 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4085.532750 # Cycle average of tags in use -system.cpu.dcache.total_refs 668192949 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 7084076000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 3077872 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 79445863 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 739 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 54863160 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 2804005174 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 723465377 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 543368654 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 89450574 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 1719 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 4139574 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 765936230 # DTB accesses +system.cpu.dcache.tagsinuse 4085.509480 # Cycle average of tags in use +system.cpu.dcache.total_refs 667844992 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 7084078000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 3077854 # number of writebacks +system.cpu.decode.DECODE:BlockedCycles 78806586 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 620 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 54720823 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 2797425384 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 722637583 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 541899569 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 88987438 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 1777 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 4443154 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 767802302 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 750636298 # DTB hits -system.cpu.dtb.data_misses 15299932 # DTB misses +system.cpu.dtb.data_hits 752449535 # DTB hits +system.cpu.dtb.data_misses 15352767 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 565223455 # DTB read accesses +system.cpu.dtb.read_accesses 566812903 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 556102001 # DTB read hits -system.cpu.dtb.read_misses 9121454 # DTB read misses -system.cpu.dtb.write_accesses 200712775 # DTB write accesses +system.cpu.dtb.read_hits 557652499 # DTB read hits +system.cpu.dtb.read_misses 9160404 # DTB read misses +system.cpu.dtb.write_accesses 200989399 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 194534297 # DTB write hits -system.cpu.dtb.write_misses 6178478 # DTB write misses -system.cpu.fetch.Branches 344822488 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 355034186 # Number of cache lines fetched -system.cpu.fetch.Cycles 913253672 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 8462729 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 2857790040 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 28218175 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.237612 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 355034186 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 321090514 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 1.969260 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 1439870042 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.984756 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.874458 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 194797036 # DTB write hits +system.cpu.dtb.write_misses 6192363 # DTB write misses +system.cpu.fetch.Branches 344584799 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 354412327 # Number of cache lines fetched +system.cpu.fetch.Cycles 911372250 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 8690810 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 2851036906 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 28190849 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.237976 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 354412327 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 321021066 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 1.968972 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 1436774330 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.984332 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.873889 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 881650589 61.23% 61.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 48391639 3.36% 64.59% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 30824264 2.14% 66.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 51186075 3.55% 70.29% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 123166257 8.55% 78.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 68161636 4.73% 83.58% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 47264733 3.28% 86.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 36668750 2.55% 89.40% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 152556099 10.60% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 879814440 61.24% 61.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 48078779 3.35% 64.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 31070380 2.16% 66.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 51055446 3.55% 70.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 122790894 8.55% 78.84% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 67990825 4.73% 83.58% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 47151543 3.28% 86.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 36952114 2.57% 89.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 151869909 10.57% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 1439870042 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 355034186 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 35334.265176 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 35459.890110 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 355032934 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 44238500 # number of ReadReq miss cycles +system.cpu.fetch.rateDist::total 1436774330 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 354412327 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 35305.051302 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 35462.540717 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 354411060 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 44731500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 1252 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 342 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 32268500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_misses 1267 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 346 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 32661000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate 0.000003 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 910 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses 921 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 390146.081319 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 384811.140065 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 355034186 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 35334.265176 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency -system.cpu.icache.demand_hits 355032934 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 44238500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_accesses 354412327 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 35305.051302 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency +system.cpu.icache.demand_hits 354411060 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 44731500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses -system.cpu.icache.demand_misses 1252 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 342 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 32268500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_misses 1267 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 346 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 32661000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate 0.000003 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 910 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses 921 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.349698 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 716.180731 # Average occupied blocks per context -system.cpu.icache.overall_accesses 355034186 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 35334.265176 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 35459.890110 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.352268 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 721.445735 # Average occupied blocks per context +system.cpu.icache.overall_accesses 354412327 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 35305.051302 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 35462.540717 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 355032934 # number of overall hits -system.cpu.icache.overall_miss_latency 44238500 # number of overall miss cycles +system.cpu.icache.overall_hits 354411060 # number of overall hits +system.cpu.icache.overall_miss_latency 44731500 # number of overall miss cycles system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses -system.cpu.icache.overall_misses 1252 # number of overall misses -system.cpu.icache.overall_mshr_hits 342 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 32268500 # number of overall MSHR miss cycles +system.cpu.icache.overall_misses 1267 # number of overall misses +system.cpu.icache.overall_mshr_hits 346 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 32661000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_rate 0.000003 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 910 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses 921 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 1 # number of replacements -system.cpu.icache.sampled_refs 910 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 921 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 716.180731 # Cycle average of tags in use -system.cpu.icache.total_refs 355032934 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 721.445735 # Cycle average of tags in use +system.cpu.icache.total_refs 354411060 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 11330087 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 280332781 # Number of branches executed -system.cpu.iew.EXEC:nop 129121920 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.560467 # Inst execution rate -system.cpu.iew.EXEC:refs 767231280 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 200922716 # Number of stores executed +system.cpu.idleCycles 11208065 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 280169878 # Number of branches executed +system.cpu.iew.EXEC:nop 129057525 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.565430 # Inst execution rate +system.cpu.iew.EXEC:refs 767802324 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 200989407 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 1522686548 # num instructions consuming a value -system.cpu.iew.WB:count 2225893734 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.811633 # average fanout of values written-back +system.cpu.iew.WB:consumers 1523016532 # num instructions consuming a value +system.cpu.iew.WB:count 2228484684 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.811571 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 1235862105 # num instructions producing a value -system.cpu.iew.WB:rate 1.533830 # insts written-back per cycle -system.cpu.iew.WB:sent 2246790117 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 21706516 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 15735224 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 619699188 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 21567119 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 233370796 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 2608680423 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 566308564 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 37529963 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 2264549792 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 297607 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 1236036667 # num instructions producing a value +system.cpu.iew.WB:rate 1.539027 # insts written-back per cycle +system.cpu.iew.WB:sent 2249496581 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 21722236 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 15314374 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 617102957 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 45 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 21692258 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 232568585 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 2603343055 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 566812917 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 38578662 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 2266715425 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 389623 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 27486 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 89450574 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 675659 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 18477 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 88987438 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 694096 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread.0.cacheBlocked 161623 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 33872925 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 214320 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.cacheBlocked 161793 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread.0.forwLoads 35773426 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 210663 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 2995791 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.memOrderViolation 2851639 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 17 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 174032827 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 72465814 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 2995791 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 3378494 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 18328022 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.196281 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.196281 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.squashedLoads 172507294 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 71840083 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 2851639 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 3390000 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 18332236 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.198940 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.198940 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 1521321100 66.08% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 97 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 232 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 138 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 17 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.08% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 576616052 25.05% 91.13% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 204142076 8.87% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 1523557218 66.09% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 93 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 225 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 19 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 139 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 15 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 24 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 577672336 25.06% 91.15% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 204064018 8.85% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 2302079755 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 12945104 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.005623 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 2305294087 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 13339064 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.005786 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 2890284 22.33% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 22.33% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 8361572 64.59% 86.92% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 1693248 13.08% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 3077619 23.07% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 23.07% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 8405753 63.02% 86.09% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 1855692 13.91% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 1439870042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.598811 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.750982 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 1436774330 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.604493 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.761639 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 553825571 38.46% 38.46% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 266666629 18.52% 56.98% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 241255351 16.76% 73.74% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 143700504 9.98% 83.72% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 114580764 7.96% 91.68% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 70398755 4.89% 96.57% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 36702113 2.55% 99.12% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 10651437 0.74% 99.85% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 2088918 0.15% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 552319838 38.44% 38.44% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 267044119 18.59% 57.03% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 243823244 16.97% 74.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 135766343 9.45% 83.45% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 111649965 7.77% 91.22% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 72620793 5.05% 96.27% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 43154972 3.00% 99.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 8489654 0.59% 99.87% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 1905402 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 1439870042 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.586328 # Inst issue rate -system.cpu.iq.iqInstsAdded 2479558460 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 2302079755 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 43 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 726499267 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 996261 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 330157127 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 1436774330 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.592073 # Inst issue rate +system.cpu.iq.iqInstsAdded 2474285485 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 2305294087 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 45 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 718781925 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 1290278 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 318719479 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 355034219 # ITB accesses +system.cpu.itb.fetch_accesses 354412360 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 355034186 # ITB hits +system.cpu.itb.fetch_hits 354412327 # ITB hits system.cpu.itb.fetch_misses 33 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -351,98 +351,98 @@ system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1884821 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34451.716970 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31263.065922 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 1001550 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 30430202500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.468623 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 883271 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 27613759500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468623 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 883271 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 7277260 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34300.261562 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.501409 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5456659 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 62447090500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.250177 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 1820601 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 56685325000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250177 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 1820601 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 3077872 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 3077872 # number of Writeback hits -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10336.866902 # average number of cycles each access was blocked +system.cpu.l2cache.ReadExReq_accesses 1884819 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34457.281872 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31270.548143 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 1001564 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 30434566500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.468615 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 883255 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 27619868000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.468615 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 883255 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 7277300 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34308.231469 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31135.566655 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 5456738 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 62460262500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.250170 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 1820562 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 56684229500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250170 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 1820562 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 3077854 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 3077854 # number of Writeback hits +system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10339.327830 # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.807813 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 1698 # number of cycles access was blocked +system.cpu.l2cache.avg_refs 2.807892 # Average number of references to valid blocks. +system.cpu.l2cache.blocked::no_mshrs 1696 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 17552000 # number of cycles access was blocked +system.cpu.l2cache.blocked_cycles::no_mshrs 17535500 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 9162081 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34349.737340 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6458209 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 92877293000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.295115 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 2703872 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 9162119 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34356.921715 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 6458302 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 92894829000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.295108 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 2703817 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 84299084500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.295115 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 2703872 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 84304097500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.295108 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 2703817 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.484528 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.327269 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 15877.018497 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 10723.955560 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 9162081 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34349.737340 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31177.172773 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.484040 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.327555 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 15861.025964 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 10733.328518 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 9162119 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34356.921715 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31179.661013 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6458209 # number of overall hits -system.cpu.l2cache.overall_miss_latency 92877293000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.295115 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 2703872 # number of overall misses +system.cpu.l2cache.overall_hits 6458302 # number of overall hits +system.cpu.l2cache.overall_miss_latency 92894829000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.295108 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 2703817 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 84299084500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.295115 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 2703872 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 84304097500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.295108 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 2703817 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 2693288 # number of replacements -system.cpu.l2cache.sampled_refs 2717930 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 2693237 # number of replacements +system.cpu.l2cache.sampled_refs 2717881 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 26600.974057 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7631439 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 148178401500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 1171803 # number of writebacks -system.cpu.memDep0.conflictingLoads 134698193 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 69978801 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 619699188 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 233370796 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 1451200129 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 52056982 # Number of cycles rename is blocking +system.cpu.l2cache.tagsinuse 26594.354482 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7631516 # Total number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 148066834500 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.writebacks 1171784 # number of writebacks +system.cpu.memDep0.conflictingLoads 123159990 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 64312407 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 617102957 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 232568585 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 1447982395 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 51393371 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 1376202963 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 6212885 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 741942603 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 18353930 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:ROBFullEvents 492222 # Number of times rename has blocked due to ROB full -system.cpu.rename.RENAME:RenameLookups 3542299573 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 2739870490 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 2052189295 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 529159748 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 89450574 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 27259412 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 675986332 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 723 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 48 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 54988572 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 46 # count of temporary serializing insts renamed -system.cpu.timesIdled 434261 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 5887635 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 740841122 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 18541128 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:ROBFullEvents 493389 # Number of times rename has blocked due to ROB full +system.cpu.rename.RENAME:RenameLookups 3535273918 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 2734162916 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 2047681663 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 528076479 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 88987438 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 27475071 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 671478700 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 849 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 54007891 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 47 # count of temporary serializing insts renamed +system.cpu.timesIdled 425188 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:01:37 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:35:16 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -28,3 +30,4 @@ Uncompressed data 1048576 bytes in length Uncompressed data compared correctly Tested 1MB buffer: OK! +Exiting @ tick 913189263000 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1736234 # Simulator instruction rate (inst/s) -host_mem_usage 184024 # Number of bytes of host memory used -host_seconds 1048.12 # Real time elapsed on the host -host_tick_rate 871264314 # Simulator tick rate (ticks/s) +host_inst_rate 5747960 # Simulator instruction rate (inst/s) +host_mem_usage 231948 # Number of bytes of host memory used +host_seconds 316.60 # Real time elapsed on the host +host_tick_rate 2884399053 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 0.913189 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 1826378527 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 613169725 # Number of memory references +system.cpu.num_refs 611922547 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=bzip2 input.source 1 -cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/bzip2 +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/bzip2 gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:33:53 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:53:28 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/60.bzip2/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1370976 # Simulator instruction rate (inst/s) -host_mem_usage 192892 # Number of bytes of host memory used -host_seconds 1327.36 # Real time elapsed on the host -host_tick_rate 2006569980 # Simulator tick rate (ticks/s) +host_inst_rate 2423488 # Simulator instruction rate (inst/s) +host_mem_usage 239668 # Number of bytes of host memory used +host_seconds 750.89 # Real time elapsed on the host +host_tick_rate 3547033530 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 1819780127 # Number of instructions simulated sim_seconds 2.663444 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 5326887432 # number of cpu cycles simulated system.cpu.num_insts 1819780127 # Number of instructions executed -system.cpu.num_refs 613169725 # Number of memory references +system.cpu.num_refs 611922547 # Number of memory references system.cpu.workload.PROG:num_syscalls 29 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -186,12 +186,12 @@ [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 -warn: Prefetching currently unimplemented -For more information see: http://www.m5sim.org/warn/8028fa22 -warn: Write Hints currently unimplemented -For more information see: http://www.m5sim.org/warn/cfb3293b warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:52:34 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:31:02 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 54763 # Simulator instruction rate (inst/s) -host_mem_usage 197304 # Number of bytes of host memory used -host_seconds 1678.20 # Real time elapsed on the host -host_tick_rate 58595727 # Simulator tick rate (ticks/s) +host_inst_rate 68324 # Simulator instruction rate (inst/s) +host_mem_usage 244132 # Number of bytes of host memory used +host_seconds 1345.11 # Real time elapsed on the host +host_tick_rate 73105878 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.098335 # Number of seconds simulated sim_ticks 98335161000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 26537108 # Number of Address Generations +system.cpu.AGEN-Unit.agens 26497301 # Number of Address Generations system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits system.cpu.Branch-Predictor.BTBLookups 8584401 # Number of BTB lookups @@ -19,7 +19,7 @@ system.cpu.Branch-Predictor.predictedNotTaken 2702033 # Number of Branches Predicted As Not Taken (False). system.cpu.Branch-Predictor.predictedTaken 7538652 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 64907696 # Number of Instructions Executed. +system.cpu.Execution-Unit.executions 64947503 # Number of Instructions Executed. system.cpu.Execution-Unit.mispredictPct 22.664900 # Percentage of Incorrect Branches Predicts system.cpu.Execution-Unit.mispredicted 2321041 # Number of Branches Incorrectly Predicted system.cpu.Execution-Unit.predicted 7919644 # Number of Branches Incorrectly Predicted @@ -31,14 +31,14 @@ system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 95.462227 # Percentage of cycles cpu is active +system.cpu.activity 95.462226 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed -system.cpu.comInts 43625545 # Number of Integer instructions committed -system.cpu.comLoads 20034413 # Number of Load instructions committed +system.cpu.comInts 43665352 # Number of Integer instructions committed +system.cpu.comLoads 19996198 # Number of Load instructions committed system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed system.cpu.comNops 7723346 # Number of Nop instructions committed -system.cpu.comStores 6502695 # Number of Store instructions committed +system.cpu.comStores 6501103 # Number of Store instructions committed system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches @@ -181,7 +181,7 @@ system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8924453 # Number of cycles cpu's stages were not processed +system.cpu.idleCycles 8924455 # Number of cycles cpu's stages were not processed system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses @@ -270,7 +270,7 @@ system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.numCycles 196670323 # number of cpu cycles simulated -system.cpu.runCycles 187745870 # Number of cycles cpu stages are processed. +system.cpu.runCycles 187745868 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI @@ -284,9 +284,9 @@ system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed. system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 170133192 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 26537131 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.493206 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 170172999 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 26497324 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 13.472965 # Percentage of cycles stage was utilized (processing insts). system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed. system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -353,12 +353,12 @@ [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,12 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:34:48 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:27:52 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -27,4 +28,4 @@ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 40701237000 because target called exit() +122 123 124 Exiting @ tick 40631511500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,340 +1,340 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 172806 # Simulator instruction rate (inst/s) -host_mem_usage 197872 # Number of bytes of host memory used -host_seconds 487.13 # Real time elapsed on the host -host_tick_rate 83552440 # Simulator tick rate (ticks/s) +host_inst_rate 191238 # Simulator instruction rate (inst/s) +host_mem_usage 244496 # Number of bytes of host memory used +host_seconds 440.18 # Real time elapsed on the host +host_tick_rate 92306061 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 84179709 # Number of instructions simulated -sim_seconds 0.040701 # Number of seconds simulated -sim_ticks 40701237000 # Number of ticks simulated +sim_seconds 0.040632 # Number of seconds simulated +sim_ticks 40631511500 # Number of ticks simulated system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.BTBHits 11915545 # Number of BTB hits -system.cpu.BPredUnit.BTBLookups 15874334 # Number of BTB lookups -system.cpu.BPredUnit.RASInCorrect 1218 # Number of incorrect RAS predictions. -system.cpu.BPredUnit.condIncorrect 1889899 # Number of conditional branches incorrect -system.cpu.BPredUnit.condPredicted 14602096 # Number of conditional branches predicted -system.cpu.BPredUnit.lookups 19578655 # Number of BP lookups -system.cpu.BPredUnit.usedRAS 1736849 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.BTBHits 11932962 # Number of BTB hits +system.cpu.BPredUnit.BTBLookups 15864027 # Number of BTB lookups +system.cpu.BPredUnit.RASInCorrect 1214 # Number of incorrect RAS predictions. +system.cpu.BPredUnit.condIncorrect 1885603 # Number of conditional branches incorrect +system.cpu.BPredUnit.condPredicted 14586720 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 19564106 # Number of BP lookups +system.cpu.BPredUnit.usedRAS 1732867 # Number of times the RAS was used to get a target. system.cpu.commit.COM:branches 10240685 # Number of branches committed -system.cpu.commit.COM:bw_lim_events 2864912 # number cycles where commit BW limit reached +system.cpu.commit.COM:bw_lim_events 2884434 # number cycles where commit BW limit reached system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits -system.cpu.commit.COM:committed_per_cycle::samples 73200571 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::mean 1.255496 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::stdev 1.951465 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::samples 73022923 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::mean 1.258551 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::stdev 1.953672 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::0 35883667 49.02% 49.02% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::1 18420857 25.16% 74.19% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::2 7399798 10.11% 84.29% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::3 3793136 5.18% 89.48% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::4 2033346 2.78% 92.25% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::5 1324316 1.81% 94.06% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::6 734839 1.00% 95.07% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::7 745700 1.02% 96.09% # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::8 2864912 3.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::0 35697739 48.89% 48.89% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::1 18400471 25.20% 74.08% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::2 7461073 10.22% 84.30% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::3 3811930 5.22% 89.52% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::4 1995705 2.73% 92.25% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::5 1288642 1.76% 94.02% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::6 737357 1.01% 95.03% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::7 745572 1.02% 96.05% # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::8 2884434 3.95% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.COM:committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.COM:committed_per_cycle::total 73200571 # Number of insts commited each cycle +system.cpu.commit.COM:committed_per_cycle::total 73022923 # Number of insts commited each cycle system.cpu.commit.COM:count 91903055 # Number of instructions committed -system.cpu.commit.COM:loads 20034413 # Number of loads committed +system.cpu.commit.COM:loads 19996198 # Number of loads committed system.cpu.commit.COM:membars 0 # Number of memory barriers committed -system.cpu.commit.COM:refs 26537108 # Number of memory references committed +system.cpu.commit.COM:refs 26497301 # Number of memory references committed system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.branchMispredicts 1876760 # The number of times a branch was mispredicted +system.cpu.commit.branchMispredicts 1872416 # The number of times a branch was mispredicted system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.commitSquashedInsts 56257975 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 56371965 # The number of squashed insts skipped by commit system.cpu.committedInsts 84179709 # Number of Instructions Simulated system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated -system.cpu.cpi 0.967008 # CPI: Cycles Per Instruction -system.cpu.cpi_total 0.967008 # CPI: Total CPI of All Threads -system.cpu.dcache.LoadLockedReq_accesses 11 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_hits 11 # number of LoadLockedReq hits -system.cpu.dcache.ReadReq_accesses 23361980 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 30151.634724 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32163.725490 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 23361093 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 26744500 # number of ReadReq miss cycles +system.cpu.cpi 0.965352 # CPI: Cycles Per Instruction +system.cpu.cpi_total 0.965352 # CPI: Total CPI of All Threads +system.cpu.dcache.LoadLockedReq_accesses 10 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_hits 10 # number of LoadLockedReq hits +system.cpu.dcache.ReadReq_accesses 23336477 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_avg_miss_latency 30318.337130 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32167.647059 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 23335599 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26619500 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_rate 0.000038 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 887 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_hits 377 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_miss_latency 16403500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_misses 878 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 368 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 16405500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000022 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 510 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 35569.269207 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35483.256351 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6493098 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 284732000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.001231 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 8005 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_hits 6273 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_miss_latency 61457000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.000266 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 1732 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_avg_miss_latency 35388.341031 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35272.360069 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6493092 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 283496000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.001232 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 8011 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 6278 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 61127000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_rate 0.000267 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_misses 1733 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs 1500 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 13315.879572 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 13298.573785 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 1500 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 29863083 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 35028.846154 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency -system.cpu.dcache.demand_hits 29854191 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 311476500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_accesses 29837580 # number of demand (read+write) accesses +system.cpu.dcache.demand_avg_miss_latency 34887.557656 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency +system.cpu.dcache.demand_hits 29828691 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 310115500 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_rate 0.000298 # miss rate for demand accesses -system.cpu.dcache.demand_misses 8892 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 6650 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 77860500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_misses 8889 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 6646 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 77532500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000075 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 2242 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses 2243 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.356508 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1460.254824 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 29863083 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 35028.846154 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 34728.144514 # average overall mshr miss latency +system.cpu.dcache.occ_%::0 0.356524 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1460.322095 # Average occupied blocks per context +system.cpu.dcache.overall_accesses 29837580 # number of overall (read+write) accesses +system.cpu.dcache.overall_avg_miss_latency 34887.557656 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 34566.428890 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 29854191 # number of overall hits -system.cpu.dcache.overall_miss_latency 311476500 # number of overall miss cycles +system.cpu.dcache.overall_hits 29828691 # number of overall hits +system.cpu.dcache.overall_miss_latency 310115500 # number of overall miss cycles system.cpu.dcache.overall_miss_rate 0.000298 # miss rate for overall accesses -system.cpu.dcache.overall_misses 8892 # number of overall misses -system.cpu.dcache.overall_mshr_hits 6650 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 77860500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_misses 8889 # number of overall misses +system.cpu.dcache.overall_mshr_hits 6646 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 77532500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000075 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 2242 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses 2243 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.dcache.replacements 160 # number of replacements -system.cpu.dcache.sampled_refs 2242 # Sample count of references to valid blocks. +system.cpu.dcache.sampled_refs 2243 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1460.254824 # Cycle average of tags in use -system.cpu.dcache.total_refs 29854202 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1460.322095 # Cycle average of tags in use +system.cpu.dcache.total_refs 29828701 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 109 # number of writebacks -system.cpu.decode.DECODE:BlockedCycles 4195761 # Number of cycles decode is blocked -system.cpu.decode.DECODE:BranchMispred 13279 # Number of times decode detected a branch misprediction -system.cpu.decode.DECODE:BranchResolved 3138343 # Number of times decode resolved a branch -system.cpu.decode.DECODE:DecodedInsts 162326891 # Number of instructions handled by decode -system.cpu.decode.DECODE:IdleCycles 39347906 # Number of cycles decode is idle -system.cpu.decode.DECODE:RunCycles 29437041 # Number of cycles decode is running -system.cpu.decode.DECODE:SquashCycles 8093015 # Number of cycles decode is squashing -system.cpu.decode.DECODE:SquashedInsts 48049 # Number of squashed instructions handled by decode -system.cpu.decode.DECODE:UnblockCycles 219863 # Number of cycles decode is unblocking -system.cpu.dtb.data_accesses 31798533 # DTB accesses +system.cpu.decode.DECODE:BlockedCycles 3982765 # Number of cycles decode is blocked +system.cpu.decode.DECODE:BranchMispred 13329 # Number of times decode detected a branch misprediction +system.cpu.decode.DECODE:BranchResolved 3143444 # Number of times decode resolved a branch +system.cpu.decode.DECODE:DecodedInsts 162519421 # Number of instructions handled by decode +system.cpu.decode.DECODE:IdleCycles 39357415 # Number of cycles decode is idle +system.cpu.decode.DECODE:RunCycles 29479520 # Number of cycles decode is running +system.cpu.decode.DECODE:SquashCycles 8131535 # Number of cycles decode is squashing +system.cpu.decode.DECODE:SquashedInsts 48925 # Number of squashed instructions handled by decode +system.cpu.decode.DECODE:UnblockCycles 203223 # Number of cycles decode is unblocking +system.cpu.dtb.data_accesses 31749224 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 31420024 # DTB hits -system.cpu.dtb.data_misses 378509 # DTB misses +system.cpu.dtb.data_hits 31371389 # DTB hits +system.cpu.dtb.data_misses 377835 # DTB misses system.cpu.dtb.fetch_accesses 0 # ITB accesses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 24587243 # DTB read accesses +system.cpu.dtb.read_accesses 24565202 # DTB read accesses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 24209793 # DTB read hits -system.cpu.dtb.read_misses 377450 # DTB read misses -system.cpu.dtb.write_accesses 7211290 # DTB write accesses +system.cpu.dtb.read_hits 24188408 # DTB read hits +system.cpu.dtb.read_misses 376794 # DTB read misses +system.cpu.dtb.write_accesses 7184022 # DTB write accesses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 7210231 # DTB write hits -system.cpu.dtb.write_misses 1059 # DTB write misses -system.cpu.fetch.Branches 19578655 # Number of branches that fetch encountered -system.cpu.fetch.CacheLines 19042384 # Number of cache lines fetched -system.cpu.fetch.Cycles 49581925 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.IcacheSquashes 482421 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.Insts 167418269 # Number of instructions fetch has processed -system.cpu.fetch.SquashCycles 2029286 # Number of cycles fetch has spent squashing -system.cpu.fetch.branchRate 0.240517 # Number of branch fetches per cycle -system.cpu.fetch.icacheStallCycles 19042384 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.predictedBranches 13652394 # Number of branches that fetch has predicted taken -system.cpu.fetch.rate 2.056673 # Number of inst fetches per cycle -system.cpu.fetch.rateDist::samples 81293586 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 2.059428 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.087450 # Number of instructions fetched each cycle (Total) +system.cpu.dtb.write_hits 7182981 # DTB write hits +system.cpu.dtb.write_misses 1041 # DTB write misses +system.cpu.fetch.Branches 19564106 # Number of branches that fetch encountered +system.cpu.fetch.CacheLines 19059447 # Number of cache lines fetched +system.cpu.fetch.Cycles 49623738 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.IcacheSquashes 482133 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.Insts 167632917 # Number of instructions fetch has processed +system.cpu.fetch.SquashCycles 2031289 # Number of cycles fetch has spent squashing +system.cpu.fetch.branchRate 0.240750 # Number of branch fetches per cycle +system.cpu.fetch.icacheStallCycles 19059447 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.predictedBranches 13665829 # Number of branches that fetch has predicted taken +system.cpu.fetch.rate 2.062844 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::samples 81154458 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 2.065603 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 3.090223 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 50754116 62.43% 62.43% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 3139628 3.86% 66.30% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1895979 2.33% 68.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3231029 3.97% 72.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 4381369 5.39% 77.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1498108 1.84% 79.83% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 1855702 2.28% 82.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 1657872 2.04% 84.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 12879783 15.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 50590239 62.34% 62.34% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 3137902 3.87% 66.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1890959 2.33% 68.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3231189 3.98% 72.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 4367674 5.38% 77.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1502603 1.85% 79.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 1888200 2.33% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 1658917 2.04% 84.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 12886775 15.88% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 81293586 # Number of instructions fetched each cycle (Total) -system.cpu.icache.ReadReq_accesses 19042384 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 15742.896836 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11872.070120 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 19031227 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 175643500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000586 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 11157 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1003 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 120549000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000533 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 10154 # number of ReadReq MSHR misses +system.cpu.fetch.rateDist::total 81154458 # Number of instructions fetched each cycle (Total) +system.cpu.icache.ReadReq_accesses 19059447 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 15766.588953 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 11899.082569 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 19048295 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 175829000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.000585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 11152 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 1015 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 120621000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.000532 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 10137 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1874.259110 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1879.086022 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 19042384 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 15742.896836 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency -system.cpu.icache.demand_hits 19031227 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 175643500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000586 # miss rate for demand accesses -system.cpu.icache.demand_misses 11157 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1003 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 120549000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000533 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 10154 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 19059447 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 15766.588953 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency +system.cpu.icache.demand_hits 19048295 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 175829000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.000585 # miss rate for demand accesses +system.cpu.icache.demand_misses 11152 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 1015 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 120621000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.000532 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 10137 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.756089 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1548.470149 # Average occupied blocks per context -system.cpu.icache.overall_accesses 19042384 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 15742.896836 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11872.070120 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.756347 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1548.997868 # Average occupied blocks per context +system.cpu.icache.overall_accesses 19059447 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 15766.588953 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 11899.082569 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 19031227 # number of overall hits -system.cpu.icache.overall_miss_latency 175643500 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000586 # miss rate for overall accesses -system.cpu.icache.overall_misses 11157 # number of overall misses -system.cpu.icache.overall_mshr_hits 1003 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 120549000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000533 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 10154 # number of overall MSHR misses +system.cpu.icache.overall_hits 19048295 # number of overall hits +system.cpu.icache.overall_miss_latency 175829000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.000585 # miss rate for overall accesses +system.cpu.icache.overall_misses 11152 # number of overall misses +system.cpu.icache.overall_mshr_hits 1015 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 120621000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.000532 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 10137 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 8238 # number of replacements -system.cpu.icache.sampled_refs 10154 # Sample count of references to valid blocks. +system.cpu.icache.replacements 8219 # number of replacements +system.cpu.icache.sampled_refs 10137 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1548.470149 # Cycle average of tags in use -system.cpu.icache.total_refs 19031227 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1548.997868 # Cycle average of tags in use +system.cpu.icache.total_refs 19048295 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 108889 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.iew.EXEC:branches 12932789 # Number of branches executed -system.cpu.iew.EXEC:nop 12752151 # number of nop insts executed -system.cpu.iew.EXEC:rate 1.252018 # Inst execution rate -system.cpu.iew.EXEC:refs 31851951 # number of memory reference insts executed -system.cpu.iew.EXEC:stores 7212939 # Number of stores executed +system.cpu.idleCycles 108566 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.iew.EXEC:branches 12934750 # Number of branches executed +system.cpu.iew.EXEC:nop 12801851 # number of nop insts executed +system.cpu.iew.EXEC:rate 1.253335 # Inst execution rate +system.cpu.iew.EXEC:refs 31749416 # number of memory reference insts executed +system.cpu.iew.EXEC:stores 7184063 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed -system.cpu.iew.WB:consumers 91351431 # num instructions consuming a value -system.cpu.iew.WB:count 100121785 # cumulative count of insts written-back -system.cpu.iew.WB:fanout 0.722504 # average fanout of values written-back +system.cpu.iew.WB:consumers 91396336 # num instructions consuming a value +system.cpu.iew.WB:count 100051870 # cumulative count of insts written-back +system.cpu.iew.WB:fanout 0.721943 # average fanout of values written-back system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.iew.WB:producers 66001783 # num instructions producing a value -system.cpu.iew.WB:rate 1.229960 # insts written-back per cycle -system.cpu.iew.WB:sent 100960101 # cumulative count of insts sent to commit -system.cpu.iew.branchMispredicts 2058583 # Number of branch mispredicts detected at execute -system.cpu.iew.iewBlockCycles 308073 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 33906754 # Number of dispatched load instructions -system.cpu.iew.iewDispNonSpecInsts 436 # Number of dispatched non-speculative instructions -system.cpu.iew.iewDispSquashedInsts 1495766 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispStoreInsts 10659940 # Number of dispatched store instructions -system.cpu.iew.iewDispatchedInsts 148159865 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 24639012 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2167407 # Number of squashed instructions skipped in execute -system.cpu.iew.iewExecutedInsts 101917357 # Number of executed instructions -system.cpu.iew.iewIQFullEvents 147057 # Number of times the IQ has become full, causing a stall +system.cpu.iew.WB:producers 65982976 # num instructions producing a value +system.cpu.iew.WB:rate 1.231210 # insts written-back per cycle +system.cpu.iew.WB:sent 100889956 # cumulative count of insts sent to commit +system.cpu.iew.branchMispredicts 2057434 # Number of branch mispredicts detected at execute +system.cpu.iew.iewBlockCycles 253528 # Number of cycles IEW is blocking +system.cpu.iew.iewDispLoadInsts 33850050 # Number of dispatched load instructions +system.cpu.iew.iewDispNonSpecInsts 434 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispSquashedInsts 1485832 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispStoreInsts 10655807 # Number of dispatched store instructions +system.cpu.iew.iewDispatchedInsts 148273965 # Number of instructions dispatched to IQ +system.cpu.iew.iewExecLoadInsts 24565353 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2165750 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 101849758 # Number of executed instructions +system.cpu.iew.iewIQFullEvents 124164 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewLSQFullEvents 229 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.iewSquashCycles 8093015 # Number of cycles IEW is squashing -system.cpu.iew.iewUnblockCycles 184742 # Number of cycles IEW is unblocking +system.cpu.iew.iewLSQFullEvents 47 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewSquashCycles 8131535 # Number of cycles IEW is squashing +system.cpu.iew.iewUnblockCycles 157443 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread.0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread.0.forwLoads 837974 # Number of loads that had data forwarded from stores -system.cpu.iew.lsq.thread.0.ignoredResponses 2531 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread.0.forwLoads 842082 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread.0.ignoredResponses 2486 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address -system.cpu.iew.lsq.thread.0.memOrderViolation 262379 # Number of memory ordering violations -system.cpu.iew.lsq.thread.0.rescheduledLoads 9827 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 13872341 # Number of loads squashed -system.cpu.iew.lsq.thread.0.squashedStores 4157245 # Number of stores squashed -system.cpu.iew.memOrderViolationEvents 262379 # Number of memory order violations -system.cpu.iew.predictedNotTakenIncorrect 456408 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.predictedTakenIncorrect 1602175 # Number of branches that were predicted taken incorrectly -system.cpu.ipc 1.034117 # IPC: Instructions Per Cycle -system.cpu.ipc_total 1.034117 # IPC: Total IPC of All Threads +system.cpu.iew.lsq.thread.0.memOrderViolation 268955 # Number of memory ordering violations +system.cpu.iew.lsq.thread.0.rescheduledLoads 9838 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread.0.squashedLoads 13853852 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedStores 4154704 # Number of stores squashed +system.cpu.iew.memOrderViolationEvents 268955 # Number of memory order violations +system.cpu.iew.predictedNotTakenIncorrect 456787 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.predictedTakenIncorrect 1600647 # Number of branches that were predicted taken incorrectly +system.cpu.ipc 1.035892 # IPC: Instructions Per Cycle +system.cpu.ipc_total 1.035892 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 7 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 64580956 62.05% 62.05% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 474234 0.46% 62.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.50% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2786797 2.68% 65.18% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114549 0.11% 65.29% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2387018 2.29% 67.58% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 305140 0.29% 67.88% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 754986 0.73% 68.60% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 323 0.00% 68.60% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 25334340 24.34% 92.94% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemWrite 7346414 7.06% 100.00% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 64603279 62.11% 62.11% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 474408 0.46% 62.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 62.57% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 2788350 2.68% 65.25% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 114559 0.11% 65.36% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 2389553 2.30% 67.65% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 305056 0.29% 67.95% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 755116 0.73% 68.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 324 0.00% 68.67% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 25265594 24.29% 92.96% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemWrite 7319262 7.04% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::total 104084764 # Type of FU issued -system.cpu.iq.ISSUE:fu_busy_cnt 1605421 # FU busy when requested -system.cpu.iq.ISSUE:fu_busy_rate 0.015424 # FU busy rate (busy events/executed inst) +system.cpu.iq.ISSUE:FU_type_0::total 104015508 # Type of FU issued +system.cpu.iq.ISSUE:fu_busy_cnt 1951419 # FU busy when requested +system.cpu.iq.ISSUE:fu_busy_rate 0.018761 # FU busy rate (busy events/executed inst) system.cpu.iq.ISSUE:fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntAlu 233590 14.55% 14.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 14.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 14.55% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatAdd 339 0.02% 14.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 14.57% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatCvt 3702 0.23% 14.80% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatMult 2371 0.15% 14.95% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatDiv 538253 33.53% 48.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 48.48% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemRead 750644 46.76% 95.23% # attempts to use FU when none available -system.cpu.iq.ISSUE:fu_full::MemWrite 76522 4.77% 100.00% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntAlu 264504 13.55% 13.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntMult 0 0.00% 13.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::IntDiv 0 0.00% 13.55% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatAdd 67 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCmp 0 0.00% 13.56% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatCvt 1979 0.10% 13.66% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatMult 2355 0.12% 13.78% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatDiv 826053 42.33% 56.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::FloatSqrt 0 0.00% 56.11% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemRead 733480 37.59% 93.70% # attempts to use FU when none available +system.cpu.iq.ISSUE:fu_full::MemWrite 122981 6.30% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.ISSUE:fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.ISSUE:issued_per_cycle::samples 81293586 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::mean 1.280356 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.539590 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::samples 81154458 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::mean 1.281698 # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::stdev 1.540203 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::0 34992440 43.04% 43.04% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::1 18916491 23.27% 66.31% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::2 11753286 14.46% 80.77% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::3 6613191 8.13% 88.91% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::4 5113111 6.29% 95.20% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::5 2406044 2.96% 98.16% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::6 1201508 1.48% 99.63% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::7 249704 0.31% 99.94% # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::8 47811 0.06% 100.00% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::0 34964609 43.08% 43.08% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::1 18826048 23.20% 66.28% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::2 11595868 14.29% 80.57% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::3 6807186 8.39% 88.96% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::4 5054639 6.23% 95.19% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::5 2409288 2.97% 98.16% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::6 1203500 1.48% 99.64% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::7 256390 0.32% 99.95% # Number of insts issued each cycle +system.cpu.iq.ISSUE:issued_per_cycle::8 36930 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.ISSUE:issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.ISSUE:issued_per_cycle::total 81293586 # Number of insts issued each cycle -system.cpu.iq.ISSUE:rate 1.278644 # Inst issue rate -system.cpu.iq.iqInstsAdded 135407278 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqInstsIssued 104084764 # Number of instructions issued -system.cpu.iq.iqNonSpecInstsAdded 436 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqSquashedInstsExamined 50574577 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedInstsIssued 302079 # Number of squashed instructions issued -system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed -system.cpu.iq.iqSquashedOperandsExamined 47259225 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.ISSUE:issued_per_cycle::total 81154458 # Number of insts issued each cycle +system.cpu.iq.ISSUE:rate 1.279986 # Inst issue rate +system.cpu.iq.iqInstsAdded 135471680 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsIssued 104015508 # Number of instructions issued +system.cpu.iq.iqNonSpecInstsAdded 434 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqSquashedInstsExamined 50629869 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedInstsIssued 304728 # Number of squashed instructions issued +system.cpu.iq.iqSquashedNonSpecRemoved 45 # Number of squashed non-spec instructions that were removed +system.cpu.iq.iqSquashedOperandsExamined 47460542 # Number of squashed operands that are examined and possibly removed from graph system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 19042455 # ITB accesses +system.cpu.itb.fetch_accesses 19059519 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 19042384 # ITB hits -system.cpu.itb.fetch_misses 71 # ITB misses +system.cpu.itb.fetch_hits 19059447 # ITB hits +system.cpu.itb.fetch_misses 72 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -343,97 +343,97 @@ system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 1732 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 34699.413490 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31528.152493 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_accesses 1733 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 34492.672919 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31439.624853 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 27 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 59162500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.984411 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 1705 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 53755500 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984411 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 1705 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 10664 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 34281.213192 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.566549 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 7268 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 116419000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.318455 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3396 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 105553000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.318455 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3396 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadExReq_miss_latency 58844500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.984420 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 1706 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 53636000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.984420 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 1706 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10647 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 34284.558824 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31082.500000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7247 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 116567500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.319339 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 105680500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.319339 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3400 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 109 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 109 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 2.100462 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.091984 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 12396 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 34420.995883 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 7295 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 175581500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.411504 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 5101 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12380 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 34354.093224 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7274 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 175412000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.412439 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 5106 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 159308500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.411504 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 5101 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 159316500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.412439 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 5106 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.070268 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000537 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2302.534301 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.609654 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 12396 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 34420.995883 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.837091 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.070256 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000538 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2302.164021 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.613547 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12380 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 34354.093224 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 31201.821387 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 7295 # number of overall hits -system.cpu.l2cache.overall_miss_latency 175581500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.411504 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 5101 # number of overall misses +system.cpu.l2cache.overall_hits 7274 # number of overall hits +system.cpu.l2cache.overall_miss_latency 175412000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.412439 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 5106 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 159308500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.411504 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 5101 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 159316500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.412439 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 5106 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3464 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3468 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2320.143954 # Cycle average of tags in use -system.cpu.l2cache.total_refs 7276 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2319.777568 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7255 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.memDep0.conflictingLoads 17616969 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 5053323 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 33906754 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 10659940 # Number of stores inserted to the mem dependence unit. -system.cpu.numCycles 81402475 # number of cpu cycles simulated -system.cpu.rename.RENAME:BlockCycles 1958550 # Number of cycles rename is blocking +system.cpu.memDep0.conflictingLoads 17824866 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 5359806 # Number of conflicting stores. +system.cpu.memDep0.insertedLoads 33850050 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 10655807 # Number of stores inserted to the mem dependence unit. +system.cpu.numCycles 81263024 # number of cpu cycles simulated +system.cpu.rename.RENAME:BlockCycles 1835260 # Number of cycles rename is blocking system.cpu.rename.RENAME:CommittedMaps 68427361 # Number of HB maps that are committed -system.cpu.rename.RENAME:IQFullEvents 1204707 # Number of times rename has blocked due to IQ full -system.cpu.rename.RENAME:IdleCycles 40603552 # Number of cycles rename is idle -system.cpu.rename.RENAME:LSQFullEvents 943829 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RENAME:RenameLookups 202471233 # Number of register rename lookups that rename has made -system.cpu.rename.RENAME:RenamedInsts 157096154 # Number of instructions processed by rename -system.cpu.rename.RENAME:RenamedOperands 115391431 # Number of destination operands rename has renamed -system.cpu.rename.RENAME:RunCycles 28385991 # Number of cycles rename is running -system.cpu.rename.RENAME:SquashCycles 8093015 # Number of cycles rename is squashing -system.cpu.rename.RENAME:UnblockCycles 2247276 # Number of cycles rename is unblocking -system.cpu.rename.RENAME:UndoneMaps 46964070 # Number of HB maps that are undone due to squashing -system.cpu.rename.RENAME:serializeStallCycles 5202 # count of cycles rename stalled for serializing inst -system.cpu.rename.RENAME:serializingInsts 471 # count of serializing insts renamed -system.cpu.rename.RENAME:skidInsts 4950569 # count of insts added to the skid buffer -system.cpu.rename.RENAME:tempSerializingInsts 460 # count of temporary serializing insts renamed -system.cpu.timesIdled 2416 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.rename.RENAME:IQFullEvents 1124456 # Number of times rename has blocked due to IQ full +system.cpu.rename.RENAME:IdleCycles 40588679 # Number of cycles rename is idle +system.cpu.rename.RENAME:LSQFullEvents 939622 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RENAME:RenameLookups 202646679 # Number of register rename lookups that rename has made +system.cpu.rename.RENAME:RenamedInsts 157276395 # Number of instructions processed by rename +system.cpu.rename.RENAME:RenamedOperands 115514667 # Number of destination operands rename has renamed +system.cpu.rename.RENAME:RunCycles 28432140 # Number of cycles rename is running +system.cpu.rename.RENAME:SquashCycles 8131535 # Number of cycles rename is squashing +system.cpu.rename.RENAME:UnblockCycles 2161646 # Number of cycles rename is unblocking +system.cpu.rename.RENAME:UndoneMaps 47087306 # Number of HB maps that are undone due to squashing +system.cpu.rename.RENAME:serializeStallCycles 5198 # count of cycles rename stalled for serializing inst +system.cpu.rename.RENAME:serializingInsts 467 # count of serializing insts renamed +system.cpu.rename.RENAME:skidInsts 4785663 # count of insts added to the skid buffer +system.cpu.rename.RENAME:tempSerializingInsts 456 # count of temporary serializing insts renamed +system.cpu.timesIdled 2403 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_binaries/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,2 +1,5 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) +For more information see: http://www.m5sim.org/warn/5c5b547f +hack: be nice to actually delete the event here diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:01:12 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:32:41 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -26,4 +28,4 @@ 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 \ No newline at end of file +122 123 124 Exiting @ tick 45951567500 because target called exit() diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1794306 # Simulator instruction rate (inst/s) -host_mem_usage 187928 # Number of bytes of host memory used -host_seconds 51.22 # Real time elapsed on the host -host_tick_rate 897149357 # Simulator tick rate (ticks/s) +host_inst_rate 4196549 # Simulator instruction rate (inst/s) +host_mem_usage 235848 # Number of bytes of host memory used +host_seconds 21.90 # Real time elapsed on the host +host_tick_rate 2098254960 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.045952 # Number of seconds simulated @@ -44,7 +44,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 91903136 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26537141 # Number of memory references +system.cpu.num_refs 26497334 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -152,12 +152,12 @@ [system.cpu.workload] type=LiveProcess cmd=twolf smred -cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +cwd=build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing egid=100 env= errout=cerr euid=100 -executable=/home/stever/m5/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:49 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:04:52 -M5 executing on phenom -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:35:14 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/simple-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt --- a/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/long/70.twolf/ref/alpha/tru64/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1097596 # Simulator instruction rate (inst/s) -host_mem_usage 196804 # Number of bytes of host memory used -host_seconds 83.73 # Real time elapsed on the host -host_tick_rate 1418103765 # Simulator tick rate (ticks/s) +host_inst_rate 2386222 # Simulator instruction rate (inst/s) +host_mem_usage 243572 # Number of bytes of host memory used +host_seconds 38.51 # Real time elapsed on the host +host_tick_rate 3083013039 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 91903056 # Number of instructions simulated sim_seconds 0.118740 # Number of seconds simulated @@ -233,7 +233,7 @@ system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles system.cpu.numCycles 237480098 # number of cpu cycles simulated system.cpu.num_insts 91903056 # Number of instructions executed -system.cpu.num_refs 26537141 # Number of memory references +system.cpu.num_refs 26497334 # Number of memory references system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -358,7 +358,7 @@ env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/linux/o3-timing/simout --- a/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/linux/o3-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,5 +1,5 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing/simerr +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +7,11 @@ All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:04 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 22:53:27 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/tru64/o3-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 34398 # Simulator instruction rate (inst/s) -host_mem_usage 203876 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host -host_tick_rate 104794717 # Simulator tick rate (ticks/s) +host_inst_rate 101462 # Simulator instruction rate (inst/s) +host_mem_usage 236800 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +host_tick_rate 307213198 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2387 # Number of instructions simulated sim_seconds 0.000007 # Number of seconds simulated @@ -228,7 +228,7 @@ system.cpu.iew.EXEC:branches 601 # Number of branches executed system.cpu.iew.EXEC:nop 306 # number of nop insts executed system.cpu.iew.EXEC:rate 0.241079 # Inst execution rate -system.cpu.iew.EXEC:refs 1019 # number of memory reference insts executed +system.cpu.iew.EXEC:refs 1017 # number of memory reference insts executed system.cpu.iew.EXEC:stores 368 # Number of stores executed system.cpu.iew.EXEC:swp 0 # number of swp insts executed system.cpu.iew.WB:consumers 1981 # num instructions consuming a value @@ -241,12 +241,12 @@ system.cpu.iew.WB:sent 3452 # cumulative count of insts sent to commit system.cpu.iew.branchMispredicts 164 # Number of branch mispredicts detected at execute system.cpu.iew.iewBlockCycles 55 # Number of cycles IEW is blocking -system.cpu.iew.iewDispLoadInsts 795 # Number of dispatched load instructions +system.cpu.iew.iewDispLoadInsts 793 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 68 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 435 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 4588 # Number of instructions dispatched to IQ -system.cpu.iew.iewExecLoadInsts 651 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts 649 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 3520 # Number of executed instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall @@ -262,7 +262,7 @@ system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread.0.memOrderViolation 13 # Number of memory ordering violations system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread.0.squashedLoads 380 # Number of loads squashed +system.cpu.iew.lsq.thread.0.squashedLoads 378 # Number of loads squashed system.cpu.iew.lsq.thread.0.squashedStores 141 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 13 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 109 # Number of branches that were predicted not taken incorrectly @@ -270,16 +270,16 @@ system.cpu.ipc 0.163482 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.163482 # IPC: Total IPC of All Threads system.cpu.iq.ISSUE:FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntAlu 2582 71.11% 71.11% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.14% # Type of FU issued -system.cpu.iq.ISSUE:FU_type_0::MemRead 675 18.59% 89.73% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntAlu 2584 71.16% 71.16% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntMult 1 0.03% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::IntDiv 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatAdd 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCmp 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatCvt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatMult 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatDiv 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::FloatSqrt 0 0.00% 71.19% # Type of FU issued +system.cpu.iq.ISSUE:FU_type_0::MemRead 673 18.53% 89.73% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::MemWrite 373 10.27% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.ISSUE:FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued @@ -406,7 +406,7 @@ system.cpu.l2cache.writebacks 0 # number of writebacks system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 16 # Number of conflicting stores. -system.cpu.memDep0.insertedLoads 795 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedLoads 793 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 435 # Number of stores inserted to the mem dependence unit. system.cpu.numCycles 14601 # number of cpu cycles simulated system.cpu.rename.RENAME:BlockCycles 63 # Number of cycles rename is blocking diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -57,7 +57,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/chips/pd/randd/dist/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:37:14 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:32:40 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/tru64/simple-atomic Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 794145 # Simulator instruction rate (inst/s) -host_mem_usage 181656 # Number of bytes of host memory used +host_inst_rate 759729 # Simulator instruction rate (inst/s) +host_mem_usage 228516 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 371138444 # Simulator tick rate (ticks/s) +host_tick_rate 362937063 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -265,7 +265,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -285,7 +285,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -411,7 +411,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,14 +7,13 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:04:53 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:09:56 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2584495 # Simulator instruction rate (inst/s) -host_mem_usage 281712 # Number of bytes of host memory used -host_seconds 24.44 # Real time elapsed on the host -host_tick_rate 76540345609 # Simulator tick rate (ticks/s) +host_inst_rate 4418519 # Simulator instruction rate (inst/s) +host_mem_usage 326752 # Number of bytes of host memory used +host_seconds 14.29 # Real time elapsed on the host +host_tick_rate 130854140423 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 63154034 # Number of instructions simulated sim_seconds 1.870336 # Number of seconds simulated @@ -306,7 +306,7 @@ system.cpu0.not_idle_fraction 0.015300 # Percentage of non-idle cycles system.cpu0.numCycles 3740670933 # number of cpu cycles simulated system.cpu0.num_insts 57222076 # Number of instructions executed -system.cpu0.num_refs 15330887 # Number of memory references +system.cpu0.num_refs 15135515 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits @@ -588,7 +588,7 @@ system.cpu1.not_idle_fraction 0.001587 # Percentage of non-idle cycles system.cpu1.numCycles 3740248881 # number of cpu cycles simulated system.cpu1.num_insts 5931958 # Number of instructions executed -system.cpu1.num_refs 1926645 # Number of memory references +system.cpu1.num_refs 1926244 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -158,7 +158,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -178,7 +178,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -304,7 +304,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,12 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:04:53 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:09:41 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 2709831 # Simulator instruction rate (inst/s) -host_mem_usage 280300 # Number of bytes of host memory used -host_seconds 22.16 # Real time elapsed on the host -host_tick_rate 82566195794 # Simulator tick rate (ticks/s) +host_inst_rate 4413707 # Simulator instruction rate (inst/s) +host_mem_usage 325356 # Number of bytes of host memory used +host_seconds 13.60 # Real time elapsed on the host +host_tick_rate 134480396261 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 60038305 # Number of instructions simulated sim_seconds 1.829332 # Number of seconds simulated @@ -298,7 +298,7 @@ system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles system.cpu.numCycles 3658664408 # number of cpu cycles simulated system.cpu.num_insts 60038305 # Number of instructions executed -system.cpu.num_refs 16311238 # Number of memory references +system.cpu.num_refs 16115709 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -259,7 +259,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -279,7 +279,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -405,7 +405,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,14 +7,13 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:16:21 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:10:42 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 562628000 Exiting @ tick 1958647095000 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1372828 # Simulator instruction rate (inst/s) -host_mem_usage 278528 # Number of bytes of host memory used -host_seconds 43.24 # Real time elapsed on the host -host_tick_rate 45301058959 # Simulator tick rate (ticks/s) +host_inst_rate 1781653 # Simulator instruction rate (inst/s) +host_mem_usage 323564 # Number of bytes of host memory used +host_seconds 33.32 # Real time elapsed on the host +host_tick_rate 58791386546 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 59355643 # Number of instructions simulated sim_seconds 1.958647 # Number of seconds simulated @@ -361,7 +361,7 @@ system.cpu0.not_idle_fraction 0.060263 # Percentage of non-idle cycles system.cpu0.numCycles 3916023774 # number of cpu cycles simulated system.cpu0.num_insts 54072652 # Number of instructions executed -system.cpu0.num_refs 14919880 # Number of memory references +system.cpu0.num_refs 14724357 # Number of memory references system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency @@ -692,7 +692,7 @@ system.cpu1.not_idle_fraction 0.004865 # Percentage of non-idle cycles system.cpu1.numCycles 3917294190 # number of cpu cycles simulated system.cpu1.num_insts 5282991 # Number of instructions executed -system.cpu1.num_refs 1711037 # Number of memory references +system.cpu1.num_refs 1710778 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -8,12 +8,12 @@ children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/home/stever/m5/m5_system_2.0b3/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=timing -pal=/home/stever/m5/m5_system_2.0b3/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -155,7 +155,7 @@ [system.disk0.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.disk2] @@ -175,7 +175,7 @@ [system.disk2.image.child] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -301,7 +301,7 @@ [system.simple_disk.disk] type=RawDiskImage -image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [system.terminal] diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,12 @@ All Rights Reserved -M5 compiled Sep 20 2010 15:04:50 -M5 revision 0c4a7d867247 7686 default qtip print-identical tip -M5 started Sep 20 2010 15:15:41 -M5 executing on phenom -command line: build/ALPHA_FS/m5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:10:12 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/m5_system_2.0b3/binaries/vmlinux - 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1915548867000 because m5_exit instruction encountered diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 1445061 # Simulator instruction rate (inst/s) -host_mem_usage 277124 # Number of bytes of host memory used -host_seconds 38.85 # Real time elapsed on the host -host_tick_rate 49309117653 # Simulator tick rate (ticks/s) +host_inst_rate 1917155 # Simulator instruction rate (inst/s) +host_mem_usage 322176 # Number of bytes of host memory used +host_seconds 29.28 # Real time elapsed on the host +host_tick_rate 65417896896 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 56137087 # Number of instructions simulated sim_seconds 1.915549 # Number of seconds simulated @@ -342,7 +342,7 @@ system.cpu.not_idle_fraction 0.063469 # Percentage of non-idle cycles system.cpu.numCycles 3831097734 # number of cpu cycles simulated system.cpu.num_insts 56137087 # Number of instructions executed -system.cpu.num_refs 15658046 # Number of memory references +system.cpu.num_refs 15462519 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,5 +1,9 @@ -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here - -gzip: stdout: Broken pipe +Traceback (most recent call last): + File "", line 1, in + File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main + exec filecode in scope + File "tests/run.py", line 78, in + execfile(joinpath(tests_root, category, name, 'test.py')) + File "tests/quick/20.eio-short/test.py", line 29, in + root.system.cpu.workload = EioProcess(file = binpath('anagram', +NameError: name 'EioProcess' is not defined diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,8 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 03:02:04 -M5 executing on SC2B0619 +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:33:04 +M5 executing on aus-bc2-b15 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-atomic -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 250015500 because a thread reached the max instruction count diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,50 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3013906 # Simulator instruction rate (inst/s) -host_mem_usage 181592 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host -host_tick_rate 1504585693 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 500032 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 500019 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 500032 # number of cpu cycles simulated -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 182222 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,5 +1,9 @@ -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here - -gzip: stdout: Broken pipe +Traceback (most recent call last): + File "", line 1, in + File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main + exec filecode in scope + File "tests/run.py", line 78, in + execfile(joinpath(tests_root, category, name, 'test.py')) + File "tests/quick/20.eio-short/test.py", line 29, in + root.system.cpu.workload = EioProcess(file = binpath('anagram', +NameError: name 'EioProcess' is not defined diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,8 @@ All Rights Reserved -M5 compiled Aug 26 2010 19:15:13 -M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix -M5 started Aug 26 2010 19:20:56 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/20.eio-short/alpha/eio/simple-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -49508 bytes wasted ->Exiting @ tick 727929000 because a thread reached the max instruction count +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:31:02 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/20.eio-short/alpha/eio/simple-timing diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt --- a/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/20.eio-short/ref/alpha/eio/simple-timing/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,233 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1184343 # Simulator instruction rate (inst/s) -host_mem_usage 203180 # Number of bytes of host memory used -host_seconds 0.42 # Real time elapsed on the host -host_tick_rate 1723169900 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 500001 # Number of instructions simulated -sim_seconds 0.000728 # Number of seconds simulated -sim_ticks 727929000 # Number of ticks simulated -system.cpu.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 124120 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 17640000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002531 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 315 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 16695000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate 0.002531 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_misses 315 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7784000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7367000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses -system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 397.182819 # Average number of references to valid blocks. -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.demand_hits 180321 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 25424000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.002511 # miss rate for demand accesses -system.cpu.dcache.demand_misses 454 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 24062000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_rate 0.002511 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_misses 454 # number of demand (read+write) MSHR misses -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.070111 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 287.175167 # Average occupied blocks per context -system.cpu.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 180321 # number of overall hits -system.cpu.dcache.overall_miss_latency 25424000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.002511 # miss rate for overall accesses -system.cpu.dcache.overall_misses 454 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 24062000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_rate 0.002511 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_misses 454 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.sampled_refs 454 # Sample count of references to valid blocks. -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 287.175167 # Cycle average of tags in use -system.cpu.dcache.total_refs 180321 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 0 # number of writebacks -system.cpu.dtb.data_accesses 180793 # DTB accesses -system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_hits 180775 # DTB hits -system.cpu.dtb.data_misses 18 # DTB misses -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.read_accesses 124443 # DTB read accesses -system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_hits 124435 # DTB read hits -system.cpu.dtb.read_misses 8 # DTB read misses -system.cpu.dtb.write_accesses 56350 # DTB write accesses -system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_hits 56340 # DTB write hits -system.cpu.dtb.write_misses 10 # DTB write misses -system.cpu.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 499617 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 22568000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000806 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 403 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 21359000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000806 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 403 # number of ReadReq MSHR misses -system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1239.744417 # Average number of references to valid blocks. -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.demand_hits 499617 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 22568000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000806 # miss rate for demand accesses -system.cpu.icache.demand_misses 403 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 21359000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000806 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 403 # number of demand (read+write) MSHR misses -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.129371 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 264.952126 # Average occupied blocks per context -system.cpu.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 499617 # number of overall hits -system.cpu.icache.overall_miss_latency 22568000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000806 # miss rate for overall accesses -system.cpu.icache.overall_misses 403 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 21359000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000806 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 403 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 403 # Sample count of references to valid blocks. -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 264.952126 # Cycle average of tags in use -system.cpu.icache.total_refs 499617 # Total number of references to valid blocks. -system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idle_fraction 0 # Percentage of idle cycles -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 500033 # ITB accesses -system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 500020 # ITB hits -system.cpu.itb.fetch_misses 13 # ITB misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 139 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 7228000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 139 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5560000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 139 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 718 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_miss_latency 37336000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 718 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 28720000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 718 # number of ReadReq MSHR misses -system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 857 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 44564000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 857 # number of demand (read+write) misses -system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 34280000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 857 # number of demand (read+write) MSHR misses -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.014692 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 481.419470 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 857 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 0 # number of overall hits -system.cpu.l2cache.overall_miss_latency 44564000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 857 # number of overall misses -system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 34280000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 857 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 718 # Sample count of references to valid blocks. -system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 481.419470 # Cycle average of tags in use -system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 1455858 # number of cpu cycles simulated -system.cpu.num_insts 500001 # Number of instructions executed -system.cpu.num_refs 182222 # Number of memory references -system.cpu.workload.PROG:num_syscalls 18 # Number of system calls - ----------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,11 +1,9 @@ -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe +Traceback (most recent call last): + File "", line 1, in + File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main + exec filecode in scope + File "tests/run.py", line 78, in + execfile(joinpath(tests_root, category, name, 'test.py')) + File "tests/quick/30.eio-mp/test.py", line 29, in + process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) +NameError: name 'EioProcess' is not defined diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,19 +7,8 @@ All Rights Reserved -M5 compiled Aug 26 2010 19:15:13 -M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix -M5 started Aug 26 2010 19:20:56 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-atomic-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 250015500 because a thread reached the max instruction count +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:31:02 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-atomic-mp diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,712 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 3552670 # Simulator instruction rate (inst/s) -host_mem_usage 1128260 # Number of bytes of host memory used -host_seconds 0.56 # Real time elapsed on the host -host_tick_rate 443935332 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 2000004 # Number of instructions simulated -sim_seconds 0.000250 # Number of seconds simulated -sim_ticks 250015500 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180312 # number of overall hits -system.cpu0.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 463 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.425950 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 218.086151 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 499556 # number of overall hits -system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_misses 463 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu0.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 500032 # ITB accesses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_hits 500019 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 500032 # number of cpu cycles simulated -system.cpu0.num_insts 500001 # Number of instructions executed -system.cpu0.num_refs 182222 # Number of memory references -system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180312 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180312 # number of overall hits -system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 463 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.data_accesses 180793 # DTB accesses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_hits 180775 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.write_accesses 56350 # DTB write accesses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_hits 56340 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.425950 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 218.086151 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499556 # number of overall hits -system.cpu1.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_misses 463 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu1.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 500032 # ITB accesses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_hits 500019 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.numCycles 500032 # number of cpu cycles simulated -system.cpu1.num_insts 500001 # Number of instructions executed -system.cpu1.num_refs 182222 # Number of memory references -system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180312 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180312 # number of overall hits -system.cpu2.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 463 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.data_accesses 180793 # DTB accesses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_hits 180775 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.read_accesses 124443 # DTB read accesses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124435 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.write_accesses 56350 # DTB write accesses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_hits 56340 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.425950 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 218.086151 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499556 # number of overall hits -system.cpu2.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_misses 463 # number of overall misses -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu2.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.fetch_accesses 500032 # ITB accesses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_hits 500019 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 500032 # number of cpu cycles simulated -system.cpu2.num_insts 500001 # Number of instructions executed -system.cpu2.num_refs 182222 # Number of memory references -system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu3.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180312 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.540766 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 276.872320 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180312 # number of overall hits -system.cpu3.dcache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 463 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 276.872320 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.data_accesses 180793 # DTB accesses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_hits 180775 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.read_accesses 124443 # DTB read accesses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124435 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.write_accesses 56350 # DTB write accesses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_hits 56340 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 500019 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_hits 499556 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.954644 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 500019 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.demand_hits 499556 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.425950 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 218.086151 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 500019 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 0 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499556 # number of overall hits -system.cpu3.icache.overall_miss_latency 0 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_misses 463 # number of overall misses -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 0 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 218.086151 # Cycle average of tags in use -system.cpu3.icache.total_refs 499556 # Total number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.fetch_accesses 500032 # ITB accesses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_hits 500019 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.numCycles 500032 # number of cpu cycles simulated -system.cpu3.num_insts 500001 # Number of instructions executed -system.cpu3.num_refs 182222 # Number of memory references -system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_hits::0 69 # number of ReadReq hits -system.l2c.ReadReq_hits::1 69 # number of ReadReq hits -system.l2c.ReadReq_hits::2 69 # number of ReadReq hits -system.l2c.ReadReq_hits::3 69 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits -system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 718 # number of ReadReq misses -system.l2c.ReadReq_misses::1 718 # number of ReadReq misses -system.l2c.ReadReq_misses::2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::3 718 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 116 # number of Writeback hits -system.l2c.Writeback_hits::total 116 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 0 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.demand_hits::0 69 # number of demand (read+write) hits -system.l2c.demand_hits::1 69 # number of demand (read+write) hits -system.l2c.demand_hits::2 69 # number of demand (read+write) hits -system.l2c.demand_hits::3 69 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses -system.l2c.demand_misses::0 857 # number of demand (read+write) misses -system.l2c.demand_misses::1 857 # number of demand (read+write) misses -system.l2c.demand_misses::2 857 # number of demand (read+write) misses -system.l2c.demand_misses::3 857 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.007421 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000267 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 486.328367 # Average occupied blocks per context -system.l2c.occ_blocks::1 486.328367 # Average occupied blocks per context -system.l2c.occ_blocks::2 486.328367 # Average occupied blocks per context -system.l2c.occ_blocks::3 486.328367 # Average occupied blocks per context -system.l2c.occ_blocks::4 17.466765 # Average occupied blocks per context -system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 0 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 69 # number of overall hits -system.l2c.overall_hits::1 69 # number of overall hits -system.l2c.overall_hits::2 69 # number of overall hits -system.l2c.overall_hits::3 69 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.overall_miss_latency 0 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses -system.l2c.overall_misses::0 857 # number of overall misses -system.l2c.overall_misses::1 857 # number of overall misses -system.l2c.overall_misses::2 857 # number of overall misses -system.l2c.overall_misses::3 857 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 0 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1962.780232 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks - ----------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr Wed Nov 03 18:14:20 2010 -0500 @@ -1,11 +1,9 @@ -warn: Sockets disabled, not accepting gdb connections -For more information see: http://www.m5sim.org/warn/d946bea6 -hack: be nice to actually delete the event here - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe - -gzip: stdout: Broken pipe +Traceback (most recent call last): + File "", line 1, in + File "/arm/scratch/alisai01/m5/src/python/m5/main.py", line 359, in main + exec filecode in scope + File "tests/run.py", line 78, in + execfile(joinpath(tests_root, category, name, 'test.py')) + File "tests/quick/30.eio-mp/test.py", line 29, in + process = EioProcess(file = binpath('anagram', 'anagram-vshort.eio.gz')) +NameError: name 'EioProcess' is not defined diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,19 +7,8 @@ All Rights Reserved -M5 compiled Aug 26 2010 19:15:13 -M5 revision 85cafc6ccb42+ 7662+ default qtip tip sc-fail-fix -M5 started Aug 26 2010 19:20:56 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/opt/quick/30.eio-mp/alpha/eio/simple-timing-mp -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -main dictionary has 1245 entries -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted -49508 bytes wasted ->>>>Exiting @ tick 728920000 because a thread reached the max instruction count +M5 compiled Nov 2 2010 21:30:55 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 21:33:05 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA_SE/tests/fast/quick/30.eio-mp/alpha/eio/simple-timing-mp diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt --- a/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/30.eio-mp/ref/alpha/eio/simple-timing-mp/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -1,812 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -host_inst_rate 1077320 # Simulator instruction rate (inst/s) -host_mem_usage 210756 # Number of bytes of host memory used -host_seconds 1.86 # Real time elapsed on the host -host_tick_rate 392590905 # Simulator tick rate (ticks/s) -sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 1999954 # Number of instructions simulated -sim_seconds 0.000729 # Number of seconds simulated -sim_ticks 728920000 # Number of ticks simulated -system.cpu0.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu0.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu0.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_accesses 56340 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_avg_miss_latency 56064.748201 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53064.748201 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_hits 56201 # number of WriteReq hits -system.cpu0.dcache.WriteReq_miss_latency 7793000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu0.dcache.WriteReq_mshr_miss_latency 7376000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses -system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.dcache.avg_refs 389.442765 # Average number of references to valid blocks. -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.demand_accesses 180775 # number of demand (read+write) accesses -system.cpu0.dcache.demand_avg_miss_latency 55244.060475 # average overall miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency -system.cpu0.dcache.demand_hits 180312 # number of demand (read+write) hits -system.cpu0.dcache.demand_miss_latency 25578000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu0.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_miss_latency 24189000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.occ_%::0 0.534216 # Average percentage of cache occupancy -system.cpu0.dcache.occ_blocks::0 273.518805 # Average occupied blocks per context -system.cpu0.dcache.overall_accesses 180775 # number of overall (read+write) accesses -system.cpu0.dcache.overall_avg_miss_latency 55244.060475 # average overall miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency 52244.060475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.dcache.overall_hits 180312 # number of overall hits -system.cpu0.dcache.overall_miss_latency 25578000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu0.dcache.overall_misses 463 # number of overall misses -system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_miss_latency 24189000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.dcache.replacements 61 # number of replacements -system.cpu0.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.dcache.tagsinuse 273.518805 # Cycle average of tags in use -system.cpu0.dcache.total_refs 180312 # Total number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.writebacks 29 # number of writebacks -system.cpu0.dtb.data_accesses 180793 # DTB accesses -system.cpu0.dtb.data_acv 0 # DTB access violations -system.cpu0.dtb.data_hits 180775 # DTB hits -system.cpu0.dtb.data_misses 18 # DTB misses -system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.fetch_acv 0 # ITB acv -system.cpu0.dtb.fetch_hits 0 # ITB hits -system.cpu0.dtb.fetch_misses 0 # ITB misses -system.cpu0.dtb.read_accesses 124443 # DTB read accesses -system.cpu0.dtb.read_acv 0 # DTB read access violations -system.cpu0.dtb.read_hits 124435 # DTB read hits -system.cpu0.dtb.read_misses 8 # DTB read misses -system.cpu0.dtb.write_accesses 56350 # DTB write accesses -system.cpu0.dtb.write_acv 0 # DTB write access violations -system.cpu0.dtb.write_hits 56340 # DTB write hits -system.cpu0.dtb.write_misses 10 # DTB write misses -system.cpu0.icache.ReadReq_accesses 500020 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_avg_miss_latency 50699.784017 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency 47699.784017 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_hits 499557 # number of ReadReq hits -system.cpu0.icache.ReadReq_miss_latency 23474000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu0.icache.ReadReq_mshr_miss_latency 22085000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.icache.avg_refs 1078.956803 # Average number of references to valid blocks. -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.demand_accesses 500020 # number of demand (read+write) accesses -system.cpu0.icache.demand_avg_miss_latency 50699.784017 # average overall miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency -system.cpu0.icache.demand_hits 499557 # number of demand (read+write) hits -system.cpu0.icache.demand_miss_latency 23474000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu0.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_miss_latency 22085000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.occ_%::0 0.422639 # Average percentage of cache occupancy -system.cpu0.icache.occ_blocks::0 216.390931 # Average occupied blocks per context -system.cpu0.icache.overall_accesses 500020 # number of overall (read+write) accesses -system.cpu0.icache.overall_avg_miss_latency 50699.784017 # average overall miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency 47699.784017 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu0.icache.overall_hits 499557 # number of overall hits -system.cpu0.icache.overall_miss_latency 23474000 # number of overall miss cycles -system.cpu0.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu0.icache.overall_misses 463 # number of overall misses -system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_miss_latency 22085000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.icache.replacements 152 # number of replacements -system.cpu0.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.icache.tagsinuse 216.390931 # Cycle average of tags in use -system.cpu0.icache.total_refs 499557 # Total number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.writebacks 0 # number of writebacks -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.itb.data_acv 0 # DTB access violations -system.cpu0.itb.data_hits 0 # DTB hits -system.cpu0.itb.data_misses 0 # DTB misses -system.cpu0.itb.fetch_accesses 500033 # ITB accesses -system.cpu0.itb.fetch_acv 0 # ITB acv -system.cpu0.itb.fetch_hits 500020 # ITB hits -system.cpu0.itb.fetch_misses 13 # ITB misses -system.cpu0.itb.read_accesses 0 # DTB read accesses -system.cpu0.itb.read_acv 0 # DTB read access violations -system.cpu0.itb.read_hits 0 # DTB read hits -system.cpu0.itb.read_misses 0 # DTB read misses -system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.write_acv 0 # DTB write access violations -system.cpu0.itb.write_hits 0 # DTB write hits -system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.numCycles 1457840 # number of cpu cycles simulated -system.cpu0.num_insts 500001 # Number of instructions executed -system.cpu0.num_refs 182222 # Number of memory references -system.cpu0.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu1.dcache.ReadReq_accesses 124435 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_avg_miss_latency 54891.975309 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 51891.975309 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_hits 124111 # number of ReadReq hits -system.cpu1.dcache.ReadReq_miss_latency 17785000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu1.dcache.ReadReq_mshr_miss_latency 16813000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_avg_miss_latency 56136.690647 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 53136.690647 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_hits 56200 # number of WriteReq hits -system.cpu1.dcache.WriteReq_miss_latency 7803000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu1.dcache.WriteReq_mshr_miss_latency 7386000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses -system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.dcache.avg_refs 389.440605 # Average number of references to valid blocks. -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.demand_accesses 180774 # number of demand (read+write) accesses -system.cpu1.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency -system.cpu1.dcache.demand_hits 180311 # number of demand (read+write) hits -system.cpu1.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu1.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.occ_%::0 0.534204 # Average percentage of cache occupancy -system.cpu1.dcache.occ_blocks::0 273.512548 # Average occupied blocks per context -system.cpu1.dcache.overall_accesses 180774 # number of overall (read+write) accesses -system.cpu1.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.dcache.overall_hits 180311 # number of overall hits -system.cpu1.dcache.overall_miss_latency 25588000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu1.dcache.overall_misses 463 # number of overall misses -system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.dcache.replacements 61 # number of replacements -system.cpu1.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.dcache.tagsinuse 273.512548 # Cycle average of tags in use -system.cpu1.dcache.total_refs 180311 # Total number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.writebacks 29 # number of writebacks -system.cpu1.dtb.data_accesses 180792 # DTB accesses -system.cpu1.dtb.data_acv 0 # DTB access violations -system.cpu1.dtb.data_hits 180774 # DTB hits -system.cpu1.dtb.data_misses 18 # DTB misses -system.cpu1.dtb.fetch_accesses 0 # ITB accesses -system.cpu1.dtb.fetch_acv 0 # ITB acv -system.cpu1.dtb.fetch_hits 0 # ITB hits -system.cpu1.dtb.fetch_misses 0 # ITB misses -system.cpu1.dtb.read_accesses 124443 # DTB read accesses -system.cpu1.dtb.read_acv 0 # DTB read access violations -system.cpu1.dtb.read_hits 124435 # DTB read hits -system.cpu1.dtb.read_misses 8 # DTB read misses -system.cpu1.dtb.write_accesses 56349 # DTB write accesses -system.cpu1.dtb.write_acv 0 # DTB write access violations -system.cpu1.dtb.write_hits 56339 # DTB write hits -system.cpu1.dtb.write_misses 10 # DTB write misses -system.cpu1.icache.ReadReq_accesses 500012 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_avg_miss_latency 50697.624190 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency 47697.624190 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_hits 499549 # number of ReadReq hits -system.cpu1.icache.ReadReq_miss_latency 23473000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu1.icache.ReadReq_mshr_miss_latency 22084000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.icache.avg_refs 1078.939525 # Average number of references to valid blocks. -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.demand_accesses 500012 # number of demand (read+write) accesses -system.cpu1.icache.demand_avg_miss_latency 50697.624190 # average overall miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency -system.cpu1.icache.demand_hits 499549 # number of demand (read+write) hits -system.cpu1.icache.demand_miss_latency 23473000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu1.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_miss_latency 22084000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.occ_%::0 0.422630 # Average percentage of cache occupancy -system.cpu1.icache.occ_blocks::0 216.386658 # Average occupied blocks per context -system.cpu1.icache.overall_accesses 500012 # number of overall (read+write) accesses -system.cpu1.icache.overall_avg_miss_latency 50697.624190 # average overall miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency 47697.624190 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu1.icache.overall_hits 499549 # number of overall hits -system.cpu1.icache.overall_miss_latency 23473000 # number of overall miss cycles -system.cpu1.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu1.icache.overall_misses 463 # number of overall misses -system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_miss_latency 22084000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.icache.replacements 152 # number of replacements -system.cpu1.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.icache.tagsinuse 216.386658 # Cycle average of tags in use -system.cpu1.icache.total_refs 499549 # Total number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.writebacks 0 # number of writebacks -system.cpu1.idle_fraction 0 # Percentage of idle cycles -system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.itb.data_acv 0 # DTB access violations -system.cpu1.itb.data_hits 0 # DTB hits -system.cpu1.itb.data_misses 0 # DTB misses -system.cpu1.itb.fetch_accesses 500025 # ITB accesses -system.cpu1.itb.fetch_acv 0 # ITB acv -system.cpu1.itb.fetch_hits 500012 # ITB hits -system.cpu1.itb.fetch_misses 13 # ITB misses -system.cpu1.itb.read_accesses 0 # DTB read accesses -system.cpu1.itb.read_acv 0 # DTB read access violations -system.cpu1.itb.read_hits 0 # DTB read hits -system.cpu1.itb.read_misses 0 # DTB read misses -system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.write_acv 0 # DTB write access violations -system.cpu1.itb.write_hits 0 # DTB write hits -system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu1.numCycles 1457840 # number of cpu cycles simulated -system.cpu1.num_insts 499993 # Number of instructions executed -system.cpu1.num_refs 182221 # Number of memory references -system.cpu1.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu2.dcache.ReadReq_accesses 124433 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_avg_miss_latency 54919.753086 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 51919.753086 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_hits 124109 # number of ReadReq hits -system.cpu2.dcache.ReadReq_miss_latency 17794000 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu2.dcache.ReadReq_mshr_miss_latency 16822000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu2.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_hits 56200 # number of WriteReq hits -system.cpu2.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu2.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses -system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.dcache.avg_refs 389.436285 # Average number of references to valid blocks. -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.demand_accesses 180772 # number of demand (read+write) accesses -system.cpu2.dcache.demand_avg_miss_latency 55272.138229 # average overall miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency -system.cpu2.dcache.demand_hits 180309 # number of demand (read+write) hits -system.cpu2.dcache.demand_miss_latency 25591000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu2.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.dcache.demand_mshr_miss_latency 24202000 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses -system.cpu2.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.occ_%::0 0.534196 # Average percentage of cache occupancy -system.cpu2.dcache.occ_blocks::0 273.508588 # Average occupied blocks per context -system.cpu2.dcache.overall_accesses 180772 # number of overall (read+write) accesses -system.cpu2.dcache.overall_avg_miss_latency 55272.138229 # average overall miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency 52272.138229 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.dcache.overall_hits 180309 # number of overall hits -system.cpu2.dcache.overall_miss_latency 25591000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu2.dcache.overall_misses 463 # number of overall misses -system.cpu2.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.dcache.overall_mshr_miss_latency 24202000 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses -system.cpu2.dcache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.dcache.replacements 61 # number of replacements -system.cpu2.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.dcache.tagsinuse 273.508588 # Cycle average of tags in use -system.cpu2.dcache.total_refs 180309 # Total number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.writebacks 29 # number of writebacks -system.cpu2.dtb.data_accesses 180790 # DTB accesses -system.cpu2.dtb.data_acv 0 # DTB access violations -system.cpu2.dtb.data_hits 180772 # DTB hits -system.cpu2.dtb.data_misses 18 # DTB misses -system.cpu2.dtb.fetch_accesses 0 # ITB accesses -system.cpu2.dtb.fetch_acv 0 # ITB acv -system.cpu2.dtb.fetch_hits 0 # ITB hits -system.cpu2.dtb.fetch_misses 0 # ITB misses -system.cpu2.dtb.read_accesses 124441 # DTB read accesses -system.cpu2.dtb.read_acv 0 # DTB read access violations -system.cpu2.dtb.read_hits 124433 # DTB read hits -system.cpu2.dtb.read_misses 8 # DTB read misses -system.cpu2.dtb.write_accesses 56349 # DTB write accesses -system.cpu2.dtb.write_acv 0 # DTB write access violations -system.cpu2.dtb.write_hits 56339 # DTB write hits -system.cpu2.dtb.write_misses 10 # DTB write misses -system.cpu2.icache.ReadReq_accesses 500001 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_avg_miss_latency 50719.222462 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency 47719.222462 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_hits 499538 # number of ReadReq hits -system.cpu2.icache.ReadReq_miss_latency 23483000 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu2.icache.ReadReq_mshr_miss_latency 22094000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.icache.avg_refs 1078.915767 # Average number of references to valid blocks. -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.demand_accesses 500001 # number of demand (read+write) accesses -system.cpu2.icache.demand_avg_miss_latency 50719.222462 # average overall miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency -system.cpu2.icache.demand_hits 499538 # number of demand (read+write) hits -system.cpu2.icache.demand_miss_latency 23483000 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu2.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu2.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.icache.demand_mshr_miss_latency 22094000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu2.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.icache.occ_%::0 0.422624 # Average percentage of cache occupancy -system.cpu2.icache.occ_blocks::0 216.383557 # Average occupied blocks per context -system.cpu2.icache.overall_accesses 500001 # number of overall (read+write) accesses -system.cpu2.icache.overall_avg_miss_latency 50719.222462 # average overall miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency 47719.222462 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu2.icache.overall_hits 499538 # number of overall hits -system.cpu2.icache.overall_miss_latency 23483000 # number of overall miss cycles -system.cpu2.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu2.icache.overall_misses 463 # number of overall misses -system.cpu2.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.icache.overall_mshr_miss_latency 22094000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu2.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.icache.replacements 152 # number of replacements -system.cpu2.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.icache.tagsinuse 216.383557 # Cycle average of tags in use -system.cpu2.icache.total_refs 499538 # Total number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.writebacks 0 # number of writebacks -system.cpu2.idle_fraction 0 # Percentage of idle cycles -system.cpu2.itb.data_accesses 0 # DTB accesses -system.cpu2.itb.data_acv 0 # DTB access violations -system.cpu2.itb.data_hits 0 # DTB hits -system.cpu2.itb.data_misses 0 # DTB misses -system.cpu2.itb.fetch_accesses 500014 # ITB accesses -system.cpu2.itb.fetch_acv 0 # ITB acv -system.cpu2.itb.fetch_hits 500001 # ITB hits -system.cpu2.itb.fetch_misses 13 # ITB misses -system.cpu2.itb.read_accesses 0 # DTB read accesses -system.cpu2.itb.read_acv 0 # DTB read access violations -system.cpu2.itb.read_hits 0 # DTB read hits -system.cpu2.itb.read_misses 0 # DTB read misses -system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.write_acv 0 # DTB write access violations -system.cpu2.itb.write_hits 0 # DTB write hits -system.cpu2.itb.write_misses 0 # DTB write misses -system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu2.numCycles 1457840 # number of cpu cycles simulated -system.cpu2.num_insts 499982 # Number of instructions executed -system.cpu2.num_refs 182218 # Number of memory references -system.cpu2.workload.PROG:num_syscalls 18 # Number of system calls -system.cpu3.dcache.ReadReq_accesses 124431 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_avg_miss_latency 54910.493827 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 51910.493827 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_hits 124107 # number of ReadReq hits -system.cpu3.dcache.ReadReq_miss_latency 17791000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_rate 0.002604 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_misses 324 # number of ReadReq misses -system.cpu3.dcache.ReadReq_mshr_miss_latency 16819000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_rate 0.002604 # mshr miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_mshr_misses 324 # number of ReadReq MSHR misses -system.cpu3.dcache.WriteReq_accesses 56339 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_avg_miss_latency 56093.525180 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 53093.525180 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_hits 56200 # number of WriteReq hits -system.cpu3.dcache.WriteReq_miss_latency 7797000 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_rate 0.002467 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_misses 139 # number of WriteReq misses -system.cpu3.dcache.WriteReq_mshr_miss_latency 7380000 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_rate 0.002467 # mshr miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_mshr_misses 139 # number of WriteReq MSHR misses -system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.dcache.avg_refs 389.431965 # Average number of references to valid blocks. -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.demand_accesses 180770 # number of demand (read+write) accesses -system.cpu3.dcache.demand_avg_miss_latency 55265.658747 # average overall miss latency -system.cpu3.dcache.demand_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency -system.cpu3.dcache.demand_hits 180307 # number of demand (read+write) hits -system.cpu3.dcache.demand_miss_latency 25588000 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_rate 0.002561 # miss rate for demand accesses -system.cpu3.dcache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.dcache.demand_mshr_miss_latency 24199000 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_rate 0.002561 # mshr miss rate for demand accesses -system.cpu3.dcache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.occ_%::0 0.534191 # Average percentage of cache occupancy -system.cpu3.dcache.occ_blocks::0 273.505617 # Average occupied blocks per context -system.cpu3.dcache.overall_accesses 180770 # number of overall (read+write) accesses -system.cpu3.dcache.overall_avg_miss_latency 55265.658747 # average overall miss latency -system.cpu3.dcache.overall_avg_mshr_miss_latency 52265.658747 # average overall mshr miss latency -system.cpu3.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.dcache.overall_hits 180307 # number of overall hits -system.cpu3.dcache.overall_miss_latency 25588000 # number of overall miss cycles -system.cpu3.dcache.overall_miss_rate 0.002561 # miss rate for overall accesses -system.cpu3.dcache.overall_misses 463 # number of overall misses -system.cpu3.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.dcache.overall_mshr_miss_latency 24199000 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_rate 0.002561 # mshr miss rate for overall accesses -system.cpu3.dcache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu3.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.dcache.replacements 61 # number of replacements -system.cpu3.dcache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.dcache.tagsinuse 273.505617 # Cycle average of tags in use -system.cpu3.dcache.total_refs 180307 # Total number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.writebacks 29 # number of writebacks -system.cpu3.dtb.data_accesses 180788 # DTB accesses -system.cpu3.dtb.data_acv 0 # DTB access violations -system.cpu3.dtb.data_hits 180770 # DTB hits -system.cpu3.dtb.data_misses 18 # DTB misses -system.cpu3.dtb.fetch_accesses 0 # ITB accesses -system.cpu3.dtb.fetch_acv 0 # ITB acv -system.cpu3.dtb.fetch_hits 0 # ITB hits -system.cpu3.dtb.fetch_misses 0 # ITB misses -system.cpu3.dtb.read_accesses 124439 # DTB read accesses -system.cpu3.dtb.read_acv 0 # DTB read access violations -system.cpu3.dtb.read_hits 124431 # DTB read hits -system.cpu3.dtb.read_misses 8 # DTB read misses -system.cpu3.dtb.write_accesses 56349 # DTB write accesses -system.cpu3.dtb.write_acv 0 # DTB write access violations -system.cpu3.dtb.write_hits 56339 # DTB write hits -system.cpu3.dtb.write_misses 10 # DTB write misses -system.cpu3.icache.ReadReq_accesses 499997 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_avg_miss_latency 50738.660907 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency 47738.660907 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_hits 499534 # number of ReadReq hits -system.cpu3.icache.ReadReq_miss_latency 23492000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_rate 0.000926 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_misses 463 # number of ReadReq misses -system.cpu3.icache.ReadReq_mshr_miss_latency 22103000 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_rate 0.000926 # mshr miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_mshr_misses 463 # number of ReadReq MSHR misses -system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.icache.avg_refs 1078.907127 # Average number of references to valid blocks. -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.demand_accesses 499997 # number of demand (read+write) accesses -system.cpu3.icache.demand_avg_miss_latency 50738.660907 # average overall miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency -system.cpu3.icache.demand_hits 499534 # number of demand (read+write) hits -system.cpu3.icache.demand_miss_latency 23492000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_rate 0.000926 # miss rate for demand accesses -system.cpu3.icache.demand_misses 463 # number of demand (read+write) misses -system.cpu3.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.icache.demand_mshr_miss_latency 22103000 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_rate 0.000926 # mshr miss rate for demand accesses -system.cpu3.icache.demand_mshr_misses 463 # number of demand (read+write) MSHR misses -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.icache.occ_%::0 0.422621 # Average percentage of cache occupancy -system.cpu3.icache.occ_blocks::0 216.381810 # Average occupied blocks per context -system.cpu3.icache.overall_accesses 499997 # number of overall (read+write) accesses -system.cpu3.icache.overall_avg_miss_latency 50738.660907 # average overall miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency 47738.660907 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu3.icache.overall_hits 499534 # number of overall hits -system.cpu3.icache.overall_miss_latency 23492000 # number of overall miss cycles -system.cpu3.icache.overall_miss_rate 0.000926 # miss rate for overall accesses -system.cpu3.icache.overall_misses 463 # number of overall misses -system.cpu3.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.icache.overall_mshr_miss_latency 22103000 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_rate 0.000926 # mshr miss rate for overall accesses -system.cpu3.icache.overall_mshr_misses 463 # number of overall MSHR misses -system.cpu3.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu3.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.icache.replacements 152 # number of replacements -system.cpu3.icache.sampled_refs 463 # Sample count of references to valid blocks. -system.cpu3.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.icache.tagsinuse 216.381810 # Cycle average of tags in use -system.cpu3.icache.total_refs 499534 # Total number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.writebacks 0 # number of writebacks -system.cpu3.idle_fraction 0 # Percentage of idle cycles -system.cpu3.itb.data_accesses 0 # DTB accesses -system.cpu3.itb.data_acv 0 # DTB access violations -system.cpu3.itb.data_hits 0 # DTB hits -system.cpu3.itb.data_misses 0 # DTB misses -system.cpu3.itb.fetch_accesses 500010 # ITB accesses -system.cpu3.itb.fetch_acv 0 # ITB acv -system.cpu3.itb.fetch_hits 499997 # ITB hits -system.cpu3.itb.fetch_misses 13 # ITB misses -system.cpu3.itb.read_accesses 0 # DTB read accesses -system.cpu3.itb.read_acv 0 # DTB read access violations -system.cpu3.itb.read_hits 0 # DTB read hits -system.cpu3.itb.read_misses 0 # DTB read misses -system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.write_acv 0 # DTB write access violations -system.cpu3.itb.write_hits 0 # DTB write hits -system.cpu3.itb.write_misses 0 # DTB write misses -system.cpu3.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu3.numCycles 1457840 # number of cpu cycles simulated -system.cpu3.num_insts 499978 # Number of instructions executed -system.cpu3.num_refs 182216 # Number of memory references -system.cpu3.workload.PROG:num_syscalls 18 # Number of system calls -system.l2c.ReadExReq_accesses::0 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 139 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 556 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 208021.582734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 208021.582734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 208021.582734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 208021.582734 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 832086.330935 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40005.395683 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 28915000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::3 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 4 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 139 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 556 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_miss_latency 22243000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 4 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 4 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 4 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 4 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 16 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 556 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 787 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 3148 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 208043.175487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 208043.175487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 208043.175487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 208043.175487 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 832172.701950 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 40010.793872 # average ReadReq mshr miss latency -system.l2c.ReadReq_hits::0 69 # number of ReadReq hits -system.l2c.ReadReq_hits::1 69 # number of ReadReq hits -system.l2c.ReadReq_hits::2 69 # number of ReadReq hits -system.l2c.ReadReq_hits::3 69 # number of ReadReq hits -system.l2c.ReadReq_hits::total 276 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 149375000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.912325 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 3.649301 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 718 # number of ReadReq misses -system.l2c.ReadReq_misses::1 718 # number of ReadReq misses -system.l2c.ReadReq_misses::2 718 # number of ReadReq misses -system.l2c.ReadReq_misses::3 718 # number of ReadReq misses -system.l2c.ReadReq_misses::total 2872 # number of ReadReq misses -system.l2c.ReadReq_mshr_miss_latency 114911000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 3.649301 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 3.649301 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 3.649301 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 3.649301 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 14.597205 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 2872 # number of ReadReq MSHR misses -system.l2c.Writeback_accesses::0 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 116 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 116 # number of Writeback hits -system.l2c.Writeback_hits::total 116 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 0.113233 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 926 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3704 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 208039.673279 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 208039.673279 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 208039.673279 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 208039.673279 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 832158.693116 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency -system.l2c.demand_hits::0 69 # number of demand (read+write) hits -system.l2c.demand_hits::1 69 # number of demand (read+write) hits -system.l2c.demand_hits::2 69 # number of demand (read+write) hits -system.l2c.demand_hits::3 69 # number of demand (read+write) hits -system.l2c.demand_hits::total 276 # number of demand (read+write) hits -system.l2c.demand_miss_latency 178290000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.925486 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 3.701944 # miss rate for demand accesses -system.l2c.demand_misses::0 857 # number of demand (read+write) misses -system.l2c.demand_misses::1 857 # number of demand (read+write) misses -system.l2c.demand_misses::2 857 # number of demand (read+write) misses -system.l2c.demand_misses::3 857 # number of demand (read+write) misses -system.l2c.demand_misses::total 3428 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 137154000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 3.701944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 3.701944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 3.701944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 3.701944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 14.807775 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 3428 # number of demand (read+write) MSHR misses -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.007348 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.007347 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.007347 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.007347 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.000263 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 481.530369 # Average occupied blocks per context -system.l2c.occ_blocks::1 481.519672 # Average occupied blocks per context -system.l2c.occ_blocks::2 481.512310 # Average occupied blocks per context -system.l2c.occ_blocks::3 481.507730 # Average occupied blocks per context -system.l2c.occ_blocks::4 17.228456 # Average occupied blocks per context -system.l2c.overall_accesses::0 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 926 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3704 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 208039.673279 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 208039.673279 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 208039.673279 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 208039.673279 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 832158.693116 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 40009.918320 # average overall mshr miss latency -system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.l2c.overall_hits::0 69 # number of overall hits -system.l2c.overall_hits::1 69 # number of overall hits -system.l2c.overall_hits::2 69 # number of overall hits -system.l2c.overall_hits::3 69 # number of overall hits -system.l2c.overall_hits::total 276 # number of overall hits -system.l2c.overall_miss_latency 178290000 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.925486 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 3.701944 # miss rate for overall accesses -system.l2c.overall_misses::0 857 # number of overall misses -system.l2c.overall_misses::1 857 # number of overall misses -system.l2c.overall_misses::2 857 # number of overall misses -system.l2c.overall_misses::3 857 # number of overall misses -system.l2c.overall_misses::total 3428 # number of overall misses -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 137154000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 3.701944 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 3.701944 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 3.701944 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 3.701944 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 14.807775 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 3428 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 0 # number of replacements -system.l2c.sampled_refs 2932 # Sample count of references to valid blocks. -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 1943.298536 # Cycle average of tags in use -system.l2c.total_refs 332 # Total number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 0 # number of writebacks - ----------- End Simulation Statistics ---------- diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini Wed Nov 03 18:14:20 2010 -0500 @@ -1,20 +1,16 @@ -[root] -type=Root -children=drivesys etherdump etherlink testsys -dummy=0 - [drivesys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=drivesys.physmem -readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-server.rcS +readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -95,7 +91,7 @@ [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -115,7 +111,7 @@ [drivesys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [drivesys.intrctrl] @@ -179,7 +175,7 @@ [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [drivesys.terminal] @@ -264,7 +260,7 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 -hardware_address=00:90:00:00:00:01 +hardware_address=00:90:00:00:00:02 intr_delay=10000000 max_backoff_delay=10000000 min_backoff_delay=4000 @@ -707,18 +703,24 @@ int0=testsys.tsunami.ethernet.interface int1=drivesys.tsunami.ethernet.interface +[root] +type=Root +children=drivesys etherdump etherlink testsys +dummy=0 + [testsys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem simple_disk terminal tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/chips/pd/randd/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/chips/pd/randd/dist/binaries/vmlinux +load_addr_mask=1099511627775 mem_mode=atomic -pal=/dist/m5/system/binaries/ts_osfpal +pal=/chips/pd/randd/dist/binaries/ts_osfpal physmem=testsys.physmem -readfile=/n/blue/z/binkert/work/m5/work/configs/boot/netperf-stream-client.rcS +readfile=/arm/scratch/alisai01/m5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -799,7 +801,7 @@ [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [testsys.disk2] @@ -819,7 +821,7 @@ [testsys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img read_only=true [testsys.intrctrl] @@ -883,7 +885,7 @@ [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/chips/pd/randd/dist/disks/linux-latest.img read_only=true [testsys.terminal] @@ -968,7 +970,7 @@ dma_read_factor=0 dma_write_delay=0 dma_write_factor=0 -hardware_address=00:90:00:00:00:02 +hardware_address=00:90:00:00:00:01 intr_delay=10000000 max_backoff_delay=10000000 min_backoff_delay=4000 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal Wed Nov 03 18:14:20 2010 -0500 @@ -59,7 +59,7 @@ eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg tun: Universal TUN/TAP device driver, 1.6 tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout Wed Nov 03 18:14:20 2010 -0500 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simout +Redirecting stderr to build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ All Rights Reserved -M5 compiled Jun 14 2010 18:16:48 -M5 revision 22c414a5ff89+ 7455+ default stats_funcinit.diff qtip tip -M5 started Jun 14 2010 18:19:53 -M5 executing on maize -command line: /n/blue/z/binkert/build/work/build/ALPHA_FS/m5.fast -d /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py /n/blue/z/binkert/build/work/build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic +M5 compiled Nov 2 2010 23:00:12 +M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip +M5 started Nov 2 2010 23:11:17 +M5 executing on aus-bc2-b15 +command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux +info: kernel located at: /chips/pd/randd/dist/binaries/vmlinux info: Entering event queue @ 0. Starting simulation... Exiting @ tick 4300236804024 because checkpoint diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt Wed Nov 03 18:14:20 2010 -0500 @@ -94,7 +94,7 @@ drivesys.cpu.not_idle_fraction 0.000010 # Percentage of non-idle cycles drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated drivesys.cpu.num_insts 1958129 # Number of instructions executed -drivesys.cpu.num_refs 626223 # Number of memory references +drivesys.cpu.num_refs 625939 # Number of memory references drivesys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). drivesys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). drivesys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -156,10 +156,10 @@ drivesys.tsunami.ethernet.txPackets 5 # Number of Packets Transmitted drivesys.tsunami.ethernet.txTcpChecksums 2 # Number of tx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device -host_inst_rate 296969022 # Simulator instruction rate (inst/s) -host_mem_usage 463340 # Number of bytes of host memory used -host_seconds 0.92 # Real time elapsed on the host -host_tick_rate 217224993666 # Simulator tick rate (ticks/s) +host_inst_rate 245765975 # Simulator instruction rate (inst/s) +host_mem_usage 512700 # Number of bytes of host memory used +host_seconds 1.11 # Real time elapsed on the host +host_tick_rate 179775828937 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.200001 # Number of seconds simulated @@ -268,7 +268,7 @@ testsys.cpu.not_idle_fraction 0.000018 # Percentage of non-idle cycles testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated testsys.cpu.num_insts 3560411 # Number of instructions executed -testsys.cpu.num_refs 1173571 # Number of memory references +testsys.cpu.num_refs 1173234 # Number of memory references testsys.disk0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). testsys.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). testsys.disk0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -431,10 +431,10 @@ drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -host_inst_rate 197240139250 # Simulator instruction rate (inst/s) -host_mem_usage 463340 # Number of bytes of host memory used +host_inst_rate 151538155765 # Simulator instruction rate (inst/s) +host_mem_usage 512700 # Number of bytes of host memory used host_seconds 0.00 # Real time elapsed on the host -host_tick_rate 532144888 # Simulator tick rate (ticks/s) +host_tick_rate 415641460 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 273374833 # Number of instructions simulated sim_seconds 0.000001 # Number of seconds simulated diff -r 80177d2dc2a8 -r 15fb33736bdb tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal --- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal Wed Nov 03 18:14:16 2010 -0500 +++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal Wed Nov 03 18:14:20 2010 -0500 @@ -59,7 +59,7 @@ eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 eth0: enabling optical transceiver eth0: using 64 bit addressing. - eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg + eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg tun: Universal TUN/TAP device driver, 1.6 tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2