diff -r e3d480532111 -r 2a3da6724aae src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc	Sat Oct 02 21:13:54 2010 -0500
+++ b/src/arch/arm/isa.cc	Sat Oct 02 21:14:01 2010 -0500
@@ -186,10 +186,10 @@
     }
     switch (misc_reg) {
       case MISCREG_CLIDR:
-        warn("The clidr register always reports 0 caches.\n");
+        warn_once("The clidr register always reports 0 caches.\n");
         break;
       case MISCREG_CCSIDR:
-        warn("The ccsidr register isn't implemented and "
+        warn_once("The ccsidr register isn't implemented and "
                 "always reads as 0.\n");
         break;
       case MISCREG_ID_PFR0:
@@ -277,7 +277,7 @@
             }
             break;
           case MISCREG_CSSELR:
-            warn("The csselr register isn't implemented.\n");
+            warn_once("The csselr register isn't implemented.\n");
             break;
           case MISCREG_FPSCR:
             {
@@ -328,7 +328,7 @@
             return;
           case MISCREG_TLBIALLIS:
           case MISCREG_TLBIALL:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushAll();
             tc->getDTBPtr()->flushAll();
             return;
@@ -340,7 +340,7 @@
             return;
           case MISCREG_TLBIMVAIS:
           case MISCREG_TLBIMVA:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
                     bits(newVal, 7,0));
             tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
@@ -348,13 +348,13 @@
             return;
           case MISCREG_TLBIASIDIS:
           case MISCREG_TLBIASID:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushAsid(bits(newVal, 7,0));
             tc->getDTBPtr()->flushAsid(bits(newVal, 7,0));
             return;
           case MISCREG_TLBIMVAAIS:
           case MISCREG_TLBIMVAA:
-            warn("Need to flush all TLBs in MP\n");
+            warn_once("Need to flush all TLBs in MP\n");
             tc->getITBPtr()->flushMva(mbits(newVal, 31,12));
             tc->getDTBPtr()->flushMva(mbits(newVal, 31,12));
             return;
diff -r e3d480532111 -r 2a3da6724aae src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py	Sat Oct 02 21:13:54 2010 -0500
+++ b/src/dev/arm/RealView.py	Sat Oct 02 21:14:01 2010 -0500
@@ -100,7 +100,7 @@
     timer0 = Sp804(int_num0=36, int_num1=36, pio_addr=0x10011000)
     timer1 = Sp804(int_num0=37, int_num1=37, pio_addr=0x10012000)
 
-    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff, warn_access="1")
+    l2x0_fake     = IsaFake(pio_addr=0x1f002000, pio_size=0xfff)#, warn_access="1")
     flash_fake    = IsaFake(pio_addr=0x40000000, pio_size=0x4000000)
     dmac_fake     = AmbaFake(pio_addr=0x10030000)
     uart1_fake    = AmbaFake(pio_addr=0x1000a000)