diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/alpha/isa.hh
--- a/src/arch/alpha/isa.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/alpha/isa.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -73,7 +73,7 @@
 
       public:
 
-        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
         MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
 
         void setMiscRegNoEffect(int misc_reg, const MiscReg &val,
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/alpha/isa.cc
--- a/src/arch/alpha/isa.cc	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/alpha/isa.cc	Tue Feb 03 20:05:12 2015 +0000
@@ -74,7 +74,7 @@
 
 
 MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     switch (misc_reg) {
       case MISCREG_FPCR:
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/mips/isa.hh
--- a/src/arch/mips/isa.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/mips/isa.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -76,7 +76,7 @@
 
         void configCP();
 
-        unsigned getVPENum(ThreadID tid);
+        unsigned getVPENum(ThreadID tid) const;
 
         //////////////////////////////////////////////////////////
         //
@@ -87,7 +87,7 @@
         //@TODO: MIPS MT's register view automatically connects
         //       Status to TCStatus depending on current thread
         void updateCP0ReadView(int misc_reg, ThreadID tid) { }
-        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0);
+        MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
 
         //template <class TC>
         MiscReg readMiscReg(int misc_reg,
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/mips/isa.cc
--- a/src/arch/mips/isa.cc	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/mips/isa.cc	Tue Feb 03 20:05:12 2015 +0000
@@ -410,14 +410,14 @@
 }
 
 inline unsigned
-ISA::getVPENum(ThreadID tid)
+ISA::getVPENum(ThreadID tid) const
 {
     TCBindReg tcBind = miscRegFile[MISCREG_TC_BIND][tid];
     return tcBind.curVPE;
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     unsigned reg_sel = (bankType[misc_reg] == perThreadContext)
         ? tid : getVPENum(tid);
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/power/isa.hh
--- a/src/arch/power/isa.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/power/isa.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -61,7 +61,7 @@
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg)
+    readMiscRegNoEffect(int misc_reg) const
     {
         fatal("Power does not currently have any misc regs defined\n");
         return dummy;
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/sparc/isa.hh
--- a/src/arch/sparc/isa.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/sparc/isa.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -183,7 +183,7 @@
 
   public:
 
-    MiscReg readMiscRegNoEffect(int miscReg);
+    MiscReg readMiscRegNoEffect(int miscReg) const;
     MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
     void setMiscRegNoEffect(int miscReg, const MiscReg val);
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/sparc/isa.cc
--- a/src/arch/sparc/isa.cc	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/sparc/isa.cc	Tue Feb 03 20:05:12 2015 +0000
@@ -173,7 +173,7 @@
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
 {
 
   // The three miscRegs are moved up from the switch statement
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/x86/isa.hh
--- a/src/arch/x86/isa.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/x86/isa.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -63,7 +63,7 @@
         ISA(Params *p);
         const Params *params() const;
 
-        MiscReg readMiscRegNoEffect(int miscReg);
+        MiscReg readMiscRegNoEffect(int miscReg) const;
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
 
         void setMiscRegNoEffect(int miscReg, MiscReg val);
diff -r 3cc22df1b992 -r e09ee3611a0f src/arch/x86/isa.cc
--- a/src/arch/x86/isa.cc	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/arch/x86/isa.cc	Tue Feb 03 20:05:12 2015 +0000
@@ -124,7 +124,7 @@
 }
 
 MiscReg
-ISA::readMiscRegNoEffect(int miscReg)
+ISA::readMiscRegNoEffect(int miscReg) const
 {
     // Make sure we're not dealing with an illegal control register.
     // Instructions should filter out these indexes, and nothing else should
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/checker/cpu.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -285,7 +285,7 @@
     MicroPC microPC() { return thread->microPC(); }
     //////////////////////////////////////////
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/checker/thread_context.hh
--- a/src/cpu/checker/thread_context.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/checker/thread_context.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -275,7 +275,7 @@
     MicroPC microPC()
     { return actualTC->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/minor/exec_context.hh
--- a/src/cpu/minor/exec_context.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/minor/exec_context.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -187,7 +187,7 @@
     }
 
     TheISA::MiscReg
-    readMiscRegNoEffect(int misc_reg)
+    readMiscRegNoEffect(int misc_reg) const
     {
         return thread.readMiscRegNoEffect(misc_reg);
     }
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/o3/cpu.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -403,7 +403,7 @@
     /** Register accessors.  Index refers to the physical register index. */
 
     /** Reads a miscellaneous register. */
-    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid);
+    TheISA::MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
 
     /** Reads a misc. register, including any side effects the read
      * might have as defined by the architecture.
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/o3/cpu.cc	Tue Feb 03 20:05:12 2015 +0000
@@ -1204,7 +1204,7 @@
 
 template <class Impl>
 TheISA::MiscReg
-FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
+FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
 {
     return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/o3/thread_context.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -228,7 +228,7 @@
     { return cpu->microPC(thread->threadId()); }
 
     /** Reads a miscellaneous register. */
-    virtual MiscReg readMiscRegNoEffect(int misc_reg)
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const
     { return cpu->readMiscRegNoEffect(misc_reg, thread->threadId()); }
 
     /** Reads a misc. register, including any side-effects the
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/simple/base.hh
--- a/src/cpu/simple/base.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/simple/base.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -367,7 +367,7 @@
     Addr nextInstAddr() { return thread->nextInstAddr(); }
     MicroPC microPC() { return thread->microPC(); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     {
         return thread->readMiscRegNoEffect(misc_reg);
     }
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/simple_thread.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -372,7 +372,7 @@
     }
 
     MiscReg
-    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
+    readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const
     {
         return isa->readMiscRegNoEffect(misc_reg);
     }
diff -r 3cc22df1b992 -r e09ee3611a0f src/cpu/thread_context.hh
--- a/src/cpu/thread_context.hh	Fri Jan 16 14:12:03 2015 -0600
+++ b/src/cpu/thread_context.hh	Tue Feb 03 20:05:12 2015 +0000
@@ -225,7 +225,7 @@
 
     virtual MicroPC microPC() = 0;
 
-    virtual MiscReg readMiscRegNoEffect(int misc_reg) = 0;
+    virtual MiscReg readMiscRegNoEffect(int misc_reg) const = 0;
 
     virtual MiscReg readMiscReg(int misc_reg) = 0;
 
@@ -429,7 +429,7 @@
     void setPredicate(bool val)
     { actualTC->setPredicate(val); }
 
-    MiscReg readMiscRegNoEffect(int misc_reg)
+    MiscReg readMiscRegNoEffect(int misc_reg) const
     { return actualTC->readMiscRegNoEffect(misc_reg); }
 
     MiscReg readMiscReg(int misc_reg)