diff -r c922ae8d84f9 -r c8c9b6d902cb src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh	Wed Mar 04 03:02:41 2015 -0600
+++ b/src/cpu/o3/commit.hh	Wed Mar 04 03:09:57 2015 -0600
@@ -489,14 +489,13 @@
     /** Updates commit stats based on this instruction. */
     void updateComInstStats(DynInstPtr &inst);
 
-    /** Stat for the total number of squashed instructions discarded by commit.
-     */
+    /** Total number of squashed instructions discarded by commit. */
     Stats::Scalar commitSquashedInsts;
-    /** Stat for the total number of times commit has had to stall due to a non-
-     * speculative instruction reaching the head of the ROB.
+    /** Total number of times commit has had to stall due to a non-speculative
+     *  instruction reaching the head of the ROB.
      */
     Stats::Scalar commitNonSpecStalls;
-    /** Stat for the total number of branch mispredicts that caused a squash. */
+    /** Total number of branch mispredicts that caused a squash. */
     Stats::Scalar branchMispredicts;
     /** Distribution of the number of committed instructions each cycle. */
     Stats::Distribution numCommittedDist;
@@ -526,6 +525,17 @@
 
     /** Number of cycles where the commit bandwidth limit is reached. */
     Stats::Scalar commitEligibleSamples;
+
+    /** Number of commit slots not utilized due to a mispredicted branch */
+    Stats::Scalar slotsMispredicted;
+    /** Number of commit slots not utilized due to delay in instruction
+        fetching */
+    Stats::Scalar slotsFetchDelayed;
+    /** Number of commit slots not utilized due to delay in accessing memory
+        for load / store. */
+    Stats::Scalar slotsMemoryDelayed;
+    /** Number of commit slots not utilized due to delay in execution. */
+    Stats::Scalar slotsExecutionDelayed;
 };
 
 #endif // __CPU_O3_COMMIT_HH__
diff -r c922ae8d84f9 -r c8c9b6d902cb src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Wed Mar 04 03:02:41 2015 -0600
+++ b/src/cpu/o3/commit_impl.hh	Wed Mar 04 03:09:57 2015 -0600
@@ -285,6 +285,22 @@
         .name(name() + ".bw_lim_events")
         .desc("number cycles where commit BW limit reached")
         ;
+
+    slotsMispredicted
+        .name(name() + ".slotsMispredicted")
+        .desc("vacant slots due to mispredicted branches.");
+
+    slotsFetchDelayed
+        .name(name() + ".slotsFetchDelayed")
+        .desc("vacant slots due to delay in instruction fetching.");
+
+    slotsMemoryDelayed
+        .name(name() + ".slotsMemoryDelayed")
+        .desc("vacant slots due to delay in accessing memory.");
+
+    slotsExecutionDelayed
+        .name(name() + ".slotsExecutionDelayed")
+        .desc("vacant slots due to delay in execution of the instruction.");
 }
 
 template <class Impl>
@@ -921,6 +937,8 @@
 
         // Try to commit any instructions.
         commitInsts();
+    } else {
+        slotsMispredicted += commitWidth;
     }
 
     //Check for any activity
@@ -955,7 +973,6 @@
             toIEW->commitInfo[tid].freeROBEntries = rob->numFreeEntries(tid);
             wroteToTimeBuffer = true;
         }
-
     }
 }
 
@@ -988,13 +1005,27 @@
 
         ThreadID commit_thread = getCommittingThread();
 
-        if (commit_thread == -1 || !rob->isHeadReady(commit_thread))
+        if (commit_thread == -1)
             break;
 
         head_inst = rob->readHeadInst(commit_thread);
+        if (!rob->isHeadReady(commit_thread)) {
+          if (head_inst) {
+              if (!head_inst->isMemRef()) {
+                  slotsExecutionDelayed += (commitWidth - num_committed);
+              }
+              else {
+                  slotsMemoryDelayed += (commitWidth - num_committed);
+              }
+          }
+          else {
+            slotsFetchDelayed += (commitWidth - num_committed);
+          }
+
+          break;
+        }
 
         ThreadID tid = head_inst->threadNumber;
-
         assert(tid == commit_thread);
 
         DPRINTF(Commit, "Trying to commit head instruction, [sn:%i] [tid:%i]\n",