diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/sc_target.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/sc_target.hh	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#ifndef __SIM_SC_TARGET_HH__
+#define __SIM_SC_TARGET_HH__
+
+#include <tlm_utils/peq_with_cb_and_phase.h>
+#include <tlm_utils/simple_target_socket.h>
+
+#include <iostream>
+#include <systemc>
+#include <tlm>
+
+using namespace sc_core;
+using namespace std;
+
+struct Target: sc_module
+{
+    /** TLM interface socket: */
+    tlm_utils::simple_target_socket<Target> socket;
+
+    /** TLM related member variables: */
+    tlm::tlm_generic_payload*  transaction_in_progress;
+    sc_event                   target_done_event;
+    bool                       response_in_progress;
+    bool                       debug;
+    tlm::tlm_generic_payload*  next_response_pending;
+    tlm::tlm_generic_payload*  end_req_pending;
+    tlm_utils::peq_with_cb_and_phase<Target> m_peq;
+
+    /** Storage, may be implemented with a map for large devices */
+    unsigned char *mem;
+
+    Target(sc_core::sc_module_name name,
+        bool debug,
+        unsigned long long int size,
+        unsigned int offset);
+    SC_HAS_PROCESS(Target);
+
+    /** TLM interface functions */
+    virtual void b_transport(tlm::tlm_generic_payload& trans,
+                             sc_time& delay);
+    virtual unsigned int transport_dbg(tlm::tlm_generic_payload& trans);
+    virtual tlm::tlm_sync_enum nb_transport_fw(
+                tlm::tlm_generic_payload& trans,
+                tlm::tlm_phase& phase,
+                sc_time& delay);
+
+    /** Callback of Payload Event Queue: */
+    void peq_cb(tlm::tlm_generic_payload& trans,
+                const tlm::tlm_phase& phase);
+
+    /** Helping function common to b_transport and nb_transport */
+    void execute_transaction(tlm::tlm_generic_payload& trans);
+
+    /** Helping functions and processes: */
+    void send_end_req(tlm::tlm_generic_payload& trans);
+    void send_response(tlm::tlm_generic_payload& trans);
+
+    /** Method process that runs on target_done_event */
+    void execute_transaction_process();
+
+    /** Helping Variables **/
+    unsigned long long int size;
+    unsigned offset;
+};
+
+#endif //__SIM_SC_TARGET_HH__
+
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/sc_target.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/sc_target.cc	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,271 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#include "sc_target.hh"
+
+using namespace sc_core;
+using namespace std;
+
+Target::Target(sc_core::sc_module_name name,
+    bool debug,
+    unsigned long long int size,
+    unsigned int offset) :
+    socket("socket"),
+    transaction_in_progress(0),
+    response_in_progress(false),
+    next_response_pending(0),
+    end_req_pending(0),
+    m_peq(this, &Target::peq_cb),
+    debug(debug),
+    size(size),
+    offset(offset)
+{
+    /* Register tlm transport functions */
+    socket.register_b_transport(this, &Target::b_transport);
+    socket.register_transport_dbg(this, &Target::transport_dbg);
+    socket.register_nb_transport_fw(this, &Target::nb_transport_fw);
+
+
+    /* allocate storage memory */
+    mem = new unsigned char[size];
+
+    SC_METHOD(execute_transaction_process);
+    sensitive << target_done_event;
+    dont_initialize();
+}
+
+void
+Target::b_transport(tlm::tlm_generic_payload& trans, sc_time& delay)
+{
+    /* Execute the read or write commands */
+    execute_transaction(trans);
+}
+
+unsigned int
+Target::transport_dbg(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_command cmd = trans.get_command();
+    sc_dt::uint64    adr = trans.get_address() - offset;
+    unsigned char*   ptr = trans.get_data_ptr();
+    unsigned int     len = trans.get_data_length();
+
+    unsigned char *mem_array_ptr = mem + adr;
+
+    //unsigned int num_bytes = (len < size - adr) ? len : size - adr;
+
+    /* Load / Store the access: */
+    if ( cmd == tlm::TLM_READ_COMMAND ) {
+        if(false) {
+            SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
+            std::cout << "0x" << std::hex << adr << std::endl;
+        }
+        std::memcpy(ptr, mem_array_ptr, len);
+    } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
+        if(false) {
+            SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
+            std::cout << "0x" << std::hex << adr << std::endl;
+        }
+        std::memcpy(mem_array_ptr, ptr, len);
+    }
+
+    return len;
+}
+
+
+/* TLM-2 non-blocking transport method */
+tlm::tlm_sync_enum Target::nb_transport_fw(tlm::tlm_generic_payload& trans,
+                                           tlm::tlm_phase& phase,
+                                           sc_time& delay)
+{
+    /* Queue the transaction until the annotated time has elapsed */
+    m_peq.notify( trans, phase, delay);
+    return tlm::TLM_ACCEPTED;
+}
+
+void
+Target::peq_cb(tlm::tlm_generic_payload& trans,
+               const tlm::tlm_phase& phase)
+{
+    sc_time delay;
+
+    if(phase == tlm::BEGIN_REQ) {
+        if(debug) SC_REPORT_INFO("target", "tlm::BEGIN_REQ");
+
+        /* Increment the transaction reference count */
+        trans.acquire();
+
+        if ( !transaction_in_progress ) {
+            send_end_req(trans);
+        } else {
+            /* Put back-pressure on initiator by deferring END_REQ until
+             * pipeline is clear */
+            end_req_pending = &trans;
+        }
+    }
+    else if (phase == tlm::END_RESP)
+    {
+        /* On receiving END_RESP, the target can release the transaction and
+         * allow other pending transactions to proceed */
+        if (!response_in_progress) {
+            SC_REPORT_FATAL("TLM-2", "Illegal transaction phase END_RESP"
+                            "received by target");
+        }
+
+        transaction_in_progress = 0;
+
+        /* Target itself is now clear to issue the next BEGIN_RESP */
+        response_in_progress = false;
+        if (next_response_pending) {
+            send_response( *next_response_pending );
+            next_response_pending = 0;
+        }
+
+        /* ... and to unblock the initiator by issuing END_REQ */
+        if (end_req_pending) {
+            send_end_req( *end_req_pending );
+            end_req_pending = 0;
+        }
+
+    } else /* tlm::END_REQ or tlm::BEGIN_RESP */ {
+            SC_REPORT_FATAL("TLM-2", "Illegal transaction phase received by"
+                            "target");
+    }
+}
+
+void
+Target::send_end_req(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_phase bw_phase;
+    sc_time delay;
+
+    /* Queue the acceptance and the response with the appropriate latency */
+    bw_phase = tlm::END_REQ;
+    delay = sc_time(10, SC_NS); // Accept delay
+
+    tlm::tlm_sync_enum status = socket->nb_transport_bw(trans,
+                                                        bw_phase,
+                                                        delay);
+
+    /* Ignore return value;
+     * initiator cannot terminate transaction at this point
+     * Queue internal event to mark beginning of response: */
+    delay = delay + sc_time(40, SC_NS); // Latency
+    target_done_event.notify( delay );
+
+    assert(transaction_in_progress == 0);
+    transaction_in_progress = &trans;
+}
+
+void
+Target::execute_transaction_process()
+{
+    /* Execute the read or write commands */
+    execute_transaction( *transaction_in_progress );
+
+    /* Target must honor BEGIN_RESP/END_RESP exclusion rule; i.e. must not
+     * send BEGIN_RESP until receiving previous END_RESP or BEGIN_REQ */
+    if (response_in_progress) {
+        /* Target allows only two transactions in-flight */
+        if (next_response_pending) {
+            SC_REPORT_FATAL("TLM-2", "Attempt to have two pending responses"
+                            "in target");
+        }
+        next_response_pending = transaction_in_progress;
+    } else {
+        send_response( *transaction_in_progress );
+    }
+}
+
+void
+Target::execute_transaction(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_command cmd = trans.get_command();
+    sc_dt::uint64    adr = trans.get_address() - offset;
+    unsigned char*   ptr = trans.get_data_ptr();
+    unsigned int     len = trans.get_data_length();
+    unsigned char*   byt = trans.get_byte_enable_ptr();
+    unsigned int     wid = trans.get_streaming_width();
+
+    if ( byt != 0 ) {
+        cout << "Byte Error" << endl;
+        trans.set_response_status( tlm::TLM_BYTE_ENABLE_ERROR_RESPONSE );
+        return;
+    }
+
+    //if ( len > 4 || wid < len ) {
+    //    cout << "Burst Error len=" << len << " wid=" << wid << endl;
+    //    trans.set_response_status( tlm::TLM_BURST_ERROR_RESPONSE );
+    //    return;
+    //}
+
+    unsigned char *mem_array_ptr = mem + adr;
+
+    /* Load / Store the access: */
+    if ( cmd == tlm::TLM_READ_COMMAND ) {
+        if(debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_READ_COMMAND");
+        }
+        std::memcpy(ptr, mem_array_ptr, len);
+    } else if ( cmd == tlm::TLM_WRITE_COMMAND ) {
+        if(debug) {
+            SC_REPORT_INFO("target", "tlm::TLM_WRITE_COMMAND");
+        }
+        std::memcpy(mem_array_ptr, ptr, len);
+    }
+
+    trans.set_response_status( tlm::TLM_OK_RESPONSE );
+}
+
+void
+Target::send_response(tlm::tlm_generic_payload& trans)
+{
+    tlm::tlm_sync_enum status;
+    tlm::tlm_phase bw_phase;
+    sc_time delay;
+
+    response_in_progress = true;
+    bw_phase = tlm::BEGIN_RESP;
+    delay = sc_time(10, SC_NS);
+    status = socket->nb_transport_bw( trans, bw_phase, delay );
+
+    if (status == tlm::TLM_UPDATED) {
+        /* The timing annotation must be honored */
+        m_peq.notify( trans, bw_phase, delay);
+    } else if (status == tlm::TLM_COMPLETED) {
+        /* The initiator has terminated the transaction */
+        transaction_in_progress = 0;
+        response_in_progress = false;
+    }
+    trans.release();
+}
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/tgen.cfg
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/tgen.cfg	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,24 @@
+# This format supports comments using the '#' symbol as the leading
+# character of the line
+#
+# The file format contains [STATE]+ [INIT] [TRANSITION]+ in any order,
+# where the states are the nodes in the graph, init describes what
+# state to start in, and transition describes the edges of the graph.
+#
+# STATE <id> <duration (ticks)> <type>
+#
+# State IDLE idles
+#
+# States LINEAR and RANDOM have additional <percent reads> <start addr>
+# <end addr> <access size (bytes)> <min period (ticks)> <max period (ticks)>
+# <data limit (bytes)>
+#
+# State TRACE plays back a pre-recorded trace once
+#
+# Addresses are expressed as decimal numbers. The period in the linear
+# and random state is from a uniform random distribution over the
+# interval. If a specific value is desired, then the min and max can
+# be set to the same value.
+STATE 0 1000000 LINEAR 50 0 256 4 5000 5000 64
+INIT 0
+TRANSITION 0 0 1
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/tlm.py
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/tlm.py	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,77 @@
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+#
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+#
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Matthias Jung
+
+import m5
+from m5.objects import *
+
+# This configuration shows a simple setup of a TrafficGen (CPU) and an
+# external TLM port for SystemC co-simulation
+#
+# Base System Architecture:
+# +-------------+  +-----+    ^
+# | System Port |  | CPU |    |
+# +-------+-----+  +--+--+    |
+#         |           |       | gem5 World
+#         |      +----+       | (see this file)
+#         |      |            |
+# +-------v------v-------+    |
+# |        Membus        |    v
+# +----------------+-----+    External Port (see sc_port.*)
+#                  |          ^
+#              +---v---+      | TLM World
+#              |  TLM  |      | (see sc_target.*)
+#              +-------+      v
+#
+
+# Create a system with a Crossbar and a TrafficGenerator as CPU:
+system = System()
+system.membus = IOXBar(width = 16)
+system.physmem = SimpleMemory() # This must be instanciated, even if not needed
+system.cpu = TrafficGen(config_file = "tgen.cfg")
+system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = VoltageDomain(voltage = '1V'))
+
+# Create a external TLM port:
+system.tlm = ExternalSlave()
+system.tlm.addr_ranges = [AddrRange('512MB')]
+system.tlm.port_type = "tlm"
+system.tlm.port_data = "memory"
+
+# Route the connections:
+system.cpu.port = system.membus.slave
+system.system_port = system.membus.slave
+system.membus.master = system.tlm.port
+
+# Start the simulation:
+root = Root(full_system = False, system = system)
+root.system.mem_mode = 'timing'
+m5.instantiate()
+m5.simulate() #Simulation time specified later on commandline
diff -r 9141d87c7f71 -r 99159dd794b8 configs/common/MemConfig.py
--- a/configs/common/MemConfig.py	Mon Jun 01 18:05:11 2015 -0500
+++ b/configs/common/MemConfig.py	Fri Jun 05 17:35:00 2015 +0200
@@ -151,6 +151,15 @@
     them.
     """
 
+    if options.tlm_memory:
+        system.external_memory = m5.objects.ExternalSlave(
+            port_type="tlm",
+            port_data=options.tlm_memory,
+            port=system.membus.master,
+            addr_ranges=system.mem_ranges)
+        system.kernel_addr_check = False
+        return
+
     if options.external_memory_system:
         system.external_memory = m5.objects.ExternalSlave(
             port_type=options.external_memory_system,
diff -r 9141d87c7f71 -r 99159dd794b8 configs/common/Options.py
--- a/configs/common/Options.py	Mon Jun 01 18:05:11 2015 -0500
+++ b/configs/common/Options.py	Fri Jun 05 17:35:00 2015 +0200
@@ -106,6 +106,8 @@
     # Cache Options
     parser.add_option("--external-memory-system", type="string",
                       help="use external ports of this port_type for caches")
+    parser.add_option("--tlm-memory", type="string",
+                      help="use external port for SystemC TLM cosimulation")
     parser.add_option("--caches", action="store_true")
     parser.add_option("--l2cache", action="store_true")
     parser.add_option("--fastmem", action="store_true")
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/Makefile	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,74 @@
+# Copyright (c) 2015, University of Kaiserslautern
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met:
+# 
+# 1. Redistributions of source code must retain the above copyright notice,
+#    this list of conditions and the following disclaimer.
+# 
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+# 
+# 3. Neither the name of the copyright holder nor the names of its
+#    contributors may be used to endorse or promote products derived from
+#    this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# 
+# Authors: Matthias Jung
+
+
+ARCH = ARM
+VARIANT = opt
+#VARIANT = debug
+
+SYSTEMC_INC = /opt/systemc/include
+SYSTEMC_LIB = /opt/systemc/lib-linux64
+
+CXXFLAGS = -I../../build/$(ARCH) -L../../build/$(ARCH)
+CXXFLAGS += -I../systemc/
+CXXFLAGS += -I$(SYSTEMC_INC) -L$(SYSTEMC_LIB)
+CXXFLAGS += -std=c++0x
+CXXFLAGS += -g
+CXXFLAGS += -DSC_INCLUDE_DYNAMIC_PROCESSES -DDEBUG -DTRACING_ON
+
+LIBS = -lgem5_$(VARIANT) -lsystemc
+
+ALL = gem5.$(VARIANT).sc
+
+all: $(ALL)
+
+.cc.o:
+	$(CXX) $(CXXFLAGS) -c -o $@ $<
+
+sc_gem5_control.o: ../systemc/sc_gem5_control.cc \
+	../systemc/sc_gem5_control.hh
+sc_logger.o: ../systemc/sc_logger.cc ../systemc/sc_logger.hh
+sc_module.o: ../systemc/sc_module.cc ../systemc/sc_module.hh
+sc_port.o: sc_port.cc sc_port.hh
+sc_target.o: sc_target.cc sc_target.hh
+stats.o: ../systemc/stats.cc ../systemc/stats.hh
+main.o: main.cc ../systemc/sc_logger.hh ../systemc/sc_module.hh \
+	../systemc/stats.hh
+
+gem5.$(VARIANT).sc: main.o ../systemc/stats.o ../systemc/sc_gem5_control.o \
+	../systemc/sc_logger.o ../systemc/sc_module.o sc_port.o sc_target.o
+	$(CXX) $(CXXFLAGS) -o $@ $^ $(LIBS)
+
+clean:
+	$(RM) $(ALL)
+	$(RM) *.o
+	$(RM) -r m5out
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/README
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/README	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,91 @@
+This directory contains a demo of a coupling between gem5 and SystemC-TLM.
+It is based on the gem5-systemc implementation in utils/systemc.
+First a simple example with gem5's traffic generator is shown, later an full
+system example.
+
+Files:
+
+    main.cc                -- demonstration top level
+    sc_port.{cc,hh}        -- coupling of gem5 and tlm port types
+    sc_target.{cc,hh}      -- an example TLM-AT memory module
+    tlm.py                 -- simple gem5 configuration
+    tgen.cfg               -- configuration file for the traceplayer
+
+Other Files will be used from utils/systemc example:
+
+    sc_logger.{cc,hh},
+    sc_module.{cc,hh},
+    sc_gem5_control.{cc,hh},
+    stats.{cc,hh}
+
+
+I. Traffic Generator Setup
+==========================
+
+To build:
+
+First build a normal gem5 (cxx-config not needed, Python needed).
+Second build gem5 as a library with cxx-config support and (optionally)
+without python.
+
+> cd ../..
+> scons build/ARM/gem5.opt
+> scons --with-cxx-config --without-python build/ARM/libgem5_opt.so
+> cd util/systemc_tlm
+
+Set a proper LD_LIBRARY_PATH e.g. for bash:
+> export LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/path/to/gem5/build/ARM/"
+
+Then edit the Makefile to set the paths for SystemC and run make
+
+> make
+
+Make a config file for the C++-configured gem5 using normal gem5
+
+> ../../build/ARM/gem5.opt ./tlm.py
+
+The message "fatal: Can't find port handler type 'tlm'" is okay.
+The configuration will be stored in the m5out/ directory
+
+The binary 'gem5.opt.sc' can now be used to load in the generated config
+file from the previous normal gem5 run.
+
+Try:
+
+> ./gem5.opt.sc m5out/config.ini -e 1000000
+
+It should run a simulation for 1us.
+
+To see more information what happens inside the TLM module use the -D flag:
+
+> ./gem5.opt.sc m5out/config.ini -e 1000000 -D
+
+To see more information about the port coupling use:
+
+> ./gem5.opt.sc m5out/config.ini -e 1000000 -d ExternalPort
+
+II. Full System Setup
+=====================
+
+Build gem5 as discribed in Section I. Then, make a config file for the
+C++-configured gem5 using normal gem5
+
+> ../../build/ARM/gem5.opt ../../configs/example/fs.py --tlm-memory=memory \
+  --cpu-type=timing --num-cpu=1 --mem-type=SimpleMemory --mem-size=512MB   \
+  --mem-channels=1  --caches --l2cache --machine-type=VExpress_EMM         \
+  --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb              \
+  --kernel=vmlinux.aarch32.ll_20131205.0-gem5                              \
+  --disk-image=linux-aarch32-ael.img
+
+The message "fatal: Can't find port handler type 'tlm'" is okay.
+The configuration will be stored in the m5out/ directory
+
+The binary 'gem5.opt.sc' can now be used to load in the generated config
+file from the previous normal gem5 run.
+
+Try:
+
+> ./gem5.opt.sc m5out/config.ini -o 2147483648
+
+The parameter -o specifies the begining of the memory region (0x80000000).
+The system should boot now.
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/main.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/main.cc	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+/**
+ * @file
+ *
+ *  Example top level file for SystemC-TLM integration with C++-only
+ *  instantiation.
+ *
+ */
+
+#include <tlm_utils/simple_target_socket.h>
+
+#include <cstdlib>
+#include <iomanip>
+#include <iostream>
+#include <sstream>
+#include <systemc>
+#include <tlm>
+#include <typeinfo>
+
+#include "base/statistics.hh"
+#include "base/str.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "sc_logger.hh"
+#include "sc_module.hh"
+#include "sc_port.hh"
+#include "sc_target.hh"
+#include "sim/cxx_config_ini.hh"
+#include "sim/cxx_manager.hh"
+#include "sim/init_signals.hh"
+#include "sim/serialize.hh"
+#include "sim/simulate.hh"
+#include "sim/stat_control.hh"
+#include "sim/system.hh"
+#include "stats.hh"
+
+void usage(const std::string &prog_name)
+{
+    std::cerr << "Usage: " << prog_name << (
+        " <config_file.ini> [ <option> ]\n\n"
+        "OPTIONS:\n"
+
+        "    -o <offset>                  -- set memory offset\n"
+        "    -p <object> <param> <value>  -- set a parameter\n"
+        "    -v <object> <param> <values> -- set a vector parameter from a\n"
+        "                                    comma separated values string\n"
+        "    -d <flag>                    -- set a debug flag\n"
+        "                                    (-<flag> clear a flag)\n"
+        "    -D                           -- debug on\n"
+        "    -e <ticks>                   -- end of simulation after a \n"
+        "                                    given number of ticks\n"
+        "\n"
+        );
+    std::exit(EXIT_FAILURE);
+}
+
+class SimControl : public Gem5SystemC::Module
+{
+    protected:
+    int argc;
+    char **argv;
+    CxxConfigManager *config_manager;
+    Gem5SystemC::Logger logger;
+
+    Tick sim_end;
+    bool debug;
+    unsigned int offset;
+
+    public:
+    SC_HAS_PROCESS(SimControl);
+
+    SimControl(sc_core::sc_module_name name, int argc_, char **argv_);
+
+    void before_end_of_elaboration();
+
+    bool getDebugFlag() { return debug; }
+
+    unsigned int getOffset() { return offset; }
+
+    void run();
+};
+
+SimControl::SimControl(sc_core::sc_module_name name,
+                       int argc_,
+                       char **argv_) : Gem5SystemC::Module(name),
+                                       argc(argc_),
+                                       argv(argv_)
+{
+    SC_THREAD(run);
+
+    std::string prog_name(argv[0]);
+    unsigned int arg_ptr = 1;
+
+    if (argc == 1) {
+        usage(prog_name);
+    }
+
+    cxxConfigInit();
+    Gem5SystemC::registerSCPorts();
+
+    Trace::setDebugLogger(&logger);
+
+    Gem5SystemC::setTickFrequency();
+    sc_core::sc_set_time_resolution(1, sc_core::SC_PS);
+
+    Gem5SystemC::Module::setupEventQueues(*this);
+    initSignals();
+
+    Stats::initSimStats();
+    Stats::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
+
+    Trace::enabled = true;
+
+    sim_end = 0;
+    debug = false;
+    offset = 0;
+
+    const std::string config_file(argv[arg_ptr]);
+
+    CxxConfigFileBase *conf = new CxxIniFile();
+
+    if (!conf->load(config_file.c_str())) {
+        std::cerr << "Can't open config file: " << config_file << '\n';
+        std::exit(EXIT_FAILURE);
+    }
+    arg_ptr++;
+
+    config_manager = new CxxConfigManager(*conf);
+
+    try {
+        while (arg_ptr < argc) {
+            std::string option(argv[arg_ptr]);
+            arg_ptr++;
+            unsigned num_args = argc - arg_ptr;
+
+            if (option == "-p") {
+                if (num_args < 3) {
+                    usage(prog_name);
+                }
+
+                config_manager->setParam(argv[arg_ptr], argv[arg_ptr + 1],
+                argv[arg_ptr + 2]);
+                arg_ptr += 3;
+            } else if (option == "-v") {
+                std::vector<std::string> values;
+
+                if (num_args < 3) {
+                    usage(prog_name);
+                }
+                tokenize(values, argv[2], ',');
+                config_manager->setParamVector(argv[arg_ptr],
+                                               argv[arg_ptr],
+                                               values);
+                arg_ptr += 3;
+            } else if (option == "-d") {
+                if (num_args < 1) {
+                    usage(prog_name);
+                }
+                if (argv[arg_ptr][0] == '-') {
+                    clearDebugFlag(argv[arg_ptr] + 1);
+                } else {
+                    setDebugFlag(argv[arg_ptr]);
+                }
+                arg_ptr++;
+            } else if (option == "-e") {
+                if (num_args < 1) {
+                    usage(prog_name);
+                }
+                std::istringstream(argv[arg_ptr]) >> sim_end;
+                arg_ptr++;
+            } else if (option == "-D") {
+                debug = true;
+            } else if (option == "-o") {
+                if (num_args < 1) {
+                    usage(prog_name);
+                }
+                std::istringstream(argv[arg_ptr]) >> offset;
+                arg_ptr++;
+                /* code */
+            } else {
+                usage(prog_name);
+            }
+        }
+    } catch (CxxConfigManager::Exception &e) {
+        std::cerr << e.name << ": " << e.message << "\n";
+        std::exit(EXIT_FAILURE);
+    }
+
+    CxxConfig::statsEnable();
+    getEventQueue(0)->dump();
+
+    try {
+        config_manager->instantiate();
+    } catch (CxxConfigManager::Exception &e) {
+        std::cerr << "Config problem in sim object "
+                  << e.name << ": " << e.message << "\n";
+        std::exit(EXIT_FAILURE);
+    }
+}
+
+void
+SimControl::before_end_of_elaboration()
+{
+    try {
+        config_manager->initState();
+        config_manager->startup();
+    } catch (CxxConfigManager::Exception &e) {
+        std::cerr << "Config problem in sim object "
+            << e.name << ": " << e.message << "\n";
+        std::exit(EXIT_FAILURE);
+    }
+}
+
+void
+SimControl::run()
+{
+    GlobalSimLoopExitEvent *exit_event = NULL;
+
+    if(sim_end == 0) {
+        exit_event = simulate();
+    } else {
+        exit_event = simulate(sim_end);
+    }
+
+    std::cerr << "Exit at tick " << curTick()
+              << ", cause: " << exit_event->getCause() << '\n';
+
+    getEventQueue(0)->dump();
+
+#if TRY_CLEAN_DELETE
+    config_manager->deleteObjects();
+#endif
+}
+
+
+void
+reportHandler(const sc_core::sc_report &report,
+              const sc_core::sc_actions &actions)
+{
+    uint64_t systemc_time = report.get_time().value();
+    uint64_t gem5_time = curTick();
+
+    std::cerr << report.get_time();
+
+    if (gem5_time < systemc_time) {
+        std::cerr << " (<) ";
+    } else if (gem5_time > systemc_time) {
+        std::cerr << " (!) ";
+    } else {
+        std::cerr << " (=) ";
+    }
+
+    std::cerr << ": " << report.get_msg_type()
+              << ' ' << report.get_msg() << '\n';
+}
+
+
+int
+sc_main(int argc, char **argv)
+{
+    sc_core::sc_report_handler::set_handler(reportHandler);
+
+    SimControl sim_control("gem5", argc, argv);
+    Target *memory;
+
+    tlm::tlm_initiator_socket <> *mem_port =
+        dynamic_cast<tlm::tlm_initiator_socket<> *>(
+                    sc_core::sc_find_object("gem5.memory")
+                );
+
+    if (mem_port) {
+        SC_REPORT_INFO("sc_main", "Port Found");
+        unsigned long long int size = 512*1024*1024ULL;
+        //unsigned int offset = 0;
+        //unsigned int offset = 0x80000000;
+        memory = new Target("memory",
+                            sim_control.getDebugFlag(),
+                            size,
+                            sim_control.getOffset());
+
+        memory->socket.bind(*mem_port);
+    } else {
+        SC_REPORT_FATAL("sc_main", "Port Not Found");
+        std::exit(EXIT_FAILURE);
+    }
+
+    sc_core::sc_start();
+
+    SC_REPORT_INFO("sc_main", "End of Simulation");
+
+    return EXIT_SUCCESS;
+}
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/sc_port.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/sc_port.hh	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#ifndef __SIM_SC_PORT_HH__
+#define __SIM_SC_PORT_HH__
+
+#include <tlm_utils/simple_initiator_socket.h>
+
+#include <map>
+#include <systemc>
+#include <tlm>
+
+#include "mem/external_slave.hh"
+#include "sc_module.hh"
+
+namespace Gem5SystemC
+{
+
+class GSPort : public tlm::tlm_initiator_socket<>,
+        public tlm::tlm_bw_transport_if<>,
+        public ExternalSlave::Port
+{
+  public:
+    class Transaction
+    {
+      public:
+        GSPort &port;
+
+        /** Unique debugging sequence number */
+        uint64_t seqNum;
+
+        /**
+         * Transaction contains the initiating gem5 packet, the tlm payload
+         * populated from that packet on a request and from which response
+         * state needs to be packed into the packet
+         */
+        PacketPtr packet;
+        tlm::tlm_generic_payload payload;
+
+        /** Last TLM transaction phase.  Updated by all fw/bw calls */
+        tlm::tlm_phase phase;
+
+        /** Return value of fw(BEGIN_REQ) call */
+        tlm::tlm_sync_enum requestReturn;
+
+        /** Last annotated delay */
+        sc_core::sc_time requestDelay;
+
+        /** Time of the next scheduled event */
+        Tick nextEventTick;
+
+        /**
+         * Has this Transaction received a response
+         * (a phase past BEGIN_RESP)
+         */
+        bool responded;
+
+        Transaction(GSPort &port_);
+
+        /**
+         * Send a gem5 timing response on port after the packet has been
+         * suitably updated
+         */
+        bool sendTimingResp();
+
+        /** Send TLM END_RESP */
+        void sendEndResp();
+
+        /** Callback function for the 'Fake Payload Event Queue' */
+        void payloadEventQueueCallback();
+
+        /** Send a request retry to the initiator */
+        void sendReqRetry() { port.sendRetryReq(); }
+
+        /** Send an nb_transport_fw message for this transaction */
+        void nb_fw();
+
+        /** Send an b_transport message for this transaction */
+        void b_fw();
+
+        /** Send an transport_dbg message for this transaction */
+        void dbg();
+
+        /** Debug messages based on the packet contents or payload phase */
+        void packetMessage(const std::string &message);
+        void payloadMessage(const std::string &message,
+        bool show_return, bool show_response);
+    };
+
+    /**
+     * All calls into gem5 are implemented as scheduled Events so that event
+     * priority can be (at least partly) enforced and gem5 will only process
+     * events at the correct time
+     */
+    class ToGem5Event : public Event
+    {
+        public:
+        GSPort &port;
+        const std::string eventName;
+        void (Transaction::* handler)();
+
+        protected:
+        Transaction *transaction;
+
+        void process() { (transaction->*handler)(); }
+
+        public:
+        const std::string name() const { return eventName; }
+
+        ToGem5Event(
+            GSPort &port_,
+            void (Transaction::* handler_)(),
+            const std::string &event_name) :
+            port(port_),
+            eventName(event_name),
+            handler(handler_)
+        { }
+
+        /// Schedule an event into gem5
+        void schedule(Transaction *transaction_,
+                      bool notify,
+                      sc_core::sc_time delay);
+    };
+
+    /**
+     * A 'Fake Payload Event Queue', similar to the TLM PEQs. This will help
+     * that gem5 behaves like a normal TLM Initiator
+     */
+    ToGem5Event payloadEventQueue;
+
+    /** Counter for transaction sequence numbers */
+    uint64_t transactionSeqNum;
+
+    /**
+     * A transaction after BEGIN_REQ has been sent but before END_REQ, which
+     * is blocking the request channel (Exlusion Rule, see IEEE1666)
+     */
+    Transaction *blockingRequest;
+
+    /**
+     * A response which has been asked to retry by gem5 and so is blocking
+     * the response channel
+     */
+    Transaction *blockingResponse;
+
+    /** Did another gem5 request arrive while the request was blocked? */
+    bool needToSendRequestRetry;
+
+    typedef std::map<tlm::tlm_generic_payload *, Transaction *>
+        TransactionMap;
+
+    /**
+     * Map of payload to Transaction for reuniting responses with
+     * Packets/Transactions. All created transaction which have not been
+     * freeTransaction-ed are in this map
+     */
+    TransactionMap payloadToTransactionMap;
+
+  protected:
+    /** The gem5 Port slave interface */
+    Tick recvAtomic(PacketPtr packet);
+    void recvFunctional(PacketPtr packet);
+    bool recvTimingReq(PacketPtr packet);
+    bool recvTimingSnoopResp(PacketPtr packet);
+    void recvRespRetry();
+    void recvFunctionalSnoop(PacketPtr packet);
+
+    /** The TLM initiator interface */
+    tlm::tlm_sync_enum nb_transport_bw(tlm::tlm_generic_payload& trans,
+                                       tlm::tlm_phase& phase,
+                                       sc_core::sc_time& t);
+
+    void invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
+                                   sc_dt::uint64 end_range);
+
+  public:
+    GSPort(const std::string &name_,
+           const std::string &systemc_name,
+           ExternalSlave &owner_);
+
+    /** Make a new transaction and allocate a sequence number */
+    Transaction *newTransaction();
+
+    /** Free a transaction */
+    void freeTransaction(Transaction *transaction);
+};
+
+void registerPort(const std::string &name, Port &port);
+
+void registerSCPorts();
+
+}
+
+#endif // __SIM_SC_PORT_HH__
diff -r 9141d87c7f71 -r 99159dd794b8 util/tlm/sc_port.cc
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/util/tlm/sc_port.cc	Fri Jun 05 17:35:00 2015 +0200
@@ -0,0 +1,582 @@
+/*
+ * Copyright (c) 2015, University of Kaiserslautern
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ *    contributors may be used to endorse or promote products derived from
+ *    this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Matthias Jung
+ */
+
+#include <cctype>
+#include <iomanip>
+#include <sstream>
+
+#include "debug/ExternalPort.hh"
+#include "sc_port.hh"
+
+namespace Gem5SystemC
+{
+
+/**
+ * DPRINTF with name disambiguation for objects which are both
+ * sc_objects and SimObjects
+ */
+#define SC_DPRINTFS(flag, obj, ...) do { \
+    DPRINTFS(flag, static_cast<const SimObject *>(obj), __VA_ARGS__); \
+} while (0)
+
+#define SC_DPRINTF(flag, ...) SC_DPRINTFS(flag, this, __VA_ARGS__)
+
+/**
+ * Test that gem5 is at the same time as SystemC
+ */
+#define CAUGHT_UP do { \
+    assert(curTick() == sc_core::sc_time_stamp().value()); \
+} while (0)
+
+/**
+ * TLM memory manager that does nothing.This is is needed because gem5 will
+ * currently handle the TLM transaction memory management.
+ * TODO: use better memory manager in combination with  * aquire() and
+ * release() to be fully TLM2.0 compliant
+ */
+class NoFreeMemoryManagement : public tlm::tlm_mm_interface
+{
+    void
+    free(tlm::tlm_generic_payload *)
+    {
+        /* Do nothing */
+    }
+};
+
+NoFreeMemoryManagement noFreeMemoryManagement;
+
+void
+spewPacket(std::ostream &os, PacketPtr packet)
+{
+    if (packet) {
+        os << (packet->isRead() ? " RD" : "");
+        os << (packet->isWrite() ? " WR" : "");
+        os << (packet->needsResponse() ? " NRP" : "");
+        os << (packet->isResponse() ? " RSP" : "");
+        os << (packet->isRequest() ? " REQ" : "");
+        os << (packet->isUpgrade() ? " UPG" : "");
+        os << (packet->isInvalidate() ? " INV" : "");
+        os << (packet->hasData() ? " DAT" : "");
+        os << (packet->isError() ? " ERR" : "");
+        os << (packet->isPrint() ? " PRI" : "");
+        os << (packet->isFlush() ? " FLU" : "");
+        os << (packet->needsExclusive() ? " EXC" : "");
+        os << (packet->memInhibitAsserted() ? " INH" : "");
+        os << (packet->sharedAsserted() ? " SHA" : "");
+        os << (packet->isExpressSnoop() ? " XSN" : "");
+        os << (packet->isSupplyExclusive() ? " SUX" : "");
+
+        if (packet->isRead() || packet->isWrite()) {
+            os << ' ' << packet->getSize() << ' ';
+            os << std::hex << "0x" << packet->getAddr() << std::dec;
+        }
+    }
+}
+
+void
+gem5RequestToGenPayload(PacketPtr packet,
+                        tlm::tlm_generic_payload &payload)
+{
+    payload.set_address(packet->getAddr());
+
+    /* memory management is currently done by gem5, not SystemC */
+    payload.set_mm(&noFreeMemoryManagement);
+
+    unsigned int size = packet->getSize();
+    unsigned char *data = packet->getPtr<unsigned char>();
+
+    payload.set_data_length(size);
+    payload.set_streaming_width(size);
+    payload.set_data_ptr(data);
+
+    if (packet->isRead()) {
+        payload.set_command(tlm::TLM_READ_COMMAND);
+    }
+    else if (packet->isWrite()) {
+        payload.set_command(tlm::TLM_WRITE_COMMAND);
+    }
+    else if (packet->isInvalidate()) {
+        /* Do nothing */
+    }
+    else {
+        std::cerr << "gem5ToSystemC: Can't handle packets other than R/W ";
+        spewPacket(std::cerr, packet);
+        std::cerr << "\n";
+    }
+}
+
+void
+GSPort::Transaction::packetMessage(const std::string &message)
+{
+    if (!DTRACE(ExternalPort)) {
+        return;
+    }
+
+    std::ostringstream os;
+
+    os << '(' << seqNum << ") " << message << ' ' << (void *) packet;
+
+    spewPacket(os, packet);
+
+    SC_DPRINTFS(ExternalPort, &(port.owner), "%s\n", os.str());
+}
+
+const char
+*tlmSyncEnumToString(tlm::tlm_sync_enum sync)
+{
+    switch (sync) {
+      case tlm::TLM_ACCEPTED:
+        return "TLM_ACCEPTED";
+        break;
+      case tlm::TLM_UPDATED:
+        return "TLM_UPDATED";
+        break;
+      case tlm::TLM_COMPLETED:
+        return "TLM_COMPLETED";
+        break;
+    }
+}
+
+void
+GSPort::Transaction::payloadMessage(const std::string &message,
+                                    bool show_return,
+                                    bool show_response)
+{
+    if (!DTRACE(ExternalPort)) {
+        return;
+    }
+
+    std::ostringstream os;
+
+    os << '(' << seqNum << ") " << message;
+    os << ' ' << payload.get_command();
+    os << ' ' << phase;
+
+    if (show_return) {
+        os << ' ' << tlmSyncEnumToString(requestReturn);
+    }
+
+    if (show_response) {
+        os << ' ' << payload.get_response_status();
+    }
+
+    SC_DPRINTFS(ExternalPort, &(port.owner), "%s\n", os.str());
+}
+
+/**
+ * Similar to TLM's blocking transport (LT)
+ */
+Tick
+GSPort::recvAtomic(PacketPtr packet)
+{
+    CAUGHT_UP;
+
+    Transaction *transaction = newTransaction();
+    transaction->packet = packet;
+    gem5RequestToGenPayload(transaction->packet, transaction->payload);
+
+    transaction->b_fw();
+
+    // FIXME: is this necessary
+    packet->makeResponse();
+
+    // FIXME:
+    return transaction->requestDelay.value();
+    //return 0;
+}
+
+/**
+ * Similar to TLM's debug transport
+ */
+void
+GSPort::recvFunctional(PacketPtr packet)
+{
+    Transaction *transaction = newTransaction();
+    transaction->packet = packet;
+    gem5RequestToGenPayload(transaction->packet, transaction->payload);
+
+    transaction->dbg();
+}
+
+bool
+GSPort::recvTimingSnoopResp(PacketPtr packet)
+{
+    /* Snooping should be implemented with tlm_dbg_transport */
+    fatal("SystemC FIXME, unimplemented function: recvTimingSnoopResp\n");
+    return false;
+}
+
+void
+GSPort::recvFunctionalSnoop(PacketPtr packet)
+{
+    /* Snooping should be implemented with tlm_dbg_transport */
+    fatal("SystemC FIXME, unimplemented function: recvFunctionalSnoop\n");
+}
+
+/**
+ *  Similar to TLM's non-blocking transport (AT)
+ */
+bool
+GSPort::recvTimingReq(PacketPtr packet)
+{
+    CAUGHT_UP;
+
+    /* We should never get a second request after noting that a retry is
+     * required */
+    assert(!needToSendRequestRetry);
+
+    /* FIXME screw coherency traffic */
+    if (packet->memInhibitAsserted())
+        return true;
+
+    /* Remember if a request comes in while we're blocked so that a retry
+     * can be sent to gem5 */
+    if (blockingRequest) {
+        needToSendRequestRetry = true;
+        return false;
+    }
+
+    /* Prepare the transaction, TODO: memory manager */
+    Transaction *transaction = newTransaction(); //
+    transaction->packet = packet;
+    transaction->phase = tlm::BEGIN_REQ;
+    gem5RequestToGenPayload(transaction->packet, transaction->payload);
+
+    /* Starting TLM non-blocking sequence (AT) Refer to IEEE1666-2011 SystemC
+     * Standard Page 507 for a visualisation of the procedure */
+    transaction->nb_fw();
+
+    if(transaction->requestReturn == tlm::TLM_ACCEPTED) {
+        assert(transaction->phase == tlm::BEGIN_REQ);
+        /* Accepted but is now blocking until END_REQ (exclusion rule)*/
+        blockingRequest = transaction;
+    } else if(transaction->requestReturn == tlm::TLM_UPDATED) {
+        /* The Timing annotation must be honored: */
+        assert(transaction->phase == tlm::END_REQ ||
+               transaction->phase == tlm::BEGIN_RESP);
+        payloadEventQueue.schedule(transaction,
+                                   true,
+                                   transaction->requestDelay);
+    } else if(transaction->requestReturn == tlm::TLM_COMPLETED) {
+        /* Transaction is over nothing has do be done. */
+        assert(transaction->phase == tlm::END_RESP);
+        freeTransaction(transaction);
+    }
+
+    return true;
+}
+
+void
+GSPort::recvRespRetry()
+{
+    CAUGHT_UP;
+
+    /* Retry a response */
+    assert(blockingResponse);
+
+    Transaction *transaction = blockingResponse;
+    blockingResponse = NULL;
+
+    transaction->payloadMessage("retry response", false, false);
+
+    bool need_retry = !transaction->sendTimingResp();
+
+    assert(!need_retry);
+
+    transaction->sendEndResp();
+}
+
+/**
+ * Deletes the Transaction and the containing the TLM payload that's the
+ * reason why currently no TLM memory manager is needed
+ */
+void
+GSPort::freeTransaction(Transaction *transaction)
+{
+    payloadToTransactionMap.erase(&(transaction->payload));
+    delete transaction;
+}
+
+void
+GSPort::Transaction::sendEndResp()
+{
+    phase = tlm::END_RESP;
+
+    nb_fw();
+
+    assert(requestReturn == tlm::TLM_COMPLETED ||
+           requestReturn == tlm::TLM_ACCEPTED);
+    port.freeTransaction(this);
+}
+
+void
+GSPort::Transaction::payloadEventQueueCallback()
+{
+    this->payloadMessage("payloadEventQueueCallback", false, true);
+
+    /* Normal END Request and Pre-emption of END_REQ with BEGIN_RESP */
+    if(phase == tlm::END_REQ ||
+            (this == port.blockingRequest && phase == tlm::BEGIN_RESP)) {
+        /* This transaction must have been blocking requests */
+        assert(this == port.blockingRequest);
+        port.blockingRequest = NULL;
+
+        /* Did another request arrive while blocked, schedule a retry */
+        if (port.needToSendRequestRetry) {
+            port.needToSendRequestRetry = false;
+            this->sendReqRetry();
+        }
+    } else if (phase == tlm::BEGIN_RESP) {
+        CAUGHT_UP;
+
+        assert(!port.blockingResponse);
+
+        bool need_retry;
+
+        assert(!responded);
+
+        if (packet->needsResponse()) {
+            packet->makeResponse();
+            need_retry = !sendTimingResp();
+        } else {
+            packetMessage("needs no response");
+            need_retry = false;
+        }
+
+        responded = !need_retry;
+
+        if (need_retry) {
+            packetMessage("need retry");
+            port.blockingResponse = this;
+        } else {
+            if (phase == tlm::BEGIN_RESP) {
+                // Send END_RESP and we're finished
+                this->sendEndResp();
+            }
+        }
+    } else {
+        fatal("nb_transport_bw invalid phase: %s", phase);
+    }
+}
+
+GSPort::Transaction::Transaction(GSPort &port_) :
+    port(port_),
+    seqNum(0),
+    packet(NULL),
+    requestReturn(tlm::TLM_COMPLETED),
+    nextEventTick(0),
+    responded(false)
+{
+}
+
+/**
+ * Allocates a new Transaction object
+ */
+GSPort::Transaction * GSPort::newTransaction()
+{
+    Transaction *transaction = new Transaction(*this);
+
+    transaction->seqNum = transactionSeqNum;
+    transactionSeqNum++;
+
+    payloadToTransactionMap[&(transaction->payload)] = transaction;
+
+    return transaction;
+}
+
+/**
+ *  This function does a non blocking transport forward to the TLM world
+ */
+void
+GSPort::Transaction::nb_fw()
+{
+    sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+
+    if (packet) {
+        packetMessage("pre nb_transport_fw (Packet)");
+    }
+    payloadMessage("pre nb_transport_fw", false, false);
+
+    requestReturn = port->nb_transport_fw(payload, phase, delay);
+    requestDelay = delay;
+
+    payloadMessage("post nb_transport_fw", true, true);
+}
+
+/**
+ *  This function does a blocking transport to the TLM world
+ */
+void
+GSPort::Transaction::b_fw()
+{
+    sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+
+    if (packet) {
+        packetMessage("pre b_transport (Packet)");
+    }
+    payloadMessage("pre b_transport", false, false);
+
+    port->b_transport(payload, delay);
+    requestDelay = delay;
+
+    payloadMessage("post b_transport", true, true);
+}
+
+/**
+ *  This function does a debug transport to the TLM world
+ */
+void
+GSPort::Transaction::dbg()
+{
+    sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
+
+    if (packet) {
+        packetMessage("pre transport_dbg (Packet)");
+    }
+    payloadMessage("pre transport_dbg", false, false);
+
+    unsigned int bytes = port->transport_dbg(payload);
+    if (bytes != payload.get_data_length()) {
+        fatal("debug transport only returned %d bytes for a request of %d",
+            bytes, payload.get_data_length());
+    }
+
+
+    payloadMessage("post transport_dbg", true, true);
+}
+
+void
+GSPort::ToGem5Event::schedule(Transaction *transaction_,
+                                   bool notify,
+                                   sc_core::sc_time delay)
+{
+    assert(!scheduled());
+
+    transaction = transaction_;
+
+    /* Get time from SystemC as this will alway be more up to date than
+     * gem5's */
+    transaction->nextEventTick =
+            sc_core::sc_time_stamp().value() + delay.value();
+
+    if (notify)
+        port.owner.wakeupEventQueue(transaction->nextEventTick);
+    else
+        CAUGHT_UP;
+
+    SC_DPRINTFS(ExternalPort, &(port.owner), "(%d) scheduling %s at"
+        " %d\n", transaction->seqNum, name(),
+        transaction->nextEventTick);
+    port.owner.schedule(this, transaction->nextEventTick);
+}
+
+bool
+GSPort::Transaction::sendTimingResp()
+{
+    payloadMessage("pre sendTimingResp", false, false);
+
+    assert(packet);
+
+    bool done = port.sendTimingResp(packet);
+    if (done){
+        packet = NULL;
+    }
+
+    payloadMessage("post sendTimingResp", false, false);
+
+    return done;
+}
+
+tlm::tlm_sync_enum
+GSPort::nb_transport_bw(tlm::tlm_generic_payload& payload,
+                        tlm::tlm_phase& phase,
+                        sc_core::sc_time& delay)
+{
+    /* Find the Transaction from the payload */
+    TransactionMap::iterator transaction_i =
+       payloadToTransactionMap.find(&payload);
+    assert(transaction_i != payloadToTransactionMap.end());
+    Transaction *transaction = (*transaction_i).second;
+
+    /* Update the transaction */
+    transaction->phase = phase;
+
+    /* Display debug infomation */
+    transaction->payloadMessage("nb_transport_bw", false, true);
+
+    /* Schedule an event in the fake payload event queue */
+    payloadEventQueue.schedule(transaction, true, delay);
+    return tlm::TLM_ACCEPTED;
+}
+
+void
+GSPort::invalidate_direct_mem_ptr(sc_dt::uint64 start_range,
+                                       sc_dt::uint64 end_range)
+{
+    fatal("SystemC FIXME, unimpl. function: invalidate_direct_mem_ptr\n");
+}
+
+GSPort::GSPort(const std::string &name_,
+    const std::string &systemc_name,
+    ExternalSlave &owner_) :
+    tlm::tlm_initiator_socket<>(systemc_name.c_str()),
+    ExternalSlave::Port(name_, owner_),
+    payloadEventQueue(*this, &Transaction::payloadEventQueueCallback, "PEQ"),
+    transactionSeqNum(1),
+    blockingRequest(NULL),
+    needToSendRequestRetry(false),
+    blockingResponse(NULL)
+{
+    m_export.bind(*this);
+}
+
+class GSPortHandler : public ExternalSlave::Handler
+{
+  public:
+    ExternalSlave::Port *getExternalPort( const std::string &name,
+                                          ExternalSlave &owner,
+                                          const std::string &port_data)
+    {
+        // This will make a new initiatiator port
+        return new GSPort(name, port_data, owner);
+    }
+};
+
+void
+registerSCPorts()
+{
+    ExternalSlave::registerHandler("tlm", new GSPortHandler);
+}
+
+}