diff -r fbdaa08aaa42 -r 4d7b7d5e972d src/arch/x86/insts/microop.cc
--- a/src/arch/x86/insts/microop.cc	Tue May 05 09:25:59 2015 -0700
+++ b/src/arch/x86/insts/microop.cc	Fri May 08 10:19:49 2015 +0100
@@ -55,7 +55,7 @@
           case ConditionTests::EZF:
             return ccflags.ezf;
           case ConditionTests::SZnZF:
-            return !(!ccflags.ezf & ccflags.zf);
+            return !(!ccflags.ezf && ccflags.zf);
           case ConditionTests::MSTRZ:
             panic("This condition is not implemented!");
           case ConditionTests::STRZ:
@@ -63,7 +63,7 @@
           case ConditionTests::MSTRC:
             panic("This condition is not implemented!");
           case ConditionTests::STRZnEZF:
-            return !ccflags.ezf & ccflags.zf;
+            return !ccflags.ezf && ccflags.zf;
                 //And no interrupts or debug traps are waiting
           case ConditionTests::OF:
             return ccflags.of;
@@ -88,7 +88,7 @@
           case ConditionTests::NotEZF:
             return !ccflags.ezf;
           case ConditionTests::NotSZnZF:
-            return !ccflags.ezf & ccflags.zf;
+            return !ccflags.ezf && ccflags.zf;
           case ConditionTests::NotMSTRZ:
             panic("This condition is not implemented!");
           case ConditionTests::NotSTRZ:
@@ -96,7 +96,7 @@
           case ConditionTests::NotMSTRC:
             panic("This condition is not implemented!");
           case ConditionTests::STRnZnEZF:
-            return !ccflags.ezf & !ccflags.zf;
+            return !ccflags.ezf && !ccflags.zf;
                 //And no interrupts or debug traps are waiting
           case ConditionTests::NotOF:
             return !ccflags.of;
diff -r fbdaa08aaa42 -r 4d7b7d5e972d src/arch/x86/isa_traits.hh
--- a/src/arch/x86/isa_traits.hh	Tue May 05 09:25:59 2015 -0700
+++ b/src/arch/x86/isa_traits.hh	Fri May 08 10:19:49 2015 +0100
@@ -68,7 +68,7 @@
     const bool CurThreadInfoImplemented = false;
     const int CurThreadInfoReg = -1;
 
-    const ExtMachInst NoopMachInst = {
+    const ExtMachInst NoopMachInst M5_VAR_USED = {
         0x0,                            // No legacy prefixes.
         0x0,                            // No rex prefix.
         { OneByteOpcode, 0x90 },          // One opcode byte, 0x90.
diff -r fbdaa08aaa42 -r 4d7b7d5e972d src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Tue May 05 09:25:59 2015 -0700
+++ b/src/cpu/base_dyn_inst.hh	Fri May 08 10:19:49 2015 +0100
@@ -258,22 +258,22 @@
     /** Flattened register index of the destination registers of this
      *  instruction.
      */
-    TheISA::RegIndex _flatDestRegIdx[TheISA::MaxInstDestRegs];
+    std::array<TheISA::RegIndex, TheISA::MaxInstDestRegs> _flatDestRegIdx;
 
     /** Physical register index of the destination registers of this
      *  instruction.
      */
-    PhysRegIndex _destRegIdx[TheISA::MaxInstDestRegs];
+    std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _destRegIdx;
 
     /** Physical register index of the source registers of this
      *  instruction.
      */
-    PhysRegIndex _srcRegIdx[TheISA::MaxInstSrcRegs];
+    std::array<PhysRegIndex, TheISA::MaxInstSrcRegs> _srcRegIdx;
 
     /** Physical register index of the previous producers of the
      *  architected destinations.
      */
-    PhysRegIndex _prevDestRegIdx[TheISA::MaxInstDestRegs];
+    std::array<PhysRegIndex, TheISA::MaxInstDestRegs> _prevDestRegIdx;
 
 
   public:
@@ -366,6 +366,7 @@
      */
     PhysRegIndex renamedDestRegIdx(int idx) const
     {
+        assert(TheISA::MaxInstDestRegs > idx);
         return _destRegIdx[idx];
     }
 
diff -r fbdaa08aaa42 -r 4d7b7d5e972d src/cpu/o3/dyn_inst.hh
--- a/src/cpu/o3/dyn_inst.hh	Tue May 05 09:25:59 2015 -0700
+++ b/src/cpu/o3/dyn_inst.hh	Fri May 08 10:19:49 2015 +0100
@@ -44,6 +44,8 @@
 #ifndef __CPU_O3_DYN_INST_HH__
 #define __CPU_O3_DYN_INST_HH__
 
+#include <array>
+
 #include "arch/isa_traits.hh"
 #include "config/the_isa.hh"
 #include "cpu/o3/cpu.hh"
@@ -108,13 +110,13 @@
 
   protected:
     /** Values to be written to the destination misc. registers. */
-    MiscReg _destMiscRegVal[TheISA::MaxMiscDestRegs];
+    std::array<MiscReg, TheISA::MaxMiscDestRegs> _destMiscRegVal;
 
     /** Indexes of the destination misc. registers. They are needed to defer
      * the write accesses to the misc. registers until the commit stage, when
      * the instruction is out of its speculative state.
      */
-    short _destMiscRegIdx[TheISA::MaxMiscDestRegs];
+    std::array<short, TheISA::MaxMiscDestRegs> _destMiscRegIdx;
 
     /** Number of destination misc. registers. */
     uint8_t _numDestMiscRegs;