diff -r fc12f4d657f0 -r 741e6f03697b configs/splash2/cluster.py
--- a/configs/splash2/cluster.py	Sun Oct 17 23:15:53 2010 -0700
+++ b/configs/splash2/cluster.py	Mon Oct 18 02:06:12 2010 -0700
@@ -234,7 +234,6 @@
     for cpu in cluster.cpus:
         cpu.icache_port = cluster.clusterbus.port
         cpu.dcache_port = cluster.clusterbus.port
-        cpu.mem = cluster.l1
 
 # ----------------------
 # Define the root
diff -r fc12f4d657f0 -r 741e6f03697b configs/splash2/run.py
--- a/configs/splash2/run.py	Sun Oct 17 23:15:53 2010 -0700
+++ b/configs/splash2/run.py	Mon Oct 18 02:06:12 2010 -0700
@@ -217,7 +217,6 @@
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = options.l1size, assoc = 1),
                                 L1(size = options.l1size, assoc = 4))
-    cpu.mem = cpu.dcache
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectMemPorts(system.toL2bus)