# Node ID cb151892ed2a265600833ff7fecd5bc6d69eab63
# Parent  88582222762baadb63fdc181c7f1ec9fcd85c5dd
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -149,6 +149,8 @@
   void deallocate(Address);
   AbstractCacheEntry lookup(Address);
   bool isTagPresent(Address);
+  Cycles getTagLatency();
+  Cycles getDataLatency();
   void setMRU(Address);
   void recordRequestType(CacheRequestType);
   bool checkResourceAvailable(CacheResourceType, Address);
diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh
--- a/src/mem/ruby/structures/BankedArray.hh
+++ b/src/mem/ruby/structures/BankedArray.hh
@@ -67,6 +67,7 @@
     // This is so we don't get aliasing on blocks being replaced
     bool tryAccess(int64 idx);
 
+    Cycles getLatency() const { return accessLatency; }
 };
 
 #endif
diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh
--- a/src/mem/ruby/structures/CacheMemory.hh
+++ b/src/mem/ruby/structures/CacheMemory.hh
@@ -91,6 +91,9 @@
     const AbstractCacheEntry* lookup(const Address& address) const;
 
     Cycles getLatency() const { return m_latency; }
+    Cycles getTagLatency() const { return tagArray.getLatency(); }
+    Cycles getDataLatency() const { return dataArray.getLatency(); }
+
 
     // Hook for checkpointing the contents of the cache
     void recordCacheContents(int cntrl, CacheRecorder* tr) const;