# Node ID 76608773b16d1e73e2a96cebdebdd793a21fce69 # Parent 15f1c291f866c42b7e86d88d016f76f93893cc66 diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -155,6 +156,10 @@ void recordRequestType(CacheRequestType); bool checkResourceAvailable(CacheResourceType, Address); + int getCacheSize(); + int getNumBlocks(); + Address getAddressAtIdx(int); + Scalar demand_misses; Scalar demand_hits; } diff --git a/src/mem/ruby/structures/CacheMemory.hh b/src/mem/ruby/structures/CacheMemory.hh --- a/src/mem/ruby/structures/CacheMemory.hh +++ b/src/mem/ruby/structures/CacheMemory.hh @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -131,6 +132,10 @@ Stats::Scalar numTagArrayStalls; Stats::Scalar numDataArrayStalls; + int getCacheSize() const { return m_cache_size; } + int getNumBlocks() const { return m_cache_num_sets * m_cache_assoc; } + Address getAddressAtIdx(int idx) const; + private: // convert a Address to its location in the cache int64 addressToCacheSet(const Address& address) const; diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -1,5 +1,6 @@ /* * Copyright (c) 1999-2012 Mark D. Hill and David A. Wood + * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -132,6 +133,29 @@ return -1; // Not found } +// Given an unique cache block identifier (idx): return the valid address +// stored by the cache block. If the block is invalid/notpresent, the +// function returns the 0 address +Address +CacheMemory::getAddressAtIdx(int idx) const +{ + Address tmp(0); + + int set = idx / m_cache_assoc; + assert(set < m_cache_num_sets); + + int way = idx - set * m_cache_assoc; + assert (way < m_cache_assoc); + + AbstractCacheEntry* entry = m_cache[set][way]; + if (entry == NULL || + entry->m_Permission == AccessPermission_Invalid || + entry->m_Permission == AccessPermission_NotPresent) { + return tmp; + } + return entry->m_Address; +} + bool CacheMemory::tryCacheAccess(const Address& address, RubyRequestType type, DataBlock*& data_ptr)