diff --git a/src/mem/packet.hh b/src/mem/packet.hh --- a/src/mem/packet.hh +++ b/src/mem/packet.hh @@ -12,7 +12,7 @@ * modified or unmodified, in source code or in binary form. * * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2010 Advanced Micro Devices, Inc. + * Copyright (c) 2010-15 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -109,6 +109,10 @@ SwapResp, MessageReq, MessageResp, + ReleaseReq, + ReleaseResp, + AcquireReq, + AcquireResp, // Error responses // @TODO these should be classified as responses rather than // requests; coding them as requests initially for backwards @@ -147,6 +151,8 @@ IsPrint, //!< Print state matching address (for debugging) IsFlush, //!< Flush the address from caches IsStoreAccess, //!< exclusive permission + IsAcquire, //!< Acquire operation + IsRelease, //!< Release operation NUM_COMMAND_ATTRIBUTES }; @@ -206,6 +212,8 @@ bool isPrint() const { return testCmdAttrib(IsPrint); } bool isFlush() const { return testCmdAttrib(IsFlush); } bool isStoreAccess() const { return testCmdAttrib(IsStoreAccess); } + bool isAcquire() const { return testCmdAttrib(IsAcquire); } + bool isRelease() const { return testCmdAttrib(IsRelease); } const Command responseCommand() const @@ -491,6 +499,8 @@ bool isPrint() const { return cmd.isPrint(); } bool isFlush() const { return cmd.isFlush(); } bool isStoreAccess() const { return cmd.isStoreAccess(); } + bool isAcquire() const { return cmd.isAcquire(); } + bool isRelease() const { return cmd.isRelease(); } // Snoop flags void assertMemInhibit() # Node ID 46fbb145d2150a384d5efe70f3da996dc0944c7c # Parent 003a85a6a6e3620cce5615e49a64e319752a5462 diff --git a/src/mem/packet.cc b/src/mem/packet.cc --- a/src/mem/packet.cc +++ b/src/mem/packet.cc @@ -12,7 +12,7 @@ * modified or unmodified, in source code or in binary form. * * Copyright (c) 2006 The Regents of The University of Michigan - * Copyright (c) 2010 Advanced Micro Devices, Inc. + * Copyright (c) 2010-13 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -158,6 +158,14 @@ MessageResp, "MessageReq" }, /* IntResp -- for interrupts */ { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" }, + /* ReleaseReq -- for release synchronization */ + { SET3(IsRelease, IsRequest, NeedsResponse), ReleaseResp, "ReleaseReq" }, + /* ReleaseResp -- for release synchronization */ + { SET2(IsRelease, IsResponse), InvalidCmd, "ReleaseResp" }, + /* AcquireReq -- for release synchronization */ + { SET3(IsAcquire, IsRequest, NeedsResponse), AcquireResp, "AcquireReq" }, + /* AcquireResp -- for release synchronization */ + { SET3(IsAcquire, IsResponse, NeedsResponse), InvalidCmd, "AcquireResp" }, /* InvalidDestError -- packet dest field invalid */ { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, /* BadAddressError -- memory address invalid */ diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm +++ b/src/mem/protocol/RubySlicc_Exports.sm @@ -137,6 +137,9 @@ NULL, desc="Invalid request type"; FLUSH, desc="Flush request type"; Store_Access, desc="Store Permission Prefetch"; + Release, desc="Release operation"; + Acquire, desc="Acquire opertion"; + AcquireRelease, desc="Acquire and Release opertion"; } enumeration(SequencerRequestType, desc="...", default="SequencerRequestType_NULL") { diff --git a/src/mem/request.hh b/src/mem/request.hh --- a/src/mem/request.hh +++ b/src/mem/request.hh @@ -12,6 +12,7 @@ * modified or unmodified, in source code or in binary form. * * Copyright (c) 2002-2005 The Regents of The University of Michigan + * Copyright (c) 2010-2015 Advanced Micro Devices, Inc. * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -85,7 +86,7 @@ class Request { public: - typedef uint32_t FlagsType; + typedef uint64_t FlagsType; typedef uint8_t ArchFlagsType; typedef ::Flags Flags; @@ -96,59 +97,63 @@ * architecture-specific code. For example, SPARC uses them to * represent ASIs. */ - static const FlagsType ARCH_BITS = 0x000000FF; + static const FlagsType ARCH_BITS = 0x00000000000000FF; /** The request was an instruction fetch. */ - static const FlagsType INST_FETCH = 0x00000100; + static const FlagsType INST_FETCH = 0x0000000000000100; /** The virtual address is also the physical address. */ - static const FlagsType PHYSICAL = 0x00000200; + static const FlagsType PHYSICAL = 0x0000000000000200; /** The request is an ALPHA VPTE pal access (hw_ld). */ - static const FlagsType VPTE = 0x00000400; + static const FlagsType VPTE = 0x0000000000000400; /** Use the alternate mode bits in ALPHA. */ - static const FlagsType ALTMODE = 0x00000800; + static const FlagsType ALTMODE = 0x0000000000000800; /** The request is to an uncacheable address. */ - static const FlagsType UNCACHEABLE = 0x00001000; + static const FlagsType UNCACHEABLE = 0x0000000000001000; /** This request is to a memory mapped register. */ - static const FlagsType MMAPPED_IPR = 0x00002000; + static const FlagsType MMAPPED_IPR = 0x0000000000002000; /** This request is a clear exclusive. */ - static const FlagsType CLEAR_LL = 0x00004000; + static const FlagsType CLEAR_LL = 0x0000000000004000; /** This request is made in privileged mode. */ - static const FlagsType PRIVILEGED = 0x00008000; + static const FlagsType PRIVILEGED = 0x0000000000008000; /** This is a write that is targeted and zeroing an entire cache block. * There is no need for a read/modify/write */ - static const FlagsType CACHE_BLOCK_ZERO = 0x00010000; + static const FlagsType CACHE_BLOCK_ZERO = 0x0000000000010000; /** The request should not cause a memory access. */ - static const FlagsType NO_ACCESS = 0x00080000; + static const FlagsType NO_ACCESS = 0x0000000000020000; /** This request will lock or unlock the accessed memory. When used with * a load, the access locks the particular chunk of memory. When used * with a store, it unlocks. The rule is that locked accesses have to be * made up of a locked load, some operation on the data, and then a locked * store. */ - static const FlagsType LOCKED_RMW = 0x00100000; + static const FlagsType LOCKED_RMW = 0x0000000000040000; /** The request is a Load locked/store conditional. */ - static const FlagsType LLSC = 0x00200000; + static const FlagsType LLSC = 0x0000000000080000; /** This request is for a memory swap. */ - static const FlagsType MEM_SWAP = 0x00400000; - static const FlagsType MEM_SWAP_COND = 0x00800000; + static const FlagsType MEM_SWAP = 0x0000000000100000; + static const FlagsType MEM_SWAP_COND = 0x0000000000200000; /** The request is a prefetch. */ - static const FlagsType PREFETCH = 0x01000000; + static const FlagsType PREFETCH = 0x0000000000400000; /** The request should be prefetched into the exclusive state. */ - static const FlagsType PF_EXCLUSIVE = 0x02000000; + static const FlagsType PF_EXCLUSIVE = 0x0000000000800000; /** The request should be marked as LRU. */ - static const FlagsType EVICT_NEXT = 0x04000000; + static const FlagsType EVICT_NEXT = 0x0000000001000000; + /** The request should be marked with ACQUIRE. */ + static const FlagsType ACQUIRE = 0x0000000002000000; + /** The request should be marked with RELEASE. */ + static const FlagsType RELEASE = 0x0000000004000000; /** The request should be handled by the generic IPR code (only * valid together with MMAPPED_IPR) */ - static const FlagsType GENERIC_IPR = 0x08000000; + static const FlagsType GENERIC_IPR = 0x0000000080000000; /** The request targets the secure memory space. */ - static const FlagsType SECURE = 0x10000000; + static const FlagsType SECURE = 0x0000000100000000; /** The request is a page table walk */ - static const FlagsType PT_WALK = 0x20000000; + static const FlagsType PT_WALK = 0x0000000200000000; /** These flags are *not* cleared when a Request object is reused (assigned a new address). */ @@ -627,12 +632,19 @@ bool isLLSC() const { return _flags.isSet(LLSC); } bool isPriv() const { return _flags.isSet(PRIVILEGED); } bool isLockedRMW() const { return _flags.isSet(LOCKED_RMW); } + bool isAcquire() const { return _flags.isSet(ACQUIRE); } + bool isRelease() const { return _flags.isSet(RELEASE); } + bool isAcquireRelease() const { + return _flags.isSet(RELEASE) && _flags.isSet(ACQUIRE); + } bool isSwap() const { return _flags.isSet(MEM_SWAP|MEM_SWAP_COND); } bool isCondSwap() const { return _flags.isSet(MEM_SWAP_COND); } bool isMmappedIpr() const { return _flags.isSet(MMAPPED_IPR); } bool isClearLL() const { return _flags.isSet(CLEAR_LL); } bool isSecure() const { return _flags.isSet(SECURE); } bool isPTWalk() const { return _flags.isSet(PT_WALK); } + void setAcquire() { _flags.set(ACQUIRE); } + void setRelease() { _flags.set(RELEASE); } }; #endif // __MEM_REQUEST_HH__