diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MESI_Three_Level.py --- a/configs/ruby/MESI_Three_Level.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MESI_Three_Level.py Sat Jul 25 12:25:46 2015 -0500 @@ -37,19 +37,11 @@ from Ruby import send_evicts # -# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class L0Cache(RubyCache): - latency = 1 - -class L1Cache(RubyCache): - latency = 5 - -# -# Note: the L2 Cache latency is not currently used -# -class L2Cache(RubyCache): - latency = 15 +class L0Cache(RubyCache): pass +class L1Cache(RubyCache): pass +class L2Cache(RubyCache): pass def define_options(parser): parser.add_option("--num-clusters", type="int", default=1, @@ -106,9 +98,11 @@ clk_domain=system.cpu[i].clk_domain, ruby_system = ruby_system) - cpu_seq = RubySequencer(version = i, icache = l0i_cache, - clk_domain=system.cpu[i].clk_domain, - dcache = l0d_cache, ruby_system = ruby_system) + cpu_seq = RubySequencer(version = i, + icache = l0i_cache, + dcache = l0d_cache, + clk_domain=system.cpu[i].clk_domain, + ruby_system = ruby_system) l0_cntrl.sequencer = cpu_seq diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MESI_Two_Level.py --- a/configs/ruby/MESI_Two_Level.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MESI_Two_Level.py Sat Jul 25 12:25:46 2015 -0500 @@ -35,16 +35,10 @@ from Ruby import send_evicts # -# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class L1Cache(RubyCache): - latency = 3 - -# -# Note: the L2 Cache latency is not currently used -# -class L2Cache(RubyCache): - latency = 15 +class L1Cache(RubyCache): pass +class L2Cache(RubyCache): pass def define_options(parser): return diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MI_example.py --- a/configs/ruby/MI_example.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MI_example.py Sat Jul 25 12:25:46 2015 -0500 @@ -35,10 +35,9 @@ from Ruby import send_evicts # -# Note: the cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class Cache(RubyCache): - latency = 3 +class Cache(RubyCache): pass def define_options(parser): return diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MOESI_CMP_directory.py --- a/configs/ruby/MOESI_CMP_directory.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MOESI_CMP_directory.py Sat Jul 25 12:25:46 2015 -0500 @@ -35,16 +35,10 @@ from Ruby import send_evicts # -# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class L1Cache(RubyCache): - latency = 3 - -# -# Note: the L2 Cache latency is not currently used -# -class L2Cache(RubyCache): - latency = 15 +class L1Cache(RubyCache): pass +class L2Cache(RubyCache): pass def define_options(parser): return diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MOESI_CMP_token.py --- a/configs/ruby/MOESI_CMP_token.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MOESI_CMP_token.py Sat Jul 25 12:25:46 2015 -0500 @@ -35,16 +35,10 @@ from Ruby import send_evicts # -# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class L1Cache(RubyCache): - latency = 2 - -# -# Note: the L2 Cache latency is not currently used -# -class L2Cache(RubyCache): - latency = 10 +class L1Cache(RubyCache): pass +class L2Cache(RubyCache): pass def define_options(parser): parser.add_option("--l1-retries", type="int", default=1, diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/structures/CacheMemory.hh --- a/src/mem/ruby/structures/CacheMemory.hh Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/structures/CacheMemory.hh Sat Jul 25 12:25:46 2015 -0500 @@ -90,8 +90,6 @@ AbstractCacheEntry* lookup(const Address& address); const AbstractCacheEntry* lookup(const Address& address) const; - Cycles getLatency() const { return m_latency; } - // Hook for checkpointing the contents of the cache void recordCacheContents(int cntrl, CacheRecorder* tr) const; @@ -144,8 +142,6 @@ CacheMemory& operator=(const CacheMemory& obj); private: - Cycles m_latency; - // Data Members (m_prefix) bool m_is_instruction_only_cache; diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/structures/CacheMemory.cc --- a/src/mem/ruby/structures/CacheMemory.cc Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/structures/CacheMemory.cc Sat Jul 25 12:25:46 2015 -0500 @@ -59,7 +59,6 @@ p->start_index_bit, p->ruby_system) { m_cache_size = p->size; - m_latency = p->latency; m_cache_assoc = p->assoc; m_policy = p->replacement_policy; m_start_index_bit = p->start_index_bit; diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/system/Sequencer.hh --- a/src/mem/ruby/system/Sequencer.hh Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/system/Sequencer.hh Sat Jul 25 12:25:46 2015 -0500 @@ -180,6 +180,13 @@ CacheMemory* m_dataCache_ptr; CacheMemory* m_instCache_ptr; + // The cache access latency for top-level caches (L0/L1). These are + // currently assessed at the beginning of each memory access through the + // sequencer. + // TODO: Migrate these latencies into top-level cache controllers. + Cycles m_data_cache_hit_latency; + Cycles m_inst_cache_hit_latency; + typedef m5::hash_map RequestTable; RequestTable m_writeRequestTable; RequestTable m_readRequestTable; diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/system/Sequencer.cc Sat Jul 25 12:25:46 2015 -0500 @@ -58,6 +58,8 @@ m_instCache_ptr = p->icache; m_dataCache_ptr = p->dcache; + m_data_cache_hit_latency = p->dcache_hit_latency; + m_inst_cache_hit_latency = p->icache_hit_latency; m_max_outstanding_requests = p->max_outstanding_requests; m_deadlock_threshold = p->deadlock_threshold; @@ -65,6 +67,8 @@ assert(m_deadlock_threshold > 0); assert(m_instCache_ptr != NULL); assert(m_dataCache_ptr != NULL); + assert(m_data_cache_hit_latency > 0); + assert(m_inst_cache_hit_latency > 0); m_usingNetworkTester = p->using_network_tester; } @@ -691,12 +695,17 @@ msg->getPhysicalAddress(), RubyRequestType_to_string(secondary_type)); - Cycles latency(0); // initialzed to an null value - + // The Sequencer currently assesses instruction and data cache hit latency + // for the top-level caches at the beginning of a memory access. + // TODO: Eventually, this latency should be moved to represent the actual + // cache access latency portion of the memory access. This will require + // changing cache controller protocol files to assess the latency on the + // access response path. + Cycles latency(0); // Initialize to zero to catch misconfigured latency if (secondary_type == RubyRequestType_IFETCH) - latency = m_instCache_ptr->getLatency(); + latency = m_inst_cache_hit_latency; else - latency = m_dataCache_ptr->getLatency(); + latency = m_data_cache_hit_latency; // Send the message to the cache controller assert(latency > 0); diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/system/Sequencer.py Sat Jul 25 12:25:46 2015 -0500 @@ -61,6 +61,12 @@ icache = Param.RubyCache("") dcache = Param.RubyCache("") + # Cache latencies currently assessed at the beginning of each access + # NOTE: Setting these values to a value greater than one will result in + # O3 CPU pipeline bubbles and negatively impact performance + # TODO: Latencies should be migrated into each top-level cache controller + icache_hit_latency = Param.Cycles(1, "Inst cache hit latency") + dcache_hit_latency = Param.Cycles(1, "Data cache hit latency") max_outstanding_requests = Param.Int(16, "max requests (incl. prefetches) outstanding") deadlock_threshold = Param.Cycles(500000, diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/MOESI_hammer.py --- a/configs/ruby/MOESI_hammer.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/MOESI_hammer.py Sat Jul 25 12:25:46 2015 -0500 @@ -35,22 +35,14 @@ from Ruby import send_evicts # -# Note: the L1 Cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class L1Cache(RubyCache): - latency = 2 - +class L1Cache(RubyCache): pass +class L2Cache(RubyCache): pass # -# Note: the L2 Cache latency is not currently used +# Probe filter is a cache # -class L2Cache(RubyCache): - latency = 10 - -# -# Probe filter is a cache, latency is not used -# -class ProbeFilter(RubyCache): - latency = 1 +class ProbeFilter(RubyCache): pass def define_options(parser): parser.add_option("--allow-atomic-migration", action="store_true", diff -r cafae9abd4e4 -r cf3a413d2c38 configs/ruby/Network_test.py --- a/configs/ruby/Network_test.py Fri Jul 24 12:25:23 2015 -0700 +++ b/configs/ruby/Network_test.py Sat Jul 25 12:25:46 2015 -0500 @@ -34,10 +34,9 @@ from Ruby import create_topology # -# Note: the cache latency is only used by the sequencer on fast path hits +# Declare caches used by the protocol # -class Cache(RubyCache): - latency = 3 +class Cache(RubyCache): pass def define_options(parser): return diff -r cafae9abd4e4 -r cf3a413d2c38 src/mem/ruby/structures/Cache.py --- a/src/mem/ruby/structures/Cache.py Fri Jul 24 12:25:23 2015 -0700 +++ b/src/mem/ruby/structures/Cache.py Sat Jul 25 12:25:46 2015 -0500 @@ -36,7 +36,6 @@ cxx_class = 'CacheMemory' cxx_header = "mem/ruby/structures/CacheMemory.hh" size = Param.MemorySize("capacity in bytes"); - latency = Param.Cycles(""); assoc = Param.Int(""); replacement_policy = Param.String("PSEUDO_LRU", ""); start_index_bit = Param.Int(6, "index start, default 6 for 64-byte line");