# Node ID 5dd0809b96627bf398900c797d0dc2f128e1201e
# Parent  d02b45a554b52c68cce41e1b3895fb8582a639dd
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -63,10 +63,12 @@
         MicroHalt(ExtMachInst _machInst, const char * instMnem,
                 uint64_t setFlags) :
             X86MicroopBase(_machInst, "halt", instMnem,
-                           setFlags | (ULL(1) << StaticInst::IsNonSpeculative) |
-                           (ULL(1) << StaticInst::IsQuiesce),
+                           setFlags,
                            No_OpClass)
         {
+            flags[IsSerializeBefore] = 1;
+            flags[IsNonSpeculative] = 1;
+            flags[IsQuiesce] = 1;
         }
 
         %(BasicExecDeclare)s
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -312,9 +312,6 @@
     /** Setup CPU to insert a thread's context */
     void insertThread(ThreadID tid);
 
-    /** Remove all of a thread's context from CPU */
-    void removeThread(ThreadID tid);
-
     /** Count the Total Instructions Committed in the CPU. */
     virtual Counter totalInsts() const;
 
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -704,6 +704,7 @@
 void
 FullO3CPU<Impl>::activateContext(ThreadID tid)
 {
+    DPRINTF(O3CPU, "[tid: %i]: Activating Thread Context.\n", tid);
     assert(!switchedOut());
 
     // Needs to set each stage to running as well.
@@ -746,6 +747,19 @@
 
     deactivateThread(tid);
 
+    // Squash Throughout Pipeline
+    DynInstPtr inst = commit.rob->readHeadInst(tid);
+    InstSeqNum squash_seq_num = inst->seqNum;
+    fetch.squash(inst->pcState().npc(), squash_seq_num, inst, tid);
+    decode.squash(tid);
+    rename.squash(squash_seq_num, tid);
+    iew.squash(tid);
+    iew.ldstQueue.squash(squash_seq_num, tid);
+    commit.rob->squash(squash_seq_num, tid);
+
+    assert(iew.instQueue.getCount(tid) == 0);
+    assert(iew.ldstQueue.getCount(tid) == 0);
+
     // If this was the last thread then unschedule the tick event.
     if (activeThreads.size() == 0) {
         unscheduleTickEvent();
@@ -760,12 +774,7 @@
 void
 FullO3CPU<Impl>::haltContext(ThreadID tid)
 {
-    //For now, this is the same as deallocate
-    DPRINTF(O3CPU,"[tid:%i]: Halt Context called. Deallocating", tid);
-    assert(!switchedOut());
-
-    deactivateThread(tid);
-    removeThread(tid);
+    suspendContext(tid);
 }
 
 template <class Impl>
@@ -824,72 +833,6 @@
 }
 
 template <class Impl>
-void
-FullO3CPU<Impl>::removeThread(ThreadID tid)
-{
-    DPRINTF(O3CPU,"[tid:%i] Removing thread context from CPU.\n", tid);
-
-    // Copy Thread Data From RegFile
-    // If thread is suspended, it might be re-allocated
-    // this->copyToTC(tid);
-
-
-    // @todo: 2-27-2008: Fix how we free up rename mappings
-    // here to alleviate the case for double-freeing registers
-    // in SMT workloads.
-
-    // Unbind Int Regs from Rename Map
-    for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(ireg);
-        scoreboard.unsetReg(phys_reg);
-        freeList.addReg(phys_reg);
-    }
-
-    // Unbind Float Regs from Rename Map
-    int max_reg = TheISA::FP_Reg_Base + TheISA::NumFloatRegs;
-    for (int freg = TheISA::FP_Reg_Base; freg < max_reg; freg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(freg);
-        scoreboard.unsetReg(phys_reg);
-        freeList.addReg(phys_reg);
-    }
-
-    // Unbind condition-code Regs from Rename Map
-    max_reg = TheISA::CC_Reg_Base + TheISA::NumCCRegs;
-    for (int creg = TheISA::CC_Reg_Base; creg < max_reg; creg++) {
-        PhysRegIndex phys_reg = renameMap[tid].lookup(creg);
-        scoreboard.unsetReg(phys_reg);
-        freeList.addReg(phys_reg);
-    }
-
-    // Squash Throughout Pipeline
-    DynInstPtr inst = commit.rob->readHeadInst(tid);
-    InstSeqNum squash_seq_num = inst->seqNum;
-    fetch.squash(0, squash_seq_num, inst, tid);
-    decode.squash(tid);
-    rename.squash(squash_seq_num, tid);
-    iew.squash(tid);
-    iew.ldstQueue.squash(squash_seq_num, tid);
-    commit.rob->squash(squash_seq_num, tid);
-
-
-    assert(iew.instQueue.getCount(tid) == 0);
-    assert(iew.ldstQueue.getCount(tid) == 0);
-
-    // Reset ROB/IQ/LSQ Entries
-
-    // Commented out for now.  This should be possible to do by
-    // telling all the pipeline stages to drain first, and then
-    // checking until the drain completes.  Once the pipeline is
-    // drained, call resetEntries(). - 10-09-06 ktlim
-/*
-    if (activeThreads.size() >= 1) {
-        commit.rob->resetEntries();
-        iew.resetEntries();
-    }
-*/
-}
-
-template <class Impl>
 Fault
 FullO3CPU<Impl>::hwrei(ThreadID tid)
 {
diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh
--- a/src/cpu/o3/decode_impl.hh
+++ b/src/cpu/o3/decode_impl.hh
@@ -335,6 +335,8 @@
 
     // Squash instructions up until this one
     cpu->removeInstsUntil(squash_seq_num, tid);
+
+    stalls[tid].rename = false;
 }
 
 template<class Impl>
@@ -382,6 +384,8 @@
         skidBuffer[tid].pop();
     }
 
+    stalls[tid].rename = false;
+
     return squash_count;
 }
 
@@ -483,7 +487,6 @@
     }
 
     if (fromRename->renameUnblock[tid]) {
-        assert(stalls[tid].rename);
         stalls[tid].rename = false;
     }
 }
diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh
+++ b/src/cpu/o3/fetch_impl.hh
@@ -328,10 +328,6 @@
 {
     assert(priorityList.empty());
     resetStage();
-
-    // Fetch needs to start fetching instructions at the very beginning,
-    // so it must start up in active state.
-    switchToActive();
 }
 
 template<class Impl>
@@ -787,6 +783,8 @@
     // some opportunities to handle interrupts may be missed.
     delayedCommit[tid] = true;
 
+    stalls[tid].decode = false;
+
     ++fetchSquashCycles;
 }
 
@@ -986,7 +984,6 @@
     }
 
     if (fromDecode->decodeUnblock[tid]) {
-        assert(stalls[tid].decode);
         assert(!fromDecode->decodeBlock[tid]);
         stalls[tid].decode = false;
     }