# Node ID 716172760d78251d37334eb18707affb82e1e7d9
# Parent  e4f97e27c2832d9d66d780c1c596a4ec8e0e9f76
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -292,11 +292,13 @@
 
     // Initialize rename map to assign physical registers to the
     // architectural registers for active threads only.
+    PhysRegIndex zero_phys_reg = freeList.getIntReg();
     for (ThreadID tid = 0; tid < active_threads; tid++) {
         for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
             // Note that we can't use the rename() method because we don't
             // want special treatment for the zero register at this point
-            PhysRegIndex phys_reg = freeList.getIntReg();
+            PhysRegIndex phys_reg = (ridx != TheISA::ZeroReg) ?
+                                    freeList.getIntReg() : zero_phys_reg;
             renameMap[tid].setIntEntry(ridx, phys_reg);
             commitRenameMap[tid].setIntEntry(ridx, phys_reg);
         }