# Node ID d90ce6b66612cc075d0ef45c11cfe092aa249a4a
# Parent  27ededc60d3884fbd87f05011113e78d5dcf8fca
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -694,17 +694,23 @@
 }
 
 void
-BaseCPU::doMonitor(PacketPtr pkt) {
+BaseCPU::doMonitor(PacketPtr pkt)
+{
     assert(pkt->req->hasPaddr());
+
+    // Since LSQ accesses are monitored, we are aligning the address
+    // on a cache-line basis
+    uint64_t mask = ~((uint64_t)(cacheLineSize() - 1));
+    Addr paddr = pkt->getAddr() & mask;
+    DPRINTF(Mwait, "pAddr=0x%lx\n", paddr);
+
     for (ThreadID tid = 0; tid < numThreads; tid++) {
-        if (addressMonitor[tid].armed &&
-            addressMonitor[tid].waiting) {
-            if (addressMonitor[tid].pAddr == pkt->getAddr()) {
+        AddressMonitor &mon = addressMonitor[tid];
+        if (mon.armed && mon.waiting && (mon.pAddr == paddr)) {
                 DPRINTF(Mwait,"pAddr=0x%lx invalidated: waking up core\n",
-                        pkt->getAddr());
-                addressMonitor[tid].waiting = false;
+                        paddr);
+                mon.waiting = false;
                 activateContext(tid);
-            }
         }
     }
 }
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -108,6 +108,12 @@
         return;
     }
 
+    if (!inst->isSquashed() && inst->isStore()) {
+        // In case of split accesses, we will monitor both packets
+        // completing the access
+        cpu->doMonitor(pkt);
+    }
+
     // If this is a split access, wait until all packets are received.
     if (TheISA::HasUnalignedMemAcc && !state->complete()) {
         return;