diff -r fbdaa08aaa42 -r c7a3878f67fe src/arch/x86/isa.cc
--- a/src/arch/x86/isa.cc	Tue May 05 09:25:59 2015 -0700
+++ b/src/arch/x86/isa.cc	Tue Jun 09 14:27:12 2015 +0200
@@ -129,11 +129,13 @@
     // Make sure we're not dealing with an illegal control register.
     // Instructions should filter out these indexes, and nothing else should
     // attempt to read them directly.
-    assert( miscReg != MISCREG_CR1 &&
-            !(miscReg > MISCREG_CR4 &&
-              miscReg < MISCREG_CR8) &&
-            !(miscReg > MISCREG_CR8 &&
-              miscReg <= MISCREG_CR15));
+    assert(miscReg >= MISCREG_CR0 &&
+           miscReg < NUM_MISCREGS &&
+           miscReg != MISCREG_CR1 &&
+           !(miscReg > MISCREG_CR4 &&
+             miscReg < MISCREG_CR8) &&
+           !(miscReg > MISCREG_CR8 &&
+             miscReg <= MISCREG_CR15));
 
     return regVal[miscReg];
 }
@@ -160,11 +162,48 @@
     // Make sure we're not dealing with an illegal control register.
     // Instructions should filter out these indexes, and nothing else should
     // attempt to write to them directly.
-    assert( miscReg != MISCREG_CR1 &&
-            !(miscReg > MISCREG_CR4 &&
-              miscReg < MISCREG_CR8) &&
-            !(miscReg > MISCREG_CR8 &&
-              miscReg <= MISCREG_CR15));
+    assert(miscReg >= MISCREG_CR0 &&
+           miscReg < NUM_MISCREGS &&
+           miscReg != MISCREG_CR1 &&
+           !(miscReg > MISCREG_CR4 &&
+             miscReg < MISCREG_CR8) &&
+           !(miscReg > MISCREG_CR8 &&
+             miscReg <= MISCREG_CR15));
+
+    HandyM5Reg m5Reg = readMiscRegNoEffect(MISCREG_M5_REG);
+    switch (miscReg) {
+      case MISCREG_FSW:
+        val &= (1ULL << 16) - 1;
+        regVal[miscReg] = val;
+        miscReg = MISCREG_X87_TOP;
+        val <<= 11;
+      case MISCREG_X87_TOP:
+        val &= (1ULL << 3) - 1;
+        break;
+      case MISCREG_FTW:
+        val &= (1ULL << 8) - 1;
+        break;
+      case MISCREG_FCW:
+      case MISCREG_FOP:
+        val &= (1ULL << 16) - 1;
+        break;
+      case MISCREG_MXCSR:
+        val &= (1ULL << 32) - 1;
+        break;
+      case MISCREG_FISEG:
+      case MISCREG_FOSEG:
+        if (m5Reg.submode != SixtyFourBitMode)
+            val &= (1ULL << 16) - 1;
+        break;
+      case MISCREG_FIOFF:
+      case MISCREG_FOOFF:
+        if (m5Reg.submode != SixtyFourBitMode)
+            val &= (1ULL << 32) - 1;
+        break;
+      default:
+        break;
+    }
+
     regVal[miscReg] = val;
 }
 
diff -r fbdaa08aaa42 -r c7a3878f67fe src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py
--- a/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py	Tue May 05 09:25:59 2015 -0700
+++ b/src/arch/x86/isa/insts/simd128/integer/save_and_restore_state/save_and_restore_state.py	Tue Jun 09 14:27:12 2015 +0200
@@ -122,9 +122,6 @@
     # FSW includes TOP when read
     ld t1, seg, %(mode)s, "DISPLACEMENT + 2", dataSize=2
     wrval fsw, t1
-    srli t1, t1, 11, dataSize=2
-    andi t1, t1, 0x7, dataSize=2
-    wrval "InstRegIndex(MISCREG_X87_TOP)", t1
 
     # FTW
     ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=1
diff -r fbdaa08aaa42 -r c7a3878f67fe src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
--- a/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py	Tue May 05 09:25:59 2015 -0700
+++ b/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py	Tue Jun 09 14:27:12 2015 +0200
@@ -36,9 +36,6 @@
 
     ld t1, seg, %(mode)s, "DISPLACEMENT + 4", dataSize=2
     wrval fsw, t1
-    srli t1, t1, 11, dataSize=2
-    andi t1, t1, 0x7, dataSize=2
-    wrval "InstRegIndex(MISCREG_X87_TOP)", t1
 
     ld t1, seg, %(mode)s, "DISPLACEMENT + 8", dataSize=2
     wrval ftw, t1