diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm	Wed Jun 17 19:51:33 2015 -0500
+++ b/src/mem/protocol/RubySlicc_Types.sm	Thu Jun 18 23:02:39 2015 -0500
@@ -157,10 +157,6 @@
   Scalar demand_hits;
 }
 
-structure (WireBuffer, inport="yes", outport="yes", external = "yes") {
-
-}
-
 structure (DMASequencer, external = "yes") {
   void ackCallback();
   void dataCallback(DataBlock);
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/ruby/SConscript
--- a/src/mem/ruby/SConscript	Wed Jun 17 19:51:33 2015 -0500
+++ b/src/mem/ruby/SConscript	Thu Jun 18 23:02:39 2015 -0500
@@ -126,7 +126,6 @@
 MakeInclude('structures/CacheMemory.hh')
 MakeInclude('system/DMASequencer.hh')
 MakeInclude('structures/DirectoryMemory.hh')
-MakeInclude('structures/WireBuffer.hh')
 MakeInclude('structures/PerfectCacheMemory.hh')
 MakeInclude('structures/PersistentTable.hh')
 MakeInclude('system/Sequencer.hh')
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/ruby/structures/SConscript
--- a/src/mem/ruby/structures/SConscript	Wed Jun 17 19:51:33 2015 -0500
+++ b/src/mem/ruby/structures/SConscript	Thu Jun 18 23:02:39 2015 -0500
@@ -37,11 +37,9 @@
 SimObject('DirectoryMemory.py')
 SimObject('RubyMemoryControl.py')
 SimObject('RubyPrefetcher.py')
-SimObject('WireBuffer.py')
 
 Source('DirectoryMemory.cc')
 Source('CacheMemory.cc')
-Source('WireBuffer.cc')
 Source('RubyMemoryControl.cc')
 Source('MemoryNode.cc')
 Source('PersistentTable.cc')
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/ruby/structures/WireBuffer.hh
--- a/src/mem/ruby/structures/WireBuffer.hh	Wed Jun 17 19:51:33 2015 -0500
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,102 +0,0 @@
-/*
- * Copyright (c) 2010 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author: Lisa Hsu
- *
- */
-
-#ifndef __MEM_RUBY_STRUCTURES_WIREBUFFER_HH__
-#define __MEM_RUBY_STRUCTURES_WIREBUFFER_HH__
-
-#include <iostream>
-#include <string>
-#include <vector>
-
-#include "mem/ruby/common/Consumer.hh"
-#include "mem/ruby/network/MessageBufferNode.hh"
-#include "params/RubyWireBuffer.hh"
-#include "sim/sim_object.hh"
-
-//////////////////////////////////////////////////////////////////////////////
-// This object was written to literally mimic a Wire in Ruby, in the sense
-// that there is no way for messages to get reordered en route on the WireBuffer.
-// With Message Buffers, even if randomization is off and ordered is on,
-// messages can arrive in different orders than they were sent because of
-// network issues. This mimics a Wire, such that that is not possible. This can
-// allow for messages between closely coupled controllers that are not actually
-// separated by a network in real systems to simplify coherence.
-/////////////////////////////////////////////////////////////////////////////
-
-class Message;
-
-class WireBuffer : public SimObject
-{
-  public:
-    typedef RubyWireBufferParams Params;
-    WireBuffer(const Params *p);
-    void init();
-
-    ~WireBuffer();
-
-    void wakeup();
-
-    void setConsumer(Consumer* consumer_ptr)
-    {
-        m_consumer_ptr = consumer_ptr;
-    }
-    Consumer* getConsumer() { return m_consumer_ptr; };
-    void setDescription(const std::string& name) { m_description = name; };
-    std::string getDescription() { return m_description; };
-
-    void enqueue(MsgPtr message, Cycles latency);
-    void dequeue();
-    const Message* peek();
-    MessageBufferNode peekNode();
-    void recycle();
-    bool isReady();
-    bool areNSlotsAvailable(int n) { return true; };  // infinite queue length
-
-    void print(std::ostream& out) const;
-    uint64_t m_msg_counter;
-
-  private:
-    // Private copy constructor and assignment operator
-    WireBuffer (const WireBuffer& obj);
-    WireBuffer& operator=(const WireBuffer& obj);
-
-    // data members
-    Consumer* m_consumer_ptr;  // Consumer to signal a wakeup()
-    std::string m_description;
-
-    // queues where memory requests live
-    std::vector<MessageBufferNode> m_message_queue;
-
-};
-
-std::ostream& operator<<(std::ostream& out, const WireBuffer& obj);
-
-#endif // __MEM_RUBY_STRUCTURES_WireBuffer_HH__
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/ruby/structures/WireBuffer.cc
--- a/src/mem/ruby/structures/WireBuffer.cc	Wed Jun 17 19:51:33 2015 -0500
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,158 +0,0 @@
-/*
- * Copyright (c) 2010 Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Author:  Lisa Hsu
- *
- */
-
-#include <algorithm>
-#include <functional>
-
-#include "base/cprintf.hh"
-#include "base/stl_helpers.hh"
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/structures/WireBuffer.hh"
-#include "mem/ruby/system/System.hh"
-
-using namespace std;
-
-// Output operator definition
-
-ostream&
-operator<<(ostream& out, const WireBuffer& obj)
-{
-    obj.print(out);
-    out << flush;
-    return out;
-}
-
-
-// ****************************************************************
-
-// CONSTRUCTOR
-WireBuffer::WireBuffer(const Params *p)
-    : SimObject(p)
-{
-    m_msg_counter = 0;
-}
-
-void
-WireBuffer::init()
-{
-}
-
-WireBuffer::~WireBuffer()
-{
-}
-
-void
-WireBuffer::enqueue(MsgPtr message, Cycles latency)
-{
-    m_msg_counter++;
-    Cycles current_time = g_system_ptr->curCycle();
-    Cycles arrival_time = current_time + latency;
-    assert(arrival_time > current_time);
-
-    MessageBufferNode thisNode(arrival_time, m_msg_counter, message);
-    m_message_queue.push_back(thisNode);
-    if (m_consumer_ptr != NULL) {
-        m_consumer_ptr->
-            scheduleEventAbsolute(g_system_ptr->clockPeriod() * arrival_time);
-    } else {
-        panic("No Consumer for WireBuffer! %s\n", *this);
-    }
-}
-
-void
-WireBuffer::dequeue()
-{
-    assert(isReady());
-    pop_heap(m_message_queue.begin(), m_message_queue.end(),
-        greater<MessageBufferNode>());
-    m_message_queue.pop_back();
-}
-
-const Message*
-WireBuffer::peek()
-{
-    MessageBufferNode node = peekNode();
-    Message* msg_ptr = node.m_msgptr.get();
-    assert(msg_ptr != NULL);
-    return msg_ptr;
-}
-
-MessageBufferNode
-WireBuffer::peekNode()
-{
-    assert(isReady());
-    MessageBufferNode req = m_message_queue.front();
-    return req;
-}
-
-void
-WireBuffer::recycle()
-{
-    // Because you don't want anything reordered, make sure the recycle latency
-    // is just 1 cycle. As a result, you really want to use this only in
-    // Wire-like situations because you don't want to deadlock as a result of
-    // being stuck behind something if you're not actually supposed to.
-    assert(isReady());
-    MessageBufferNode node = m_message_queue.front();
-    pop_heap(m_message_queue.begin(), m_message_queue.end(),
-        greater<MessageBufferNode>());
-
-    node.m_time = g_system_ptr->curCycle() + Cycles(1);
-    m_message_queue.back() = node;
-    push_heap(m_message_queue.begin(), m_message_queue.end(),
-        greater<MessageBufferNode>());
-    m_consumer_ptr->
-        scheduleEventAbsolute(g_system_ptr->clockPeriod() * node.m_time);
-}
-
-bool
-WireBuffer::isReady()
-{
-    return ((!m_message_queue.empty()) &&
-            (m_message_queue.front().m_time <= g_system_ptr->curCycle()));
-}
-
-void
-WireBuffer::print(ostream& out) const
-{
-}
-
-void
-WireBuffer::wakeup()
-{
-}
-
-WireBuffer *
-RubyWireBufferParams::create()
-{
-    return new WireBuffer(this);
-}
-
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/ruby/structures/WireBuffer.py
--- a/src/mem/ruby/structures/WireBuffer.py	Wed Jun 17 19:51:33 2015 -0500
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-# Copyright (c) 2010 Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Author: Lisa Hsu
-
-from m5.params import *
-from m5.SimObject import SimObject
-
-class RubyWireBuffer(SimObject):
-    type = 'RubyWireBuffer'
-    cxx_class = 'WireBuffer'
-    cxx_header = "mem/ruby/structures/WireBuffer.hh"
diff -r e2ca2db279c8 -r 4962564c4ce6 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py	Wed Jun 17 19:51:33 2015 -0500
+++ b/src/mem/slicc/symbols/StateMachine.py	Thu Jun 18 23:02:39 2015 -0500
@@ -38,7 +38,6 @@
                     "std::string": "String",
                     "bool": "Bool",
                     "CacheMemory": "RubyCache",
-                    "WireBuffer": "RubyWireBuffer",
                     "Sequencer": "RubySequencer",
                     "DirectoryMemory": "RubyDirectoryMemory",
                     "MemoryControl": "MemoryControl",