# Node ID 50a592eadc405aa5cd42aa4e0a93a76162f4aebc # Parent e560358a45e2836f1c0e67be647152dc33d3b7a5 diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm +++ b/src/mem/protocol/RubySlicc_Types.sm @@ -157,9 +157,9 @@ Scalar demand_hits; } -structure (WireBuffer, inport="yes", outport="yes", external = "yes") { - -} +//structure (WireBuffer, inport="yes", outport="yes", external = "yes") { +// +//} structure (DMASequencer, external = "yes") { void ackCallback(); diff --git a/src/mem/ruby/SConscript b/src/mem/ruby/SConscript --- a/src/mem/ruby/SConscript +++ b/src/mem/ruby/SConscript @@ -126,7 +126,7 @@ MakeInclude('structures/CacheMemory.hh') MakeInclude('system/DMASequencer.hh') MakeInclude('structures/DirectoryMemory.hh') -MakeInclude('structures/WireBuffer.hh') +#MakeInclude('structures/WireBuffer.hh') MakeInclude('structures/PerfectCacheMemory.hh') MakeInclude('structures/PersistentTable.hh') MakeInclude('system/Sequencer.hh') diff --git a/src/mem/ruby/common/Global.hh b/src/mem/ruby/common/Global.hh --- a/src/mem/ruby/common/Global.hh +++ b/src/mem/ruby/common/Global.hh @@ -35,9 +35,6 @@ #include "base/str.hh" #include "base/types.hh" -class RubySystem; -extern RubySystem* g_system_ptr; - class AbstractController; extern std::vector > g_abs_controls; diff --git a/src/mem/ruby/common/Global.cc b/src/mem/ruby/common/Global.cc --- a/src/mem/ruby/common/Global.cc +++ b/src/mem/ruby/common/Global.cc @@ -30,5 +30,4 @@ using namespace std; -RubySystem* g_system_ptr = 0; vector > g_abs_controls; diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh --- a/src/mem/ruby/network/MessageBuffer.hh +++ b/src/mem/ruby/network/MessageBuffer.hh @@ -45,12 +45,14 @@ #include "mem/ruby/common/Consumer.hh" #include "mem/ruby/network/MessageBufferNode.hh" #include "mem/ruby/slicc_interface/Message.hh" +#include "mem/ruby/system/System.hh" #include "mem/packet.hh" class MessageBuffer { public: - MessageBuffer(const std::string &name = ""); + MessageBuffer(RubySystem *rs, const std::string &name = ""); + RubySystem *ruby_system; std::string name() const { return m_name; } diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc --- a/src/mem/ruby/network/MessageBuffer.cc +++ b/src/mem/ruby/network/MessageBuffer.cc @@ -39,9 +39,10 @@ using namespace std; using m5::stl_helpers::operator<<; -MessageBuffer::MessageBuffer(const string &name) - : m_time_last_time_size_checked(0), m_time_last_time_enqueue(0), - m_time_last_time_pop(0), m_last_arrival_time(0) +MessageBuffer::MessageBuffer(RubySystem *rs, const string &name) + : ruby_system(rs), m_time_last_time_size_checked(0), + m_time_last_time_enqueue(0), m_time_last_time_pop(0), + m_last_arrival_time(0) { m_msg_counter = 0; m_consumer = NULL; @@ -191,7 +192,8 @@ } // If running a cache trace, don't worry about the last arrival checks - if (!RubySystem::getWarmupEnabled()) { + RubySystem *rs = ruby_system; + if (!rs->m_warmup_enabled) { m_last_arrival_time = arrival_time; } diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc --- a/src/mem/ruby/network/simple/SimpleNetwork.cc +++ b/src/mem/ruby/network/simple/SimpleNetwork.cc @@ -121,7 +121,7 @@ for (int i = 0; i < m_virtual_networks; i++) { // allocate a buffer - MessageBuffer* buffer_ptr = new MessageBuffer; + MessageBuffer* buffer_ptr = new MessageBuffer(params()->ruby_system); buffer_ptr->setOrdering(true); if (m_buffer_size > 0) { diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc --- a/src/mem/ruby/network/simple/Switch.cc +++ b/src/mem/ruby/network/simple/Switch.cc @@ -97,7 +97,7 @@ out[i]->setSender(this); } - MessageBuffer* buffer_ptr = new MessageBuffer; + MessageBuffer* buffer_ptr = new MessageBuffer(rs); // Make these queues ordered buffer_ptr->setOrdering(true); if (m_network_ptr->getBufferSize() > 0) { diff --git a/src/mem/ruby/network/simple/Throttle.cc b/src/mem/ruby/network/simple/Throttle.cc --- a/src/mem/ruby/network/simple/Throttle.cc +++ b/src/mem/ruby/network/simple/Throttle.cc @@ -129,7 +129,7 @@ DPRINTF(RubyNetwork, "throttle: %d my bw %d bw spent " "enqueueing net msg %d time: %lld.\n", m_node, getLinkBandwidth(), m_units_remaining[vnet], - g_system_ptr->curCycle()); + ruby_system->curCycle()); // Move the message in->dequeue(); diff --git a/src/mem/ruby/profiler/AddressProfiler.hh b/src/mem/ruby/profiler/AddressProfiler.hh --- a/src/mem/ruby/profiler/AddressProfiler.hh +++ b/src/mem/ruby/profiler/AddressProfiler.hh @@ -35,9 +35,9 @@ #include "mem/protocol/AccessType.hh" #include "mem/protocol/RubyRequest.hh" #include "mem/ruby/common/Address.hh" -#include "mem/ruby/common/Global.hh" #include "mem/ruby/common/Histogram.hh" #include "mem/ruby/profiler/AccessTraceForAddress.hh" +#include "mem/ruby/system/System.hh" class Set; @@ -47,10 +47,10 @@ typedef m5::hash_map AddressMap; public: - AddressProfiler(int num_of_sequencers); + AddressProfiler(int num_of_sequencers, RubySystem *rs); ~AddressProfiler(); - void printStats(std::ostream& out) const; + void printStats(std::ostream& out); void clearStats(); void addTraceSample(Address data_addr, Address pc_addr, @@ -70,6 +70,8 @@ void regStats(const std::string &name) {} void collateStats() {} + RubySystem *ruby_system; + private: // Private copy constructor and assignment operator AddressProfiler(const AddressProfiler& obj); @@ -100,7 +102,7 @@ void printSorted(std::ostream& out, int num_of_sequencers, const AddressProfiler::AddressMap &record_map, - std::string description); + std::string description, RubySystem* rs); inline std::ostream& operator<<(std::ostream& out, const AddressProfiler& obj) diff --git a/src/mem/ruby/profiler/AddressProfiler.cc b/src/mem/ruby/profiler/AddressProfiler.cc --- a/src/mem/ruby/profiler/AddressProfiler.cc +++ b/src/mem/ruby/profiler/AddressProfiler.cc @@ -64,7 +64,7 @@ void printSorted(ostream& out, int num_of_sequencers, const AddressMap &record_map, - string description) + string description, RubySystem *rs) { const int records_printed = 100; @@ -82,7 +82,7 @@ out << "Total_entries_" << description << ": " << record_map.size() << endl; - if (g_system_ptr->getProfiler()->getAllInstructions()) + if (rs->getProfiler()->getAllInstructions()) out << "Total_Instructions_" << description << ": " << misses << endl; else out << "Total_data_misses_" << description << ": " << misses << endl; @@ -143,7 +143,8 @@ << endl; } -AddressProfiler::AddressProfiler(int num_of_sequencers) +AddressProfiler::AddressProfiler(int num_of_sequencers, RubySystem *rs) + : ruby_system(rs) { m_num_of_sequencers = num_of_sequencers; clearStats(); @@ -166,7 +167,7 @@ } void -AddressProfiler::printStats(ostream& out) const +AddressProfiler::printStats(ostream& out) { if (m_hot_lines) { out << endl; @@ -183,20 +184,20 @@ out << "---------------" << endl; out << endl; printSorted(out, m_num_of_sequencers, m_dataAccessTrace, - "block_address"); + "block_address", ruby_system); out << endl; out << "Hot MacroData Blocks" << endl; out << "--------------------" << endl; out << endl; printSorted(out, m_num_of_sequencers, m_macroBlockAccessTrace, - "macroblock_address"); + "macroblock_address", ruby_system); out << "Hot Instructions" << endl; out << "----------------" << endl; out << endl; printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace, - "pc_address"); + "pc_address", ruby_system); } if (m_all_instructions) { @@ -205,7 +206,7 @@ out << "-------------------------" << endl; out << endl; printSorted(out, m_num_of_sequencers, m_programCounterAccessTrace, - "pc_address"); + "pc_address", ruby_system); out << endl; } @@ -222,7 +223,7 @@ out << endl; printSorted(out, m_num_of_sequencers, m_retryProfileMap, - "block_address"); + "block_address", ruby_system); out << endl; } } diff --git a/src/mem/ruby/profiler/Profiler.hh b/src/mem/ruby/profiler/Profiler.hh --- a/src/mem/ruby/profiler/Profiler.hh +++ b/src/mem/ruby/profiler/Profiler.hh @@ -66,7 +66,7 @@ class Profiler { public: - Profiler(const RubySystemParams *); + Profiler(const RubySystemParams *params, RubySystem *rs); ~Profiler(); void wakeup(); diff --git a/src/mem/ruby/profiler/Profiler.cc b/src/mem/ruby/profiler/Profiler.cc --- a/src/mem/ruby/profiler/Profiler.cc +++ b/src/mem/ruby/profiler/Profiler.cc @@ -61,17 +61,17 @@ using namespace std; using m5::stl_helpers::operator<<; -Profiler::Profiler(const RubySystemParams *p) +Profiler::Profiler(const RubySystemParams *p, RubySystem *rs) { m_hot_lines = p->hot_lines; m_all_instructions = p->all_instructions; - m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers); + m_address_profiler_ptr = new AddressProfiler(p->num_of_sequencers, rs); m_address_profiler_ptr->setHotLines(m_hot_lines); m_address_profiler_ptr->setAllInstructions(m_all_instructions); if (m_all_instructions) { - m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers); + m_inst_profiler_ptr = new AddressProfiler(p->num_of_sequencers, rs); m_inst_profiler_ptr->setHotLines(m_hot_lines); m_inst_profiler_ptr->setAllInstructions(m_all_instructions); } diff --git a/src/mem/ruby/slicc_interface/AbstractController.cc b/src/mem/ruby/slicc_interface/AbstractController.cc --- a/src/mem/ruby/slicc_interface/AbstractController.cc +++ b/src/mem/ruby/slicc_interface/AbstractController.cc @@ -40,7 +40,7 @@ m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), memoryPort(csprintf("%s.memory", name()), this, ""), - m_responseFromMemory_ptr(new MessageBuffer()) + m_responseFromMemory_ptr(new MessageBuffer(p->ruby_system)) { // Set the sender pointer of the response message buffer from the // memory controller. diff --git a/src/mem/ruby/structures/BankedArray.hh b/src/mem/ruby/structures/BankedArray.hh --- a/src/mem/ruby/structures/BankedArray.hh +++ b/src/mem/ruby/structures/BankedArray.hh @@ -35,6 +35,7 @@ #include #include "mem/ruby/common/TypeDefines.hh" +#include "mem/ruby/system/System.hh" #include "sim/core.hh" class BankedArray @@ -44,6 +45,7 @@ Cycles accessLatency; unsigned int bankBits; unsigned int startIndexBit; + RubySystem *ruby_system; class AccessRecord { @@ -62,7 +64,7 @@ public: BankedArray(unsigned int banks, Cycles accessLatency, - unsigned int startIndexBit); + unsigned int startIndexBit, RubySystem *rs); // Note: We try the access based on the cache index, not the address // This is so we don't get aliasing on blocks being replaced diff --git a/src/mem/ruby/structures/BankedArray.cc b/src/mem/ruby/structures/BankedArray.cc --- a/src/mem/ruby/structures/BankedArray.cc +++ b/src/mem/ruby/structures/BankedArray.cc @@ -34,7 +34,8 @@ #include "mem/ruby/system/System.hh" BankedArray::BankedArray(unsigned int banks, Cycles accessLatency, - unsigned int startIndexBit) + unsigned int startIndexBit, RubySystem *rs) + : ruby_system(rs) { this->banks = banks; this->accessLatency = accessLatency; @@ -70,7 +71,7 @@ busyBanks[bank].idx = idx; busyBanks[bank].startAccess = curTick(); busyBanks[bank].endAccess = curTick() + - (accessLatency-1) * g_system_ptr->clockPeriod(); + (accessLatency-1) * ruby_system->clockPeriod(); return true; } diff --git a/src/mem/ruby/structures/Cache.py b/src/mem/ruby/structures/Cache.py --- a/src/mem/ruby/structures/Cache.py +++ b/src/mem/ruby/structures/Cache.py @@ -28,6 +28,7 @@ # Brad Beckmann from m5.params import * +from m5.proxy import * from m5.SimObject import SimObject class RubyCache(SimObject): @@ -46,3 +47,4 @@ dataAccessLatency = Param.Cycles(1, "cycles for a data array access") tagAccessLatency = Param.Cycles(1, "cycles for a tag array access") resourceStalls = Param.Bool(False, "stall if there is a resource failure") + ruby_system = Param.RubySystem(Parent.any, "") diff --git a/src/mem/ruby/structures/CacheMemory.cc b/src/mem/ruby/structures/CacheMemory.cc --- a/src/mem/ruby/structures/CacheMemory.cc +++ b/src/mem/ruby/structures/CacheMemory.cc @@ -53,8 +53,10 @@ CacheMemory::CacheMemory(const Params *p) : SimObject(p), - dataArray(p->dataArrayBanks, p->dataAccessLatency, p->start_index_bit), - tagArray(p->tagArrayBanks, p->tagAccessLatency, p->start_index_bit) + dataArray(p->dataArrayBanks, p->dataAccessLatency, + p->start_index_bit, p->ruby_system), + tagArray(p->tagArrayBanks, p->tagAccessLatency, + p->start_index_bit, p->ruby_system) { m_cache_size = p->size; m_latency = p->latency; diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc --- a/src/mem/ruby/structures/RubyMemoryControl.cc +++ b/src/mem/ruby/structures/RubyMemoryControl.cc @@ -310,11 +310,12 @@ physical_address_t addr = memRef->m_addr; int bank = getBank(addr); - DPRINTF(RubyMemory, - "New memory request%7d: %#08x %c arrived at %10d bank = %3x sched %c\n", - m_msg_counter, addr, memRef->m_is_mem_read ? 'R':'W', - memRef->m_time * g_system_ptr->clockPeriod(), - bank, m_event.scheduled() ? 'Y':'N'); + // TODO: access to (RubySystem*)ruby_system + //DPRINTF(RubyMemory, + //"New memory request%7d: %#08x %c arrived at %10d bank = %3x sched %c\n", + //m_msg_counter, addr, memRef->m_is_mem_read ? 'R':'W', + //memRef->m_time * ruby_system->clockPeriod(), + //bank, m_event.scheduled() ? 'Y':'N'); m_profiler_ptr->profileMemReq(bank); m_input_queue.push_back(memRef); diff --git a/src/mem/ruby/structures/SConscript b/src/mem/ruby/structures/SConscript --- a/src/mem/ruby/structures/SConscript +++ b/src/mem/ruby/structures/SConscript @@ -37,11 +37,11 @@ SimObject('DirectoryMemory.py') SimObject('RubyMemoryControl.py') SimObject('RubyPrefetcher.py') -SimObject('WireBuffer.py') +#SimObject('WireBuffer.py') Source('DirectoryMemory.cc') Source('CacheMemory.cc') -Source('WireBuffer.cc') +#Source('WireBuffer.cc') Source('RubyMemoryControl.cc') Source('MemoryNode.cc') Source('PersistentTable.cc') diff --git a/src/mem/ruby/structures/WireBuffer.cc b/src/mem/ruby/structures/WireBuffer.cc --- a/src/mem/ruby/structures/WireBuffer.cc +++ b/src/mem/ruby/structures/WireBuffer.cc @@ -34,7 +34,6 @@ #include "base/cprintf.hh" #include "base/stl_helpers.hh" -#include "mem/ruby/common/Global.hh" #include "mem/ruby/structures/WireBuffer.hh" #include "mem/ruby/system/System.hh" diff --git a/src/mem/ruby/system/DMASequencer.hh b/src/mem/ruby/system/DMASequencer.hh --- a/src/mem/ruby/system/DMASequencer.hh +++ b/src/mem/ruby/system/DMASequencer.hh @@ -32,12 +32,12 @@ #include #include +#include "mem/mem_object.hh" #include "mem/protocol/DMASequencerRequestType.hh" #include "mem/protocol/RequestStatus.hh" #include "mem/ruby/common/DataBlock.hh" #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/system/System.hh" -#include "mem/mem_object.hh" #include "mem/simple_mem.hh" #include "mem/tport.hh" #include "params/DMASequencer.hh" @@ -61,6 +61,7 @@ typedef DMASequencerParams Params; DMASequencer(const Params *); void init(); + RubySystem *ruby_system; public: class MemSlavePort : public QueuedSlavePort diff --git a/src/mem/ruby/system/DMASequencer.cc b/src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc +++ b/src/mem/ruby/system/DMASequencer.cc @@ -38,8 +38,9 @@ #include "sim/system.hh" DMASequencer::DMASequencer(const Params *p) - : MemObject(p), m_version(p->version), m_controller(NULL), - m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), + : MemObject(p), ruby_system(p->ruby_system), m_version(p->version), + m_controller(NULL), m_mandatory_q_ptr(NULL), + m_usingRubyTester(p->using_ruby_tester), slave_port(csprintf("%s.slave", name()), this, 0, p->ruby_system, p->ruby_system->getAccessBackingStore()), drainManager(NULL), system(p->system), retry(false) @@ -221,7 +222,9 @@ if (needsResponse) { DPRINTF(RubyDma, "Sending packet back over port\n"); // send next cycle - schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); + DMASequencer *seq = static_cast(&owner); + RubySystem *rs = seq->ruby_system; + schedTimingResp(pkt, curTick() + rs->clockPeriod()); } else { delete pkt; } diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -75,14 +75,13 @@ { private: RespPacketQueue queue; - RubySystem* ruby_system; bool access_backing_store; bool no_retry_on_stall; public: MemSlavePort(const std::string &_name, RubyPort *_port, - RubySystem*_system, bool _access_backing_store, - PortID id, bool _no_retry_on_stall); + bool _access_backing_store, PortID id, + bool _no_retry_on_stall); void hitCallback(PacketPtr pkt); void evictionCallback(const Address& address); @@ -184,6 +183,7 @@ */ bool recvTimingResp(PacketPtr pkt, PortID master_port_id); + RubySystem *ruby_system; uint32_t m_version; AbstractController* m_controller; MessageBuffer* m_mandatory_q_ptr; diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -51,14 +51,14 @@ #include "sim/system.hh" RubyPort::RubyPort(const Params *p) - : MemObject(p), m_version(p->version), m_controller(NULL), - m_mandatory_q_ptr(NULL), m_usingRubyTester(p->using_ruby_tester), - system(p->system), + : MemObject(p), ruby_system(p->ruby_system), m_version(p->version), + m_controller(NULL), m_mandatory_q_ptr(NULL), + m_usingRubyTester(p->using_ruby_tester), system(p->system), pioMasterPort(csprintf("%s.pio-master-port", name()), this), pioSlavePort(csprintf("%s.pio-slave-port", name()), this), memMasterPort(csprintf("%s.mem-master-port", name()), this), memSlavePort(csprintf("%s-mem-slave-port", name()), this, - p->ruby_system, p->ruby_system->getAccessBackingStore(), -1, + p->ruby_system->getAccessBackingStore(), -1, p->no_retry_on_stall), gotAddrRanges(p->port_master_connection_count), drainManager(NULL) { @@ -67,8 +67,8 @@ // create the slave ports based on the number of connected ports for (size_t i = 0; i < p->port_slave_connection_count; ++i) { slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(), - i), this, p->ruby_system, - p->ruby_system->getAccessBackingStore(), i, p->no_retry_on_stall)); + i), this, p->ruby_system->getAccessBackingStore(), i, + p->no_retry_on_stall)); } // create the master ports based on the number of connected ports @@ -159,11 +159,10 @@ } RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port, - RubySystem *_system, bool _access_backing_store, PortID id, bool _no_retry_on_stall) : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this), - ruby_system(_system), access_backing_store(_access_backing_store), + access_backing_store(_access_backing_store), no_retry_on_stall(_no_retry_on_stall) { DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name); @@ -172,12 +171,12 @@ bool RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt) { - RubyPort *ruby_port = static_cast(&owner); + RubyPort *rp = static_cast(&owner); DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr()); // send next cycle - ruby_port->pioSlavePort.schedTimingResp( - pkt, curTick() + g_system_ptr->clockPeriod()); + rp->pioSlavePort.schedTimingResp( + pkt, curTick() + rp->ruby_system->clockPeriod()); return true; } @@ -199,7 +198,8 @@ pkt->getAddr(), port->name()); // attempt to send the response in the next cycle - port->schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); + RubyPort *rp = static_cast(&owner); + port->schedTimingResp(pkt, curTick() + rp->ruby_system->clockPeriod()); return true; } @@ -247,8 +247,9 @@ pkt->pushSenderState(new SenderState(this)); // send next cycle + RubySystem *rs = ruby_port->ruby_system; ruby_port->memMasterPort.schedTimingReq(pkt, - curTick() + g_system_ptr->clockPeriod()); + curTick() + rs->clockPeriod()); return true; } @@ -302,11 +303,13 @@ { DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr()); + RubyPort *rp M5_VAR_USED = static_cast(&owner); + RubySystem *rs = rp->ruby_system; + // Check for pio requests and directly send them to the dedicated // pio port. if (!isPhysMemAddress(pkt->getAddr())) { - RubyPort *ruby_port M5_VAR_USED = static_cast(&owner); - assert(ruby_port->memMasterPort.isConnected()); + assert(rp->memMasterPort.isConnected()); DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr()); panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n"); } @@ -320,16 +323,16 @@ // The following command performs the real functional access. // This line should be removed once Ruby supplies the official version // of data. - ruby_system->getPhysMem()->functionalAccess(pkt); + rs->getPhysMem()->functionalAccess(pkt); } else { bool accessSucceeded = false; bool needsResponse = pkt->needsResponse(); // Do the functional access on ruby memory if (pkt->isRead()) { - accessSucceeded = ruby_system->functionalRead(pkt); + accessSucceeded = rs->functionalRead(pkt); } else if (pkt->isWrite()) { - accessSucceeded = ruby_system->functionalWrite(pkt); + accessSucceeded = rs->functionalWrite(pkt); } else { panic("Unsupported functional command %s\n", pkt->cmdString()); } @@ -536,8 +539,10 @@ DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); + RubyPort *ruby_port = static_cast(&owner); + RubySystem *rs = ruby_port->ruby_system; if (accessPhysMem) { - ruby_system->getPhysMem()->access(pkt); + rs->getPhysMem()->access(pkt); } else if (needsResponse) { pkt->makeResponse(); } @@ -546,7 +551,7 @@ if (needsResponse) { DPRINTF(RubyPort, "Sending packet back over port\n"); // send next cycle - schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod()); + schedTimingResp(pkt, curTick() + rs->clockPeriod()); } else { delete pkt; } diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc +++ b/src/mem/ruby/system/Sequencer.cc @@ -160,7 +160,7 @@ #if 0 int total_demand = 0; out << "Sequencer Stats Version " << m_version << endl; - out << "Current time = " << g_system_ptr->getTime() << endl; + out << "Current time = " << ruby_system->getTime() << endl; out << "---------------" << endl; out << "outstanding requests" << endl; @@ -525,7 +525,8 @@ request_address, total_latency); // update the data unless it is a non-data-carrying flush - if (RubySystem::getWarmupEnabled()) { + RubySystem *rs = ruby_system; + if (rs->m_warmup_enabled) { data.setData(pkt->getConstPtr(), request_address.getOffset(), pkt->getSize()); } else if (!pkt->isFlush()) { @@ -557,14 +558,14 @@ delete srequest; - if (RubySystem::getWarmupEnabled()) { + if (rs->m_warmup_enabled) { assert(pkt->req); delete pkt->req; delete pkt; - g_system_ptr->m_cache_recorder->enqueueNextFetchRequest(); - } else if (RubySystem::getCooldownEnabled()) { + rs->m_cache_recorder->enqueueNextFetchRequest(); + } else if (rs->m_cooldown_enabled) { delete pkt; - g_system_ptr->m_cache_recorder->enqueueNextFlushRequest(); + rs->m_cache_recorder->enqueueNextFlushRequest(); } else { ruby_hit_callback(pkt); } @@ -737,7 +738,7 @@ Sequencer::checkCoherence(const Address& addr) { #ifdef CHECK_COHERENCE - g_system_ptr->checkGlobalCoherenceInvariant(addr); + ruby_system->checkGlobalCoherenceInvariant(addr); #endif } diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py --- a/src/mem/ruby/system/Sequencer.py +++ b/src/mem/ruby/system/Sequencer.py @@ -46,7 +46,7 @@ using_ruby_tester = Param.Bool(False, "") no_retry_on_stall = Param.Bool(False, "") - ruby_system = Param.RubySystem("") + ruby_system = Param.RubySystem(Parent.any, "") system = Param.System(Parent.any, "system object") support_data_reqs = Param.Bool(True, "data cache requests supported") support_inst_reqs = Param.Bool(True, "inst cache requests supported") diff --git a/src/mem/ruby/system/System.hh b/src/mem/ruby/system/System.hh --- a/src/mem/ruby/system/System.hh +++ b/src/mem/ruby/system/System.hh @@ -128,9 +128,6 @@ static uint32_t m_block_size_bytes; static uint32_t m_block_size_bits; static uint32_t m_memory_size_bits; - static bool m_warmup_enabled; - static unsigned m_systems_to_warmup; - static bool m_cooldown_enabled; SimpleMemory *m_phys_mem; const bool m_access_backing_store; @@ -141,6 +138,9 @@ public: Profiler* m_profiler; CacheRecorder* m_cache_recorder; + static bool m_warmup_enabled; + static bool m_cooldown_enabled; + static unsigned m_systems_to_warmup; }; class RubyStatsCallback : public Callback diff --git a/src/mem/ruby/system/System.cc b/src/mem/ruby/system/System.cc --- a/src/mem/ruby/system/System.cc +++ b/src/mem/ruby/system/System.cc @@ -58,9 +58,6 @@ RubySystem::RubySystem(const Params *p) : ClockedObject(p), m_access_backing_store(p->access_backing_store) { - if (g_system_ptr != NULL) - fatal("Only one RubySystem object currently allowed.\n"); - m_random_seed = p->random_seed; srandom(m_random_seed); m_randomization = p->randomization; @@ -70,8 +67,8 @@ m_block_size_bits = floorLog2(m_block_size_bytes); m_memory_size_bits = p->memory_size_bits; - // Setup the global variables used in Ruby - g_system_ptr = this; + m_warmup_enabled = false; + m_cooldown_enabled = false; // Resize to the size of different machine types g_abs_controls.resize(MachineType_NUM); @@ -79,7 +76,7 @@ // Collate the statistics before they are printed. Stats::registerDumpCallback(new RubyStatsCallback(this)); // Create the profiler - m_profiler = new Profiler(p); + m_profiler = new Profiler(p, this); m_phys_mem = p->phys_mem; } diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py +++ b/src/mem/slicc/symbols/StateMachine.py @@ -38,7 +38,7 @@ "std::string": "String", "bool": "Bool", "CacheMemory": "RubyCache", - "WireBuffer": "RubyWireBuffer", + #"WireBuffer": "RubyWireBuffer", "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", "MemoryControl": "MemoryControl", @@ -513,7 +513,7 @@ for var in self.objects: if var.ident.find("mandatoryQueue") >= 0: code(''' -m_${{var.ident}}_ptr = new ${{var.type.c_ident}}(); +m_${{var.ident}}_ptr = new ${{var.type.c_ident}}(p->ruby_system); m_${{var.ident}}_ptr->setReceiver(this); ''') @@ -636,7 +636,10 @@ expr = "%s = new %s%s" % (vid, vtype.c_ident, th) args = "" if "non_obj" not in vtype and not vtype.isEnumeration: - args = var.get("constructor", "") + rs = "" + if vtype.c_ident == "MessageBuffer": + rs = "params()->ruby_system" + args = var.get("constructor", rs) code('$expr($args);') code('assert($vid != NULL);') @@ -735,7 +738,7 @@ event < ${ident}_Event_NUM; ++event) { Stats::Vector *t = new Stats::Vector(); t->init(m_num_controllers); - t->name(g_system_ptr->name() + ".${c_ident}." + + t->name(params()->ruby_system->name() + ".${c_ident}." + ${ident}_Event_to_string(event)); t->flags(Stats::pdf | Stats::total | Stats::oneline | Stats::nozero); @@ -753,7 +756,7 @@ Stats::Vector *t = new Stats::Vector(); t->init(m_num_controllers); - t->name(g_system_ptr->name() + ".${c_ident}." + + t->name(params()->ruby_system->name() + ".${c_ident}." + ${ident}_State_to_string(state) + "." + ${ident}_Event_to_string(event)); diff --git a/src/mem/slicc/symbols/Type.py b/src/mem/slicc/symbols/Type.py --- a/src/mem/slicc/symbols/Type.py +++ b/src/mem/slicc/symbols/Type.py @@ -422,8 +422,9 @@ for dm in self.data_members.values(): code('out << "${{dm.ident}} = " << m_${{dm.ident}} << " ";''') - if self.isMessage: - code('out << "Time = " << g_system_ptr->clockPeriod() * getTime() << " ";') + # Does not look easy to pass in the system pointer to a message. + #if self.isMessage: + #code('out << "Time = " << g_system_ptr->clockPeriod() * getTime() << " ";') code.dedent() # Trailer diff --git a/src/python/swig/pyobject.cc b/src/python/swig/pyobject.cc --- a/src/python/swig/pyobject.cc +++ b/src/python/swig/pyobject.cc @@ -44,6 +44,7 @@ #include "python/swig/pyobject.hh" #include "sim/full_system.hh" #include "sim/sim_object.hh" +#include "mem/ruby/system/System.hh" using namespace std; @@ -107,7 +108,9 @@ ac2 = dynamic_cast(o2); if ((ac1 || ac2) && name1 != "memory" && name2 != "memory") { - MessageBuffer *b = new MessageBuffer(); + RubySystem *rs = ac1 ? ac1->params()->ruby_system : + ac2->params()->ruby_system; + MessageBuffer *b = new MessageBuffer(rs); // set the message buffer associated with the provided names if (ac1) {