# HG changeset patch
# User Erfan Azarkhish <erfan.azarkhish@unibo.it>
# Date 1436365276 -7200
#      Wed Jul 08 16:21:16 2015 +0200
# Node ID 465fb8c652387b041ef7480823e6abf311aede07
# Parent d02e9c239892833cc448467f3ab514b2f65f90e3
dram controller

diff -r d02e9c239892 src/mem/DRAMCtrl.py
--- a/src/mem/DRAMCtrl.py	Fri Jul 17 11:31:22 2015 -0500
+++ b/src/mem/DRAMCtrl.py	Sat Jul 18 09:16:02 2015 +0200
@@ -382,8 +382,8 @@
 # developed at the University of Kaiserslautern. This high level tool
 # uses RC (resistance-capacitance) and CV (capacitance-voltage) models to
 # estimate the DRAM bank latency and power numbers.
-# [2] A Logic-base Interconnect for Supporting Near Memory Computation in the
-# Hybrid Memory Cube (E. Azarkhish et. al)
+# [2] High performance AXI-4.0 based interconnect for extensible smart memory
+# cubes (E. Azarkhish et. al)
 # Assumed for the HMC model is a 30 nm technology node.
 # The modelled HMC consists of 4 Gbit layers which sum up to 2GB of memory (4
 # layers).
@@ -457,12 +457,23 @@
     tREFI = '3.9us'
 
     # Set default controller parameters
-    page_policy = 'close'
-    write_buffer_size = 8
-    read_buffer_size = 8
+    page_policy = 'close_adaptive'
+
+    # RoCoRaBaCh resembles the default address mapping in HMC
     addr_mapping = 'RoCoRaBaCh'
     min_writes_per_switch = 8
 
+    # These parameters do not directly correlate with buffer_size in real
+    #  hardware. Nevertheless, their value has been tuned to achieve a bandwidth
+    #  similar to the cycle-accurate model in [2]
+    write_buffer_size = 32
+    read_buffer_size = 32
+
+    # The static latency of the vault controllers is estimated to be smaller
+    #  than a full DRAM channel controller
+    static_backend_latency='4ns'
+    static_frontend_latency='4ns'
+
 # A single DDR3-2133 x64 channel refining a selected subset of the
 # options for the DDR-1600 configuration, based on the same DDR3-1600
 # 4 Gbit datasheet (Micron MT41J512M8). Most parameters are kept