diff -r ebb3d0737aa7 -r e4447e47a52b configs/example/hmctest.py --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/configs/example/hmctest.py Mon Jun 22 11:15:38 2015 +0200 @@ -0,0 +1,131 @@ +import optparse +import sys +import subprocess + +import m5 +from m5.objects import * +from m5.util import addToPath + +addToPath('../common') +import MemConfig +import HMC + +parser = optparse.OptionParser() + +# Use a single-channel DDR3-1600 x64 by default +parser.add_option("--mem-type", type="choice", default="HMC_2500_x32", + choices=MemConfig.mem_names(), + help = "type of memory to use") + +parser.add_option("--ranks", "-r", type="int", default=1, + help = "Number of ranks to iterate across") + +parser.add_option("--rd_perc", type="int", default=100, + help = "Percentage of read commands") + +parser.add_option("--mode", type="choice", default="DRAM", + choices=["DRAM", "DRAM_ROTATE", "RANDOM"], + help = "DRAM: Random traffic; \ + DRAM_ROTATE: Traffic rotating across banks and ranks") + +parser.add_option("--addr_map", type="int", default=1, + help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") + +(options, args) = parser.parse_args() + +if args: + print "Error: script doesn't take any positional arguments" + sys.exit(1) + +system = System() +system.clk_domain = SrcClockDomain(clock = '100GHz', + voltage_domain = + VoltageDomain(voltage = '1V')) + +system.membus = NoncoherentXBar( width=8 ) +system.membus.badaddr_responder = BadAddr() +system.membus.default = Self.badaddr_responder.pio +system.membus.width = 8 +system.membus.frontend_latency = 3 +system.membus.forward_latency = 4 +system.membus.response_latency = 2 + +system.membus.clk_domain = SrcClockDomain(clock='100GHz', voltage_domain = VoltageDomain(voltage = '1V')) + +# determine the burst length in bytes +burst_size = 256 +page_size = 512 +options.mem_channels = 16 +options.external_memory_system = 0 +options.mem_ranks=1 +stride_size = burst_size +system.cache_line_size = burst_size + +# Enable performance monitoring +options.enable_global_monitor = True +options.enable_link_monitor = True + +mem_range = AddrRange('128MB') +system.mem_ranges = [mem_range] + +# force a single channel to match the assumptions in the DRAM traffic +# generator + +HMC.config_hmc(options, system) +MemConfig.config_mem(options, system, system.hmc, system.hmc.xbar) + +# stay in each state for 0.25 ms, long enough to warm things up, and +# short enough to avoid hitting a refresh +period = 10000 + +# this is where we go off piste, and print the traffic generator +# configuration that we will later use, crazy but it works +cfg_file_name = "./m5out/traffic.cfg" +cfg_file = open(cfg_file_name, 'w') + +# stay in each state as long as the dump/reset period, use the entire +# range, issue transactions of the right DRAM burst size, and match +# the DRAM maximum bandwidth to ensure that it is saturated + +# match the maximum bandwidth of the memory, the parameter is in ns +# and we need it in ticks +itt = 1000; + +# assume we start at 0 +max_addr = mem_range.end + +cfg_file.write("STATE %d %d %s %d 0 %d %d " + "%d %d %d\n" % + (0, period, options.mode, options.rd_perc, + max_addr, burst_size, itt, itt, 0 )) + +# Very high pressure traffic +cfg_file.write("STATE %d %d %s\n" % + (1, 1000, "IDLE")) + +cfg_file.write("INIT 0\n") + +cfg_file.write("TRANSITION %d %d 1\n" % (0, 1)) +cfg_file.write("TRANSITION %d %d 1\n" % (1, 0)) + +cfg_file.close() + +np = 1 +# create a traffic generator, and point it to the file we just created +system.tgen = [ TrafficGen(config_file = cfg_file_name) for i in xrange(np)] +for i in xrange(np): + system.tgen[i].port = system.membus.slave + +# connect the system port even if it is not used in this example +system.system_port = system.membus.slave + +# run Forrest, run! +root = Root(full_system = False, system = system) +root.system.mem_mode = 'timing' + +m5.instantiate() +m5.simulate(10000000000) + +m5.stats.dump() + +print "Done!" diff -r ebb3d0737aa7 -r e4447e47a52b configs/common/MemConfig.py --- a/configs/common/MemConfig.py Tue Jun 09 09:21:18 2015 -0400 +++ b/configs/common/MemConfig.py Mon Jun 22 11:15:38 2015 +0200 @@ -140,7 +140,7 @@ intlvMatch = i) return ctrl -def config_mem(options, system): +def config_mem(options, system, subsystem=None, xbar = None): """ Create the memory controllers based on the options and attach them. @@ -149,14 +149,22 @@ the specific class. The individual controllers have their parameters set such that the address range is interleaved between them. + + subsystem: asks this method to add the components to the given subsystem + (e.g. HMC) """ + if xbar is None: + xbar = system.membus + if subsystem is None: + subsystem = system + if options.external_memory_system: - system.external_memory = m5.objects.ExternalSlave( + subsystem.external_memory = m5.objects.ExternalSlave( port_type=options.external_memory_system, - port_data="init_mem0", port=system.membus.master, + port_data="init_mem0", port=xbar.master, addr_ranges=system.mem_ranges) - system.kernel_addr_check = False + subsystem.kernel_addr_check = False return nbr_mem_ctrls = options.mem_channels @@ -190,8 +198,8 @@ mem_ctrls.append(mem_ctrl) - system.mem_ctrls = mem_ctrls + subsystem.mem_ctrls = mem_ctrls # Connect the controllers to the membus - for i in xrange(len(system.mem_ctrls)): - system.mem_ctrls[i].port = system.membus.master + for i in xrange(len(subsystem.mem_ctrls)): + subsystem.mem_ctrls[i].port = xbar.master diff -r ebb3d0737aa7 -r e4447e47a52b configs/example/fs.py --- a/configs/example/fs.py Tue Jun 09 09:21:18 2015 -0400 +++ b/configs/example/fs.py Mon Jun 22 11:15:38 2015 +0200 @@ -60,6 +60,7 @@ import Simulation import CacheConfig import MemConfig +import HMC from Caches import * import Options @@ -215,7 +216,12 @@ test_sys.cpu[i].createThreads() CacheConfig.config_cache(options, test_sys) - MemConfig.config_mem(options, test_sys) + + if ( options.mem_type == "HMC_2500_x32"): + HMC.config_hmc(options, test_sys) + MemConfig.config_mem(options, test_sys, test_sys.hmc, test_sys.hmc.xbar) + else: + MemConfig.config_mem(options, test_sys) return test_sys