diff -r 7cc3399e1f53 -r 514ddcac7c76 src/cpu/testers/directedtest/RubyDirectedTester.hh --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh Sun Jul 19 18:39:40 2015 -0500 @@ -109,9 +109,9 @@ RubyDirectedTester(const RubyDirectedTester& obj); RubyDirectedTester& operator=(const RubyDirectedTester& obj); - uint64 m_requests_completed; + uint64_t m_requests_completed; std::vector ports; - uint64 m_requests_to_complete; + uint64_t m_requests_to_complete; DirectedGenerator* generator; }; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/cpu/testers/rubytest/RubyTester.hh --- a/src/cpu/testers/rubytest/RubyTester.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/cpu/testers/rubytest/RubyTester.hh Sun Jul 19 18:39:40 2015 -0500 @@ -143,10 +143,10 @@ std::vector m_last_progress_vector; int m_num_cpus; - uint64 m_checks_completed; + uint64_t m_checks_completed; std::vector writePorts; std::vector readPorts; - uint64 m_checks_to_complete; + uint64_t m_checks_to_complete; int m_deadlock_threshold; int m_num_writers; int m_num_readers; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/common/Histogram.hh --- a/src/mem/ruby/common/Histogram.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/common/Histogram.hh Sun Jul 19 18:39:40 2015 -0500 @@ -40,7 +40,7 @@ Histogram(int binsize = 1, uint32_t bins = 50); ~Histogram(); - void add(int64 value); + void add(int64_t value); void add(Histogram& hist); void doubleBinSize(); @@ -51,10 +51,10 @@ uint64_t size() const { return m_count; } uint32_t getBins() const { return m_data.size(); } int getBinSize() const { return m_binsize; } - int64 getTotal() const { return m_sumSamples; } + int64_t getTotal() const { return m_sumSamples; } uint64_t getSquaredTotal() const { return m_sumSquaredSamples; } uint64_t getData(int index) const { return m_data[index]; } - int64 getMax() const { return m_max; } + int64_t getMax() const { return m_max; } void printWithMultiplier(std::ostream& out, double multiplier) const; void printPercent(std::ostream& out) const; @@ -62,12 +62,12 @@ private: std::vector m_data; - int64 m_max; // the maximum value seen so far + int64_t m_max; // the maximum value seen so far uint64_t m_count; // the number of elements added int m_binsize; // the size of each bucket uint32_t m_largest_bin; // the largest bin used - int64 m_sumSamples; // the sum of all samples + int64_t m_sumSamples; // the sum of all samples uint64_t m_sumSquaredSamples; // the sum of the square of all samples double getStandardDeviation() const; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/common/Histogram.cc --- a/src/mem/ruby/common/Histogram.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/common/Histogram.cc Sun Jul 19 18:39:40 2015 -0500 @@ -84,7 +84,7 @@ } void -Histogram::add(int64 value) +Histogram::add(int64_t value) { assert(value >= 0); m_max = max(m_max, value); diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/common/TypeDefines.hh --- a/src/mem/ruby/common/TypeDefines.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/common/TypeDefines.hh Sun Jul 19 18:39:40 2015 -0500 @@ -30,9 +30,6 @@ #ifndef TYPEDEFINES_H #define TYPEDEFINES_H -typedef unsigned long long uint64; -typedef long long int64; - typedef unsigned int LinkID; typedef unsigned int NodeID; typedef unsigned int SwitchID; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/filters/H3BloomFilter.hh --- a/src/mem/ruby/filters/H3BloomFilter.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/filters/H3BloomFilter.hh Sun Jul 19 18:39:40 2015 -0500 @@ -68,7 +68,7 @@ private: int get_index(Addr addr, int hashNumber); - int hash_H3(uint64 value, int index); + int hash_H3(uint64_t value, int index); std::vector m_filter; int m_filter_size; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/filters/H3BloomFilter.cc --- a/src/mem/ruby/filters/H3BloomFilter.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/filters/H3BloomFilter.cc Sun Jul 19 18:39:40 2015 -0500 @@ -507,8 +507,8 @@ int H3BloomFilter::get_index(Addr addr, int i) { - uint64 x = makeLineAddress(addr); - // uint64 y = (x*mults_list[i] + adds_list[i]) % primes_list[i]; + uint64_t x = makeLineAddress(addr); + // uint64_t y = (x*mults_list[i] + adds_list[i]) % primes_list[i]; int y = hash_H3(x,i); if (isParallel) { @@ -519,10 +519,10 @@ } int -H3BloomFilter::hash_H3(uint64 value, int index) +H3BloomFilter::hash_H3(uint64_t value, int index) { - uint64 mask = 1; - uint64 val = value; + uint64_t mask = 1; + uint64_t val = value; int result = 0; for (int i = 0; i < 64; i++) { diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/filters/MultiBitSelBloomFilter.hh --- a/src/mem/ruby/filters/MultiBitSelBloomFilter.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.hh Sun Jul 19 18:39:40 2015 -0500 @@ -68,7 +68,7 @@ private: int get_index(Addr addr, int hashNumber); - int hash_bitsel(uint64 value, int index, int jump, int maxBits, + int hash_bitsel(uint64_t value, int index, int jump, int maxBits, int numBits); std::vector m_filter; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/filters/MultiBitSelBloomFilter.cc --- a/src/mem/ruby/filters/MultiBitSelBloomFilter.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/filters/MultiBitSelBloomFilter.cc Sun Jul 19 18:39:40 2015 -0500 @@ -171,7 +171,7 @@ // m_skip_bits is used to perform BitSelect after skipping some // bits. Used to simulate BitSel hashing on larger than cache-line // granularities - uint64 x = (makeLineAddress(addr) >> m_skip_bits); + uint64_t x = (makeLineAddress(addr) >> m_skip_bits); int y = hash_bitsel(x, i, m_num_hashes, 30, m_filter_size_bits); //36-bit addresses, 6-bit cache lines @@ -183,10 +183,10 @@ } int -MultiBitSelBloomFilter::hash_bitsel(uint64 value, int index, int jump, +MultiBitSelBloomFilter::hash_bitsel(uint64_t value, int index, int jump, int maxBits, int numBits) { - uint64 mask = 1; + uint64_t mask = 1; int result = 0; int bit, i; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/network/MessageBuffer.hh --- a/src/mem/ruby/network/MessageBuffer.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/network/MessageBuffer.hh Sun Jul 19 18:39:40 2015 -0500 @@ -191,7 +191,7 @@ int m_not_avail_count; // count the # of times I didn't have N // slots available - uint64 m_msg_counter; + uint64_t m_msg_counter; int m_priority_rank; bool m_strict_fifo; bool m_ordering_set; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/profiler/AccessTraceForAddress.hh --- a/src/mem/ruby/profiler/AccessTraceForAddress.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/profiler/AccessTraceForAddress.hh Sun Jul 19 18:39:40 2015 -0500 @@ -67,12 +67,12 @@ private: Addr m_addr; - uint64 m_loads; - uint64 m_stores; - uint64 m_atomics; - uint64 m_total; - uint64 m_user; - uint64 m_sharing; + uint64_t m_loads; + uint64_t m_stores; + uint64_t m_atomics; + uint64_t m_total; + uint64_t m_user; + uint64_t m_sharing; Set m_touched_by; Histogram* m_histogram_ptr; }; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/profiler/AddressProfiler.hh --- a/src/mem/ruby/profiler/AddressProfiler.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/profiler/AddressProfiler.hh Sun Jul 19 18:39:40 2015 -0500 @@ -75,7 +75,7 @@ AddressProfiler(const AddressProfiler& obj); AddressProfiler& operator=(const AddressProfiler& obj); - int64 m_sharing_miss_counter; + int64_t m_sharing_miss_counter; AddressMap m_dataAccessTrace; AddressMap m_macroBlockAccessTrace; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/profiler/AddressProfiler.cc --- a/src/mem/ruby/profiler/AddressProfiler.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/profiler/AddressProfiler.cc Sun Jul 19 18:39:40 2015 -0500 @@ -67,7 +67,7 @@ { const int records_printed = 100; - uint64 misses = 0; + uint64_t misses = 0; std::vector sorted; AddressMap::const_iterator i = record_map.begin(); @@ -95,8 +95,8 @@ Histogram all_records_log(-1); // Allows us to track how many lines where touched by n processors - std::vector m_touched_vec; - std::vector m_touched_weighted_vec; + std::vector m_touched_vec; + std::vector m_touched_weighted_vec; m_touched_vec.resize(num_of_sequencers+1); m_touched_weighted_vec.resize(num_of_sequencers+1); for (int j = 0; j < m_touched_vec.size(); j++) { diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/profiler/StoreTrace.hh --- a/src/mem/ruby/profiler/StoreTrace.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/profiler/StoreTrace.hh Sun Jul 19 18:39:40 2015 -0500 @@ -53,7 +53,7 @@ private: static bool s_init; - static int64 s_total_samples; // Total number of store lifetimes + static int64_t s_total_samples; // Total number of store lifetimes // of all lines static Histogram* s_store_count_ptr; static Histogram* s_store_first_to_stolen_ptr; @@ -66,7 +66,7 @@ Tick m_last_store; int m_stores_this_interval; - int64 m_total_samples; // Total number of store lifetimes of this line + int64_t m_total_samples; // Total number of store lifetimes of this line Histogram m_store_count; Histogram m_store_first_to_stolen; Histogram m_store_last_to_stolen; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/profiler/StoreTrace.cc --- a/src/mem/ruby/profiler/StoreTrace.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/profiler/StoreTrace.cc Sun Jul 19 18:39:40 2015 -0500 @@ -33,7 +33,7 @@ bool StoreTrace::s_init = false; // Total number of store lifetimes of // all lines -int64 StoreTrace::s_total_samples = 0; // Total number of store +int64_t StoreTrace::s_total_samples = 0; // Total number of store // lifetimes of all lines Histogram* StoreTrace::s_store_count_ptr = NULL; Histogram* StoreTrace::s_store_first_to_stolen_ptr = NULL; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/AbstractReplacementPolicy.hh --- a/src/mem/ruby/structures/AbstractReplacementPolicy.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/AbstractReplacementPolicy.hh Sun Jul 19 18:39:40 2015 -0500 @@ -34,17 +34,17 @@ class AbstractReplacementPolicy { public: - AbstractReplacementPolicy(int64 num_sets, int64 assoc); + AbstractReplacementPolicy(int64_t num_sets, int64_t assoc); virtual ~AbstractReplacementPolicy(); /* touch a block. a.k.a. update timestamp */ - virtual void touch(int64 set, int64 way, Tick time) = 0; + virtual void touch(int64_t set, int64_t way, Tick time) = 0; /* returns the way to replace */ - virtual int64 getVictim(int64 set) const = 0; + virtual int64_t getVictim(int64_t set) const = 0; /* get the time of the last access */ - Tick getLastAccess(int64 set, int64 way); + Tick getLastAccess(int64_t set, int64_t way); protected: unsigned m_num_sets; /** total number of sets */ @@ -53,8 +53,8 @@ }; inline -AbstractReplacementPolicy::AbstractReplacementPolicy(int64 num_sets, - int64 assoc) +AbstractReplacementPolicy::AbstractReplacementPolicy(int64_t num_sets, + int64_t assoc) { m_num_sets = num_sets; m_assoc = assoc; @@ -81,7 +81,7 @@ } inline Tick -AbstractReplacementPolicy::getLastAccess(int64 set, int64 way) +AbstractReplacementPolicy::getLastAccess(int64_t set, int64_t way) { return m_last_ref_ptr[set][way]; } diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/BankedArray.hh --- a/src/mem/ruby/structures/BankedArray.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/BankedArray.hh Sun Jul 19 18:39:40 2015 -0500 @@ -51,7 +51,7 @@ { public: AccessRecord() : idx(0), startAccess(0), endAccess(0) {} - int64 idx; + int64_t idx; Tick startAccess; Tick endAccess; }; @@ -60,7 +60,7 @@ // otherwise, schedule the event and wait for it to complete std::vector busyBanks; - unsigned int mapIndexToBank(int64 idx); + unsigned int mapIndexToBank(int64_t idx); public: BankedArray(unsigned int banks, Cycles accessLatency, @@ -68,7 +68,7 @@ // Note: We try the access based on the cache index, not the address // This is so we don't get aliasing on blocks being replaced - bool tryAccess(int64 idx); + bool tryAccess(int64_t idx); }; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/BankedArray.cc --- a/src/mem/ruby/structures/BankedArray.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/BankedArray.cc Sun Jul 19 18:39:40 2015 -0500 @@ -49,7 +49,7 @@ } bool -BankedArray::tryAccess(int64 idx) +BankedArray::tryAccess(int64_t idx) { if (accessLatency == 0) return true; @@ -77,7 +77,7 @@ } unsigned int -BankedArray::mapIndexToBank(int64 idx) +BankedArray::mapIndexToBank(int64_t idx) { if (banks == 1) { return 0; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/CacheMemory.hh --- a/src/mem/ruby/structures/CacheMemory.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/CacheMemory.hh Sun Jul 19 18:39:40 2015 -0500 @@ -136,12 +136,12 @@ private: // convert a Address to its location in the cache - int64 addressToCacheSet(Addr address) const; + int64_t addressToCacheSet(Addr address) const; // Given a cache tag: returns the index of the tag in a set. // returns -1 if the tag is not found. - int findTagInSet(int64 line, Addr tag) const; - int findTagInSetIgnorePermissions(int64 cacheSet, Addr tag) const; + int findTagInSet(int64_t line, Addr tag) const; + int findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const; // Private copy constructor and assignment operator CacheMemory(const CacheMemory& obj); diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/CacheMemory.cc --- a/src/mem/ruby/structures/CacheMemory.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/CacheMemory.cc Sun Jul 19 18:39:40 2015 -0500 @@ -106,7 +106,7 @@ } // convert a Address to its location in the cache -int64 +int64_t CacheMemory::addressToCacheSet(Addr address) const { assert(address == makeLineAddress(address)); @@ -117,7 +117,7 @@ // Given a cache index: returns the index of the tag in a set. // returns -1 if the tag is not found. int -CacheMemory::findTagInSet(int64 cacheSet, Addr tag) const +CacheMemory::findTagInSet(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); // search the set for the tags @@ -132,7 +132,7 @@ // Given a cache index: returns the index of the tag in a set. // returns -1 if the tag is not found. int -CacheMemory::findTagInSetIgnorePermissions(int64 cacheSet, +CacheMemory::findTagInSetIgnorePermissions(int64_t cacheSet, Addr tag) const { assert(tag == makeLineAddress(tag)); @@ -149,7 +149,7 @@ { assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { // Do we even have a tag match? @@ -176,7 +176,7 @@ { assert(address == makeLineAddress(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { @@ -198,7 +198,7 @@ CacheMemory::isTagPresent(Addr address) const { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc == -1) { @@ -218,7 +218,7 @@ { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); for (int i = 0; i < m_cache_assoc; i++) { AbstractCacheEntry* entry = m_cache[cacheSet][i]; @@ -244,7 +244,7 @@ DPRINTF(RubyCache, "address: %s\n", address); // Find the first open slot - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); std::vector &set = m_cache[cacheSet]; for (int i = 0; i < m_cache_assoc; i++) { if (!set[i] || set[i]->m_Permission == AccessPermission_NotPresent) { @@ -270,7 +270,7 @@ assert(address == makeLineAddress(address)); assert(isTagPresent(address)); DPRINTF(RubyCache, "address: %s\n", address); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if (loc != -1) { delete m_cache[cacheSet][loc]; @@ -286,7 +286,7 @@ assert(address == makeLineAddress(address)); assert(!cacheAvail(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); return m_cache[cacheSet][m_replacementPolicy_ptr->getVictim(cacheSet)]-> m_Address; } @@ -296,7 +296,7 @@ CacheMemory::lookup(Addr address) { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; return m_cache[cacheSet][loc]; @@ -307,7 +307,7 @@ CacheMemory::lookup(Addr address) const { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc == -1) return NULL; return m_cache[cacheSet][loc]; @@ -317,7 +317,7 @@ void CacheMemory::setMRU(Addr address) { - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); if(loc != -1) @@ -327,9 +327,9 @@ void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { - uint64 warmedUpBlocks = 0; - uint64 totalBlocks M5_VAR_USED = (uint64)m_cache_num_sets - * (uint64)m_cache_assoc; + uint64_t warmedUpBlocks = 0; + uint64_t totalBlocks M5_VAR_USED = (uint64_t)m_cache_num_sets * + (uint64_t)m_cache_assoc; for (int i = 0; i < m_cache_num_sets; i++) { for (int j = 0; j < m_cache_assoc; j++) { @@ -359,8 +359,7 @@ DPRINTF(RubyCacheTrace, "%s: %lli blocks of %lli total blocks" "recorded %.2f%% \n", name().c_str(), warmedUpBlocks, - (uint64)m_cache_num_sets * (uint64)m_cache_assoc, - (float(warmedUpBlocks)/float(totalBlocks))*100.0); + totalBlocks, (float(warmedUpBlocks) / float(totalBlocks)) * 100.0); } void @@ -393,7 +392,7 @@ { DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context); assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); m_cache[cacheSet][loc]->m_locked = context; @@ -404,7 +403,7 @@ { DPRINTF(RubyCache, "Clear Lock for addr: %x\n", address); assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); m_cache[cacheSet][loc]->m_locked = -1; @@ -414,7 +413,7 @@ CacheMemory::isLocked(Addr address, int context) { assert(address == makeLineAddress(address)); - int64 cacheSet = addressToCacheSet(address); + int64_t cacheSet = addressToCacheSet(address); int loc = findTagInSet(cacheSet, address); assert(loc != -1); DPRINTF(RubyCache, "Testing Lock for addr: %llx cur %d con %d\n", diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/LRUPolicy.hh --- a/src/mem/ruby/structures/LRUPolicy.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/LRUPolicy.hh Sun Jul 19 18:39:40 2015 -0500 @@ -36,15 +36,15 @@ class LRUPolicy : public AbstractReplacementPolicy { public: - LRUPolicy(int64 num_sets, int64 assoc); + LRUPolicy(int64_t num_sets, int64_t assoc); ~LRUPolicy(); - void touch(int64 set, int64 way, Tick time); - int64 getVictim(int64 set) const; + void touch(int64_t set, int64_t way, Tick time); + int64_t getVictim(int64_t set) const; }; inline -LRUPolicy::LRUPolicy(int64 num_sets, int64 assoc) +LRUPolicy::LRUPolicy(int64_t num_sets, int64_t assoc) : AbstractReplacementPolicy(num_sets, assoc) { } @@ -55,7 +55,7 @@ } inline void -LRUPolicy::touch(int64 set, int64 index, Tick time) +LRUPolicy::touch(int64_t set, int64_t index, Tick time) { assert(index >= 0 && index < m_assoc); assert(set >= 0 && set < m_num_sets); @@ -63,12 +63,12 @@ m_last_ref_ptr[set][index] = time; } -inline int64 -LRUPolicy::getVictim(int64 set) const +inline int64_t +LRUPolicy::getVictim(int64_t set) const { // assert(m_assoc != 0); Tick time, smallest_time; - int64 smallest_index; + int64_t smallest_index; smallest_index = 0; smallest_time = m_last_ref_ptr[set][0]; @@ -84,11 +84,6 @@ } } - // DEBUG_EXPR(CACHE_COMP, MedPrio, cacheSet); - // DEBUG_EXPR(CACHE_COMP, MedPrio, smallest_index); - // DEBUG_EXPR(CACHE_COMP, MedPrio, m_cache[cacheSet][smallest_index]); - // DEBUG_EXPR(CACHE_COMP, MedPrio, *this); - return smallest_index; } diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/PseudoLRUPolicy.hh --- a/src/mem/ruby/structures/PseudoLRUPolicy.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/PseudoLRUPolicy.hh Sun Jul 19 18:39:40 2015 -0500 @@ -47,25 +47,25 @@ class PseudoLRUPolicy : public AbstractReplacementPolicy { public: - PseudoLRUPolicy(int64 num_sets, int64 assoc); + PseudoLRUPolicy(int64_t num_sets, int64_t assoc); ~PseudoLRUPolicy(); - void touch(int64 set, int64 way, Tick time); - int64 getVictim(int64 set) const; + void touch(int64_t set, int64_t way, Tick time); + int64_t getVictim(int64_t set) const; private: unsigned int m_effective_assoc; /** nearest (to ceiling) power of 2 */ unsigned int m_num_levels; /** number of levels in the tree */ - uint64* m_trees; /** bit representation of the + uint64_t *m_trees; /** bit representation of the * trees, one for each set */ }; inline -PseudoLRUPolicy::PseudoLRUPolicy(int64 num_sets, int64 assoc) +PseudoLRUPolicy::PseudoLRUPolicy(int64_t num_sets, int64_t assoc) : AbstractReplacementPolicy(num_sets, assoc) { // associativity cannot exceed capacity of tree representation - assert(num_sets > 0 && assoc > 1 && assoc <= sizeof(uint64)*4); + assert(num_sets > 0 && assoc > 1 && assoc <= sizeof(uint64_t)*4); m_trees = NULL; m_num_levels = 0; @@ -82,7 +82,7 @@ m_num_levels++; } assert(m_num_levels < sizeof(unsigned int)*4); - m_trees = new uint64[m_num_sets]; + m_trees = new uint64_t[m_num_sets]; for (unsigned i = 0; i < m_num_sets; i++) { m_trees[i] = 0; } @@ -96,7 +96,7 @@ } inline void -PseudoLRUPolicy::touch(int64 set, int64 index, Tick time) +PseudoLRUPolicy::touch(int64_t set, int64_t index, Tick time) { assert(index >= 0 && index < m_assoc); assert(set >= 0 && set < m_num_sets); @@ -114,11 +114,11 @@ m_last_ref_ptr[set][index] = time; } -inline int64 -PseudoLRUPolicy::getVictim(int64 set) const +inline int64_t +PseudoLRUPolicy::getVictim(int64_t set) const { // assert(m_assoc != 0); - int64 index = 0; + int64_t index = 0; int tree_index = 0; int node_val; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/RubyMemoryControl.hh --- a/src/mem/ruby/structures/RubyMemoryControl.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/RubyMemoryControl.hh Sun Jul 19 18:39:40 2015 -0500 @@ -162,11 +162,11 @@ // Each entry indicates number of address-bus cycles until bank // is reschedulable: - int* m_bankBusyCounter; - int* m_oldRequest; + int *m_bankBusyCounter; + int *m_oldRequest; - uint64* m_tfaw_shift; - int* m_tfaw_count; + uint64_t *m_tfaw_shift; + int *m_tfaw_count; // Each of these indicates number of address-bus cycles until // we can issue a new request of the corresponding type: @@ -182,12 +182,12 @@ int m_ageCounter; // age of old requests; to detect starvation int m_idleCount; // watchdog timer for shutting down - MemCntrlProfiler* m_profiler_ptr; + MemCntrlProfiler *m_profiler_ptr; class MemCntrlEvent : public Event { public: - MemCntrlEvent(RubyMemoryControl* _mem_cntrl) + MemCntrlEvent(RubyMemoryControl *_mem_cntrl) { mem_cntrl = _mem_cntrl; } diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/structures/RubyMemoryControl.cc --- a/src/mem/ruby/structures/RubyMemoryControl.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/structures/RubyMemoryControl.cc Sun Jul 19 18:39:40 2015 -0500 @@ -176,7 +176,7 @@ RubyMemoryControl::init() { m_msg_counter = 0; - assert(m_tFaw <= 62); // must fit in a uint64 shift register + assert(m_tFaw <= 62); // must fit in a uint64_t shift register m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel; m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel; @@ -213,7 +213,7 @@ // m_tfaw_count keeps track of how many 1 bits are set // in each shift register. When m_tfaw_count is >= 4, // new activates are not allowed. - m_tfaw_shift = new uint64[m_total_ranks]; + m_tfaw_shift = new uint64_t[m_total_ranks]; m_tfaw_count = new int[m_total_ranks]; for (int i = 0; i < m_total_ranks; i++) { m_tfaw_shift[i] = 0; @@ -236,7 +236,7 @@ { m_msg_counter = 0; - assert(m_tFaw <= 62); // must fit in a uint64 shift register + assert(m_tFaw <= 62); // must fit in a uint64_t shift register m_total_banks = m_banks_per_rank * m_ranks_per_dimm * m_dimms_per_channel; m_total_ranks = m_ranks_per_dimm * m_dimms_per_channel; diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/system/CacheRecorder.hh --- a/src/mem/ruby/system/CacheRecorder.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/system/CacheRecorder.hh Sun Jul 19 18:39:40 2015 -0500 @@ -77,7 +77,7 @@ void addRecord(int cntrl, Addr data_addr, Addr pc_addr, RubyRequestType type, Tick time, DataBlock& data); - uint64 aggregateRecords(uint8_t** data, uint64 size); + uint64_t aggregateRecords(uint8_t **data, uint64_t size); /*! * Function for flushing the memory contents of the caches to the diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/system/CacheRecorder.cc --- a/src/mem/ruby/system/CacheRecorder.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/system/CacheRecorder.cc Sun Jul 19 18:39:40 2015 -0500 @@ -157,13 +157,13 @@ m_records.push_back(rec); } -uint64 -CacheRecorder::aggregateRecords(uint8_t** buf, uint64 total_size) +uint64_t +CacheRecorder::aggregateRecords(uint8_t **buf, uint64_t total_size) { std::sort(m_records.begin(), m_records.end(), compareTraceRecords); int size = m_records.size(); - uint64 current_size = 0; + uint64_t current_size = 0; int record_size = sizeof(TraceRecord) + m_block_size_bytes; for (int i = 0; i < size; ++i) { diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/system/System.hh --- a/src/mem/ruby/system/System.hh Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/system/System.hh Sun Jul 19 18:39:40 2015 -0500 @@ -118,9 +118,9 @@ void readCompressedTrace(std::string filename, uint8_t *&raw_data, - uint64& uncompressed_trace_size); + uint64_t &uncompressed_trace_size); void writeCompressedTrace(uint8_t *raw_data, std::string file, - uint64 uncompressed_trace_size); + uint64_t uncompressed_trace_size); private: // configuration parameters diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/ruby/system/System.cc --- a/src/mem/ruby/system/System.cc Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/ruby/system/System.cc Sun Jul 19 18:39:40 2015 -0500 @@ -100,7 +100,7 @@ void RubySystem::writeCompressedTrace(uint8_t *raw_data, string filename, - uint64 uncompressed_trace_size) + uint64_t uncompressed_trace_size) { // Create the checkpoint file for the memory string thefile = CheckpointIn::dir() + "/" + filename.c_str(); @@ -152,7 +152,7 @@ // Store the cache-block size, so we are able to restore on systems with a // different cache-block size. CacheRecorder depends on the correct // cache-block size upon unserializing. - uint64 block_size_bytes = getBlockSizeBytes(); + uint64_t block_size_bytes = getBlockSizeBytes(); SERIALIZE_SCALAR(block_size_bytes); DPRINTF(RubyCacheTrace, "Recording Cache Trace\n"); @@ -185,7 +185,7 @@ // Aggregate the trace entries together into a single array uint8_t *raw_data = new uint8_t[4096]; - uint64 cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data, + uint64_t cache_trace_size = m_cache_recorder->aggregateRecords(&raw_data, 4096); string cache_trace_file = name() + ".cache.gz"; writeCompressedTrace(raw_data, cache_trace_file, cache_trace_size); @@ -198,7 +198,7 @@ void RubySystem::readCompressedTrace(string filename, uint8_t *&raw_data, - uint64& uncompressed_trace_size) + uint64_t &uncompressed_trace_size) { // Read the trace file gzFile compressedTrace; @@ -235,11 +235,11 @@ // This value should be set to the checkpoint-system's block-size. // Optional, as checkpoints without it can be run if the // checkpoint-system's block-size == current block-size. - uint64 block_size_bytes = getBlockSizeBytes(); + uint64_t block_size_bytes = getBlockSizeBytes(); UNSERIALIZE_OPT_SCALAR(block_size_bytes); string cache_trace_file; - uint64 cache_trace_size = 0; + uint64_t cache_trace_size = 0; UNSERIALIZE_SCALAR(cache_trace_file); UNSERIALIZE_SCALAR(cache_trace_size); diff -r 7cc3399e1f53 -r 514ddcac7c76 src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py Sun Jul 19 07:28:10 2015 -0500 +++ b/src/mem/slicc/symbols/StateMachine.py Sun Jul 19 18:39:40 2015 -0500 @@ -288,9 +288,9 @@ void countTransition(${ident}_State state, ${ident}_Event event); void possibleTransition(${ident}_State state, ${ident}_Event event); - uint64 getEventCount(${ident}_Event event); + uint64_t getEventCount(${ident}_Event event); bool isPossible(${ident}_State state, ${ident}_Event event); - uint64 getTransitionCount(${ident}_State state, ${ident}_Event event); + uint64_t getTransitionCount(${ident}_State state, ${ident}_Event event); private: ''') @@ -810,7 +810,7 @@ m_possible[state][event] = true; } -uint64 +uint64_t $c_ident::getEventCount(${ident}_Event event) { return m_event_counters[event]; @@ -822,7 +822,7 @@ return m_possible[state][event]; } -uint64 +uint64_t $c_ident::getTransitionCount(${ident}_State state, ${ident}_Event event) {