diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MESI_Three_Level-L0cache.sm --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -509,6 +509,19 @@ } } + action(sm_setMRU, "sm", desc="update replacement policy state") { + Icache.setMRU(address); + Dcache.setMRU(address); + } + + action(uic_setICacheMRU, "uic", desc="update replacement policy state") { + Icache.setMRU(cache_entry); + } + + action(udc_setDCacheMRU, "udc", desc="update replacement policy state") { + Dcache.setMRU(cache_entry); + } + action(ff_deallocateCacheBlock, "\f", desc="Deallocate L1 cache block.") { if (Dcache.isTagPresent(address)) { @@ -605,12 +618,14 @@ // Transitions from Shared transition({S,E,M}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition({S,E,M}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; @@ -637,6 +652,7 @@ // Transitions from Exclusive transition({E,M}, Store, M) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -682,6 +698,7 @@ transition(IS, Data, S) { u_writeDataToCache; + sm_setMRU; h_load_hit; s_deallocateTBE; o_popIncomingResponseQueue; @@ -690,6 +707,7 @@ transition(IS, Data_Exclusive, E) { u_writeDataToCache; + sm_setMRU; h_load_hit; s_deallocateTBE; o_popIncomingResponseQueue; @@ -698,6 +716,7 @@ transition(IS, Data_Stale, I) { u_writeDataToCache; + sm_setMRU; h_load_hit; s_deallocateTBE; o_popIncomingResponseQueue; @@ -706,6 +725,7 @@ transition({IM,SM}, Data_Exclusive, M) { u_writeDataToCache; + sm_setMRU; hh_store_hit; s_deallocateTBE; o_popIncomingResponseQueue; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MESI_Two_Level-L1cache.sm --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -880,6 +880,19 @@ } } + action(sm_setMRU, "sm", desc="update replacement policy state") { + L1Icache.setMRU(address); + L1Dcache.setMRU(address); + } + + action(uic_setICacheMRU, "uic", desc="update replacement policy state") { + L1Icache.setMRU(cache_entry); + } + + action(udc_setDCacheMRU, "udc", desc="update replacement policy state") { + L1Dcache.setMRU(cache_entry); + } + action(q_updateAckCount, "q", desc="Update ack count") { peek(responseL1Network_in, ResponseMsg) { assert(is_valid(tbe)); @@ -1074,12 +1087,14 @@ // Transitions from Shared transition({S,E,M}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition({S,E,M}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; @@ -1106,6 +1121,7 @@ // Transitions from Exclusive transition({E,M}, Store, M) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -1200,6 +1216,7 @@ transition(IS, Data_all_Acks, S) { u_writeDataToL1Cache; + sm_setMRU; hx_load_hit; s_deallocateTBE; o_popIncomingResponseQueue; @@ -1216,6 +1233,7 @@ transition(IS_I, Data_all_Acks, I) { u_writeDataToL1Cache; + sm_setMRU; hx_load_hit; s_deallocateTBE; o_popIncomingResponseQueue; @@ -1230,6 +1248,7 @@ transition(IS, DataS_fromL1, S) { u_writeDataToL1Cache; + sm_setMRU; j_sendUnblock; hx_load_hit; s_deallocateTBE; @@ -1247,6 +1266,7 @@ transition(IS_I, DataS_fromL1, I) { u_writeDataToL1Cache; + sm_setMRU; j_sendUnblock; hx_load_hit; s_deallocateTBE; @@ -1264,6 +1284,7 @@ // directory is blocked when sending exclusive data transition(IS_I, Data_Exclusive, E) { u_writeDataToL1Cache; + sm_setMRU; hx_load_hit; jj_sendExclusiveUnblock; s_deallocateTBE; @@ -1282,6 +1303,7 @@ transition(IS, Data_Exclusive, E) { u_writeDataToL1Cache; + sm_setMRU; hx_load_hit; jj_sendExclusiveUnblock; s_deallocateTBE; @@ -1323,6 +1345,7 @@ transition(IM, Data_all_Acks, M) { u_writeDataToL1Cache; + sm_setMRU; hhx_store_hit; jj_sendExclusiveUnblock; s_deallocateTBE; @@ -1354,6 +1377,7 @@ transition(SM, Ack_all, M) { jj_sendExclusiveUnblock; + sm_setMRU; hhx_store_hit; s_deallocateTBE; o_popIncomingResponseQueue; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MI_example-cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -353,6 +353,7 @@ action(r_load_hit, "r", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, false); } @@ -360,6 +361,7 @@ peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.readCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } @@ -368,6 +370,7 @@ action(s_store_hit, "s", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, false); } @@ -375,6 +378,7 @@ peek(responseNetwork_in, ResponseMsg) { assert(is_valid(cache_entry)); DPRINTF(RubySlicc,"%s\n", cache_entry.DataBlk); + cacheMemory.setMRU(cache_entry); sequencer.writeCallback(address, cache_entry.DataBlk, true, machineIDToMachineType(in_msg.Sender)); } diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -644,6 +644,8 @@ action(hx_load_hit, "hx", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); + L1Icache.setMRU(address); + L1Dcache.setMRU(address); sequencer.readCallback(address, cache_entry.DataBlk, true); } @@ -657,6 +659,8 @@ action(xx_store_hit, "\xx", desc="Notify sequencer that store completed.") { assert(is_valid(cache_entry)); DPRINTF(RubySlicc, "%s\n", cache_entry.DataBlk); + L1Icache.setMRU(address); + L1Dcache.setMRU(address); sequencer.writeCallback(address, cache_entry.DataBlk, true); cache_entry.Dirty := true; } @@ -850,6 +854,14 @@ } } + action(uic_setICacheMRU, "uic", desc="update replacement policy state") { + L1Icache.setMRU(cache_entry); + } + + action(udc_setDCacheMRU, "udc", desc="update replacement policy state") { + L1Dcache.setMRU(cache_entry); + } + action(kk_deallocateL1CacheBlock, "\k", desc="Deallocate cache block. Sets the cache to invalid, allowing a replacement in parallel with a fetch.") { if (L1Dcache.isTagPresent(address)) { L1Dcache.deallocate(address); @@ -958,12 +970,14 @@ } transition({S, SM, O, OM, MM, MM_W, M, M_W}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition({S, SM, O, OM, MM, MM_W, M, M_W}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; @@ -1035,6 +1049,7 @@ // Transitions from MM transition({MM, MM_W}, Store) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -1067,12 +1082,14 @@ // Transitions from M transition(M, Store, MM) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Store, MM_W) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -1284,6 +1284,18 @@ } } + action(sm_setMRU, "sm", desc="update replacement policy state") { + L1Icache.setMRU(address); + L1Dcache.setMRU(address); + } + + action(uic_setICacheMRU, "uic", desc="update replacement policy state") { + L1Icache.setMRU(cache_entry); + } + + action(udc_setDCacheMRU, "udc", desc="update replacement policy state") { + L1Dcache.setMRU(cache_entry); + } action(h_load_hit, "h", desc="Notify sequencer the load completed.") { assert(is_valid(cache_entry)); @@ -1696,12 +1708,14 @@ // Transitions from Shared transition({S, SM, S_L, SM_L}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition({S, SM, S_L, SM_L}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; @@ -1784,12 +1798,14 @@ // Transitions from Owned transition({O, OM}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; } transition({O, OM}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -1874,30 +1890,35 @@ // Transitions from Modified transition({MM, MM_W}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; } transition({MM, MM_W}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition({MM_W}, {Store, Atomic}) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(MM, Store) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(MM, Atomic, M) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -1949,36 +1970,42 @@ // Transitions from Dirty Exclusive transition({M, M_W}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileInstHit; k_popMandatoryQueue; } transition({M, M_W}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(M, Store, MM) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(M, Atomic) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Store, MM_W) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; } transition(M_W, Atomic) { + udc_setDCacheMRU; hh_store_hit; uu_profileDataHit; k_popMandatoryQueue; @@ -2146,6 +2173,7 @@ transition(IM, Data_All_Tokens, MM_W) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; o_scheduleUseTimeout; j_unsetReissueTimer; @@ -2168,6 +2196,7 @@ transition(SM, Data_All_Tokens, MM_W) { w_assertIncomingDataAndCacheDataMatch; q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; o_scheduleUseTimeout; j_unsetReissueTimer; @@ -2199,6 +2228,7 @@ transition(OM, Ack_All_Tokens, MM_W) { q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; o_scheduleUseTimeout; j_unsetReissueTimer; @@ -2215,6 +2245,7 @@ transition(OM, Data_All_Tokens, MM_W) { w_assertIncomingDataAndCacheDataMatch; q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; o_scheduleUseTimeout; j_unsetReissueTimer; @@ -2237,6 +2268,7 @@ transition(IS, Data_Shared, S) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; s_deallocateTBE; j_unsetReissueTimer; @@ -2247,6 +2279,7 @@ transition(IS, Data_Owner, O) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; s_deallocateTBE; j_unsetReissueTimer; @@ -2257,6 +2290,7 @@ transition(IS, Data_All_Tokens, M_W) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; o_scheduleUseTimeout; j_unsetReissueTimer; @@ -2345,6 +2379,7 @@ transition(IM_L, Data_All_Tokens, MM_W) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; j_unsetReissueTimer; o_scheduleUseTimeout; @@ -2355,6 +2390,7 @@ transition(SM_L, Data_All_Tokens, S_L) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; xx_external_store_hit; ff_sendDataWithAllButNorOneTokens; s_deallocateTBE; @@ -2365,6 +2401,7 @@ transition(IS_L, Data_Shared, I_L) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; s_deallocateTBE; e_sendAckWithCollectedTokens; @@ -2376,6 +2413,7 @@ transition(IS_L, Data_Owner, I_L) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; ee_sendDataWithAllTokens; s_deallocateTBE; @@ -2387,6 +2425,7 @@ transition(IS_L, Data_All_Tokens, M_W) { u_writeDataToCache; q_updateTokensFromResponse; + sm_setMRU; x_external_load_hit; j_unsetReissueTimer; o_scheduleUseTimeout; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Sat Aug 01 13:31:16 2015 -0500 @@ -1173,6 +1173,19 @@ } } + action(sm_setMRU, "sm", desc="update replacement policy state") { + L1Icache.setMRU(address); + L1Dcache.setMRU(address); + } + + action(uic_setICacheMRU, "uic", desc="update replacement policy state") { + L1Icache.setMRU(cache_entry); + } + + action(udc_setDCacheMRU, "udc", desc="update replacement policy state") { + L1Dcache.setMRU(cache_entry); + } + action(uf_writeDataToCacheTBE, "uf", desc="Write data to TBE") { peek(responseToCache_in, ResponseMsg) { assert(is_valid(tbe)); @@ -1502,18 +1515,21 @@ // Transitions from Shared transition({S, SM, ISM}, Load) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataHit; k_popMandatoryQueue; } transition({S, SM, ISM}, Ifetch) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstHit; k_popMandatoryQueue; } transition(SR, Load, S) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1522,6 +1538,7 @@ } transition(SR, Ifetch, S) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstMiss; uu_profileL2Hit; @@ -1564,18 +1581,21 @@ // Transitions from Owned transition({O, OM, SS, MM_W, M_W}, {Load}) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataHit; k_popMandatoryQueue; } transition({O, OM, SS, MM_W, M_W}, {Ifetch}) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstHit; k_popMandatoryQueue; } transition(OR, Load, O) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1584,6 +1604,7 @@ } transition(OR, Ifetch, O) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstMiss; uu_profileL2Hit; @@ -1635,24 +1656,28 @@ // Transitions from Modified transition({MM, M}, {Ifetch}) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstHit; k_popMandatoryQueue; } transition({MM, M}, {Load}) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataHit; k_popMandatoryQueue; } transition(MM, Store) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataHit; k_popMandatoryQueue; } transition(MMR, Load, MM) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1661,6 +1686,7 @@ } transition(MMR, Ifetch, MM) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstMiss; uu_profileL2Hit; @@ -1669,6 +1695,7 @@ } transition(MMR, Store, MM) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1728,12 +1755,14 @@ // Transitions from Dirty Exclusive transition(M, Store, MM) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataHit; k_popMandatoryQueue; } transition(MR, Load, M) { + udc_setDCacheMRU; h_load_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1742,6 +1771,7 @@ } transition(MR, Ifetch, M) { + uic_setICacheMRU; h_load_hit; uu_profileL1InstMiss; uu_profileL2Hit; @@ -1750,6 +1780,7 @@ } transition(MR, Store, MM) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataMiss; uu_profileL2Hit; @@ -1817,6 +1848,7 @@ u_writeDataToCache; m_decrementNumberOfMessages; o_checkForCompletion; + sm_setMRU; sx_external_store_hit; n_popResponseQueue; kd_wakeUpDependents; @@ -1875,6 +1907,7 @@ } transition(ISM, All_acks_no_sharers, MM) { + sm_setMRU; sxt_trig_ext_store_hit; gm_sendUnblockM; s_deallocateTBE; @@ -1931,6 +1964,7 @@ } transition(OM, {All_acks, All_acks_no_sharers}, MM) { + sm_setMRU; sxt_trig_ext_store_hit; gm_sendUnblockM; s_deallocateTBE; @@ -1967,6 +2001,7 @@ u_writeDataToCache; m_decrementNumberOfMessages; o_checkForCompletion; + sm_setMRU; hx_external_load_hit; uo_updateCurrentOwner; n_popResponseQueue; @@ -1977,6 +2012,7 @@ u_writeDataToCache; m_decrementNumberOfMessages; o_checkForCompletion; + sm_setMRU; hx_external_load_hit; n_popResponseQueue; kd_wakeUpDependents; @@ -1987,6 +2023,7 @@ r_setSharerBit; m_decrementNumberOfMessages; o_checkForCompletion; + sm_setMRU; hx_external_load_hit; uo_updateCurrentOwner; n_popResponseQueue; @@ -2026,6 +2063,7 @@ // Transitions from MM_W transition(MM_W, Store) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataHit; k_popMandatoryQueue; @@ -2052,6 +2090,7 @@ // Transitions from M_W transition(M_W, Store, MM_W) { + udc_setDCacheMRU; hh_store_hit; uu_profileL1DataHit; k_popMandatoryQueue; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/protocol/RubySlicc_Types.sm Sat Aug 01 13:31:16 2015 -0500 @@ -156,6 +156,7 @@ Cycles getTagLatency(); Cycles getDataLatency(); void setMRU(Addr); + void setMRU(AbstractCacheEntry); void recordRequestType(CacheRequestType, Addr); bool checkResourceAvailable(CacheResourceType, Addr); diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/ruby/structures/CacheMemory.hh --- a/src/mem/ruby/structures/CacheMemory.hh Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/ruby/structures/CacheMemory.hh Sat Aug 01 13:31:16 2015 -0500 @@ -107,6 +107,8 @@ // Set this address to most recently used void setMRU(Addr address); + // Set this entry to most recently used + void setMRU(const AbstractCacheEntry *e); // Functions for locking and unlocking cache lines corresponding to the // provided address. These are required for supporting atomic memory diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/ruby/structures/CacheMemory.cc --- a/src/mem/ruby/structures/CacheMemory.cc Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/ruby/structures/CacheMemory.cc Sat Aug 01 13:31:16 2015 -0500 @@ -345,6 +345,14 @@ } void +CacheMemory::setMRU(const AbstractCacheEntry *e) +{ + uint32_t cacheSet = e->getSetIndex(); + uint32_t loc = e->getWayIndex(); + m_replacementPolicy_ptr->touch(cacheSet, loc, curTick()); +} + +void CacheMemory::recordCacheContents(int cntrl, CacheRecorder* tr) const { uint64_t warmedUpBlocks = 0; diff -r 5e30c6894ce3 -r d9b0c6ae77b1 src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Sat Aug 01 13:00:57 2015 -0500 +++ b/src/mem/ruby/system/Sequencer.cc Sat Aug 01 13:31:16 2015 -0500 @@ -494,17 +494,9 @@ { PacketPtr pkt = srequest->pkt; Addr request_address(pkt->getAddr()); - Addr request_line_address = makeLineAddress(pkt->getAddr()); RubyRequestType type = srequest->m_type; Cycles issued_time = srequest->issue_time; - // Set this cache entry to the most recently used - if (type == RubyRequestType_IFETCH) { - m_instCache_ptr->setMRU(request_line_address); - } else { - m_dataCache_ptr->setMRU(request_line_address); - } - assert(curCycle() >= issued_time); Cycles total_latency = curCycle() - issued_time;