diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Three_Level-L0cache.sm --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -135,6 +135,8 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); + Cycles ticksToCycles(Tick t); void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); void set_tbe(TBE a); @@ -255,7 +257,7 @@ // Messages for this L0 cache from the L1 cache in_port(messgeBuffer_in, CoherenceMsg, bufferFromL1, rank = 1) { - if (messgeBuffer_in.isReady()) { + if (messgeBuffer_in.isReady(clockEdge())) { peek(messgeBuffer_in, CoherenceMsg, block_on="addr") { assert(in_msg.Dest == machineID); @@ -291,7 +293,7 @@ // Mandatory Queue betweens Node's CPU and it's L0 caches in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank = 0) { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -483,17 +485,19 @@ } action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") { - profileMsgDelay(2, messgeBuffer_in.dequeue()); + Tick delay := messgeBuffer_in.dequeue(clockEdge()); + profileMsgDelay(2, ticksToCycles(delay)); } action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") { - profileMsgDelay(1, messgeBuffer_in.dequeue()); + Tick delay := messgeBuffer_in.dequeue(clockEdge()); + profileMsgDelay(1, ticksToCycles(delay)); } action(s_deallocateTBE, "s", desc="Deallocate TBE") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Three_Level-L1cache.sm --- a/src/mem/protocol/MESI_Three_Level-L1cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -154,6 +154,8 @@ int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; + Tick clockEdge(); + Cycles ticksToCycles(Tick t); void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); void set_tbe(TBE a); @@ -269,7 +271,7 @@ // Response From the L2 Cache to this L1 cache in_port(responseNetwork_in, ResponseMsg, responseFromL2, rank = 3) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); @@ -307,7 +309,7 @@ // Request to this L1 cache from the shared L2 in_port(requestNetwork_in, RequestMsg, requestFromL2, rank = 2) { - if(requestNetwork_in.isReady()) { + if(requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.addr); @@ -344,7 +346,7 @@ // Requests to this L1 cache from the L0 cache. in_port(messageBufferFromL0_in, CoherenceMsg, bufferFromL0, rank = 0) { - if (messageBufferFromL0_in.isReady()) { + if (messageBufferFromL0_in.isReady(clockEdge())) { peek(messageBufferFromL0_in, CoherenceMsg) { Entry cache_entry := getCacheEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -653,17 +655,19 @@ } action(k_popL0RequestQueue, "k", desc="Pop mandatory queue.") { - messageBufferFromL0_in.dequeue(); + messageBufferFromL0_in.dequeue(clockEdge()); } action(l_popL2RequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") { - profileMsgDelay(2, requestNetwork_in.dequeue()); + Tick delay := requestNetwork_in.dequeue(clockEdge()); + profileMsgDelay(2, ticksToCycles(delay)); } action(o_popL2ResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") { - profileMsgDelay(1, responseNetwork_in.dequeue()); + Tick delay := responseNetwork_in.dequeue(clockEdge()); + profileMsgDelay(1, ticksToCycles(delay)); } action(s_deallocateTBE, "s", desc="Deallocate TBE") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Two_Level-L1cache.sm --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -155,6 +155,8 @@ int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; + Tick clockEdge(); + Cycles ticksToCycles(Tick t); void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); void set_tbe(TBE a); @@ -295,7 +297,7 @@ // searches of all entries in the queue, not just the head msg. All // msgs in the structure can be invalidated if a demand miss matches. in_port(optionalQueue_in, RubyRequest, optionalQueue, desc="...", rank = 3) { - if (optionalQueue_in.isReady()) { + if (optionalQueue_in.isReady(clockEdge())) { peek(optionalQueue_in, RubyRequest) { // Instruction Prefetch if (in_msg.Type == RubyRequestType:IFETCH) { @@ -372,7 +374,7 @@ // Response L1 Network - response msg to this L1 cache in_port(responseL1Network_in, ResponseMsg, responseToL1Cache, rank = 2) { - if (responseL1Network_in.isReady()) { + if (responseL1Network_in.isReady(clockEdge())) { peek(responseL1Network_in, ResponseMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); @@ -412,7 +414,7 @@ // Request InterChip network - request from this L1 cache to the shared L2 in_port(requestL1Network_in, RequestMsg, requestToL1Cache, rank = 1) { - if(requestL1Network_in.isReady()) { + if(requestL1Network_in.isReady(clockEdge())) { peek(requestL1Network_in, RequestMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); @@ -438,7 +440,7 @@ // Mandatory Queue betweens Node's CPU and it's L1 caches in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank = 0) { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -854,17 +856,19 @@ } action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(l_popRequestQueue, "l", desc="Pop incoming request queue and profile the delay within this virtual network") { - profileMsgDelay(2, requestL1Network_in.dequeue()); + Tick delay := requestL1Network_in.dequeue(clockEdge()); + profileMsgDelay(2, ticksToCycles(delay)); } action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue and profile the delay within this virtual network") { - profileMsgDelay(1, responseL1Network_in.dequeue()); + Tick delay := responseL1Network_in.dequeue(clockEdge()); + profileMsgDelay(1, ticksToCycles(delay)); } action(s_deallocateTBE, "s", desc="Deallocate TBE") { @@ -964,7 +968,7 @@ } action(pq_popPrefetchQueue, "\pq", desc="Pop the prefetch request queue") { - optionalQueue_in.dequeue(); + optionalQueue_in.dequeue(clockEdge()); } action(mp_markPrefetched, "mp", desc="Write data from response queue to cache") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Two_Level-L2cache.sm --- a/src/mem/protocol/MESI_Two_Level-L2cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -31,6 +31,7 @@ Cycles l2_request_latency := 2; Cycles l2_response_latency := 2; Cycles to_l1_latency := 1; + Cycles recycle_latency := 10; // Message Queues // From local bank of L2 cache TO the network @@ -148,6 +149,10 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); + Cycles ticksToCycles(Tick t); + void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); void set_tbe(TBE a); @@ -285,7 +290,7 @@ in_port(L1unblockNetwork_in, ResponseMsg, unblockToL2Cache, rank = 2) { - if(L1unblockNetwork_in.isReady()) { + if(L1unblockNetwork_in.isReady(clockEdge())) { peek(L1unblockNetwork_in, ResponseMsg) { Entry cache_entry := getCacheEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -307,7 +312,7 @@ // Response L2 Network - response msg to this particular L2 bank in_port(responseL2Network_in, ResponseMsg, responseToL2Cache, rank = 1) { - if (responseL2Network_in.isReady()) { + if (responseL2Network_in.isReady(clockEdge())) { peek(responseL2Network_in, ResponseMsg) { // test wether it's from a local L1 or an off chip source assert(in_msg.Destination.isElement(machineID)); @@ -348,7 +353,7 @@ // L1 Request in_port(L1RequestL2Network_in, RequestMsg, L1RequestToL2Cache, rank = 0) { - if(L1RequestL2Network_in.isReady()) { + if(L1RequestL2Network_in.isReady(clockEdge())) { peek(L1RequestL2Network_in, RequestMsg) { Entry cache_entry := getCacheEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -604,15 +609,18 @@ } action(jj_popL1RequestQueue, "\j", desc="Pop incoming L1 request queue") { - profileMsgDelay(0, L1RequestL2Network_in.dequeue()); + Tick delay := L1RequestL2Network_in.dequeue(clockEdge()); + profileMsgDelay(0, ticksToCycles(delay)); } action(k_popUnblockQueue, "k", desc="Pop incoming unblock queue") { - profileMsgDelay(0, L1unblockNetwork_in.dequeue()); + Tick delay := L1unblockNetwork_in.dequeue(clockEdge()); + profileMsgDelay(0, ticksToCycles(delay)); } action(o_popIncomingResponseQueue, "o", desc="Pop Incoming Response queue") { - profileMsgDelay(1, responseL2Network_in.dequeue()); + Tick delay := responseL2Network_in.dequeue(clockEdge()); + profileMsgDelay(1, ticksToCycles(delay)); } action(m_writeDataToCache, "m", desc="Write data from response queue to cache") { @@ -769,7 +777,7 @@ } action(zn_recycleResponseNetwork, "zn", desc="recycle memory request") { - responseL2Network_in.recycle(); + responseL2Network_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(kd_wakeUpDependents, "kd", desc="wake-up dependents") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Two_Level-dir.sm --- a/src/mem/protocol/MESI_Two_Level-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -30,6 +30,7 @@ : DirectoryMemory * directory; Cycles to_mem_ctrl_latency := 1; Cycles directory_latency := 6; + Cycles recycle_latency := 10; MessageBuffer * requestToDir, network="From", virtual_network="0", ordered="false", vnet_type="request"; @@ -96,6 +97,8 @@ // ** OBJECTS ** TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_tbe(TBE tbe); void unset_tbe(); void wakeUpBuffers(Addr a); @@ -189,7 +192,7 @@ // ** IN_PORTS ** in_port(requestNetwork_in, RequestMsg, requestToDir, rank = 0) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (isGETRequest(in_msg.Type)) { @@ -209,7 +212,7 @@ } in_port(responseNetwork_in, ResponseMsg, responseToDir, rank = 1) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceResponseType:MEMORY_DATA) { @@ -226,7 +229,7 @@ // off-chip memory request/response is done in_port(memQueue_in, MemoryMsg, responseFromMemory, rank = 2) { - if (memQueue_in.isReady()) { + if (memQueue_in.isReady(clockEdge())) { peek(memQueue_in, MemoryMsg) { if (in_msg.Type == MemoryRequestType:MEMORY_READ) { trigger(Event:Memory_Data, in_msg.addr, TBEs.lookup(in_msg.addr)); @@ -285,15 +288,15 @@ } action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(k_popIncomingResponseQueue, "k", desc="Pop incoming request queue") { - responseNetwork_in.dequeue(); + responseNetwork_in.dequeue(clockEdge()); } action(l_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); + memQueue_in.dequeue(clockEdge()); } action(kd_wakeUpDependents, "kd", desc="wake-up dependents") { @@ -321,7 +324,7 @@ } action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(dr_sendDMAData, "dr", desc="Send Data to DMA controller from directory") { @@ -358,7 +361,7 @@ } action(zz_recycleDMAQueue, "zz", desc="recycle DMA queue") { - requestNetwork_in.recycle(); + requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(inv_sendCacheInvalidate, "inv", desc="Invalidate a cache block") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MESI_Two_Level-dma.sm --- a/src/mem/protocol/MESI_Two_Level-dma.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dma.sm Tue Jul 21 10:26:32 2015 -0500 @@ -51,6 +51,7 @@ MessageBuffer mandatoryQueue, ordered="false"; State cur_state; + Tick clockEdge(); State getState(Addr addr) { return cur_state; @@ -78,7 +79,7 @@ out_port(requestToDir_out, RequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress); @@ -92,7 +93,7 @@ } in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") { - if (dmaResponseQueue_in.isReady()) { + if (dmaResponseQueue_in.isReady(clockEdge())) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:ACK) { trigger(Event:Ack, makeLineAddress(in_msg.addr)); @@ -142,11 +143,11 @@ } action(p_popRequestQueue, "p", desc="Pop request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(p_popResponseQueue, "\p", desc="Pop request queue") { - dmaResponseQueue_in.dequeue(); + dmaResponseQueue_in.dequeue(clockEdge()); } transition(READY, ReadRequest, BUSY_RD) { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MI_example-cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -104,6 +104,8 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; // PROTOTYPES + Tick clockEdge(); + Cycles ticksToCycles(Tick t); void set_cache_entry(AbstractCacheEntry a); void unset_cache_entry(); void set_tbe(TBE b); @@ -201,7 +203,7 @@ out_port(responseNetwork_out, ResponseMsg, responseFromCache); in_port(forwardRequestNetwork_in, RequestMsg, forwardToCache) { - if (forwardRequestNetwork_in.isReady()) { + if (forwardRequestNetwork_in.isReady(clockEdge())) { peek(forwardRequestNetwork_in, RequestMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); @@ -227,7 +229,7 @@ } in_port(responseNetwork_in, ResponseMsg, responseToCache) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); @@ -245,7 +247,7 @@ // Mandatory Queue in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { Entry cache_entry := getCacheEntry(in_msg.LineAddress); @@ -331,15 +333,17 @@ } action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(n_popResponseQueue, "n", desc="Pop the response queue") { - profileMsgDelay(1, responseNetwork_in.dequeue()); + Tick delay := responseNetwork_in.dequeue(clockEdge()); + profileMsgDelay(1, ticksToCycles(delay)); } action(o_popForwardedRequestQueue, "o", desc="Pop the forwarded request queue") { - profileMsgDelay(2, forwardRequestNetwork_in.dequeue()); + Tick delay := forwardRequestNetwork_in.dequeue(clockEdge()); + profileMsgDelay(2, ticksToCycles(delay)); } action(p_profileMiss, "pi", desc="Profile cache miss") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MI_example-dir.sm --- a/src/mem/protocol/MI_example-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MI_example-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -31,6 +31,7 @@ : DirectoryMemory * directory; Cycles directory_latency := 12; Cycles to_memory_controller_latency := 1; + Cycles recycle_latency := 1; MessageBuffer * forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward"; @@ -107,6 +108,9 @@ // ** OBJECTS ** TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); + Cycles ticksToCycles(Tick t); + Tick cyclesToTicks(Cycles c); void set_tbe(TBE b); void unset_tbe(); @@ -203,7 +207,7 @@ // ** IN_PORTS ** in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, DMARequestMsg) { TBE tbe := TBEs.lookup(in_msg.LineAddress); if (in_msg.Type == DMARequestType:READ) { @@ -218,7 +222,7 @@ } in_port(requestQueue_in, RequestMsg, requestToDir) { - if (requestQueue_in.isReady()) { + if (requestQueue_in.isReady(clockEdge())) { peek(requestQueue_in, RequestMsg) { TBE tbe := TBEs.lookup(in_msg.addr); if (in_msg.Type == CoherenceRequestType:GETS) { @@ -241,7 +245,7 @@ //added by SS // off-chip memory request/response is done in_port(memQueue_in, MemoryMsg, responseFromMemory) { - if (memQueue_in.isReady()) { + if (memQueue_in.isReady(clockEdge())) { peek(memQueue_in, MemoryMsg) { TBE tbe := TBEs.lookup(in_msg.addr); if (in_msg.Type == MemoryRequestType:MEMORY_READ) { @@ -391,11 +395,11 @@ } action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") { - requestQueue_in.dequeue(); + requestQueue_in.dequeue(clockEdge()); } action(p_popIncomingDMARequestQueue, "p", desc="Pop incoming DMA queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(v_allocateTBE, "v", desc="Allocate TBE") { @@ -431,11 +435,11 @@ } action(z_recycleRequestQueue, "z", desc="recycle request queue") { - requestQueue_in.recycle(); + requestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(y_recycleDMARequestQueue, "y", desc="recycle dma request queue") { - dmaRequestQueue_in.recycle(); + dmaRequestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } @@ -475,7 +479,7 @@ } action(l_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); + memQueue_in.dequeue(clockEdge()); } // TRANSITIONS diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MI_example-dma.sm --- a/src/mem/protocol/MI_example-dma.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MI_example-dma.sm Tue Jul 21 10:26:32 2015 -0500 @@ -52,6 +52,9 @@ MessageBuffer mandatoryQueue, ordered="false"; State cur_state; + Tick clockEdge(); + Cycles ticksToCycles(Tick t); + State getState(Addr addr) { return cur_state; } @@ -77,7 +80,7 @@ out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress); @@ -91,7 +94,7 @@ } in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") { - if (dmaResponseQueue_in.isReady()) { + if (dmaResponseQueue_in.isReady(clockEdge())) { peek( dmaResponseQueue_in, DMAResponseMsg) { if (in_msg.Type == DMAResponseType:ACK) { trigger(Event:Ack, in_msg.LineAddress); @@ -147,11 +150,11 @@ } action(p_popRequestQueue, "p", desc="Pop request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(p_popResponseQueue, "\p", desc="Pop request queue") { - dmaResponseQueue_in.dequeue(); + dmaResponseQueue_in.dequeue(clockEdge()); } transition(READY, ReadRequest, BUSY_RD) { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -33,6 +33,7 @@ int l2_select_num_bits; Cycles request_latency := 2; Cycles use_timeout_latency := 50; + Cycles recycle_latency := 10; bool send_evictions; // Message Queues @@ -129,6 +130,8 @@ bool isPresent(Addr); } + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE b); @@ -266,16 +269,16 @@ // Use Timer in_port(useTimerTable_in, Addr, useTimerTable) { - if (useTimerTable_in.isReady()) { - trigger(Event:Use_Timeout, useTimerTable.readyAddress(), - getCacheEntry(useTimerTable.readyAddress()), - TBEs.lookup(useTimerTable.readyAddress())); + if (useTimerTable_in.isReady(clockEdge())) { + Addr readyAddress := useTimerTable.nextAddress(); + trigger(Event:Use_Timeout, readyAddress, getCacheEntry(readyAddress), + TBEs.lookup(readyAddress)); } } // Trigger Queue in_port(triggerQueue_in, TriggerMsg, triggerQueue) { - if (triggerQueue_in.isReady()) { + if (triggerQueue_in.isReady(clockEdge())) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { trigger(Event:All_acks, in_msg.addr, @@ -291,7 +294,7 @@ // Request Network in_port(requestNetwork_in, RequestMsg, requestToL1Cache) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); DPRINTF(RubySlicc, "L1 received: %s\n", in_msg.Type); @@ -331,7 +334,7 @@ // Response Network in_port(responseToL1Cache_in, ResponseMsg, responseToL1Cache) { - if (responseToL1Cache_in.isReady()) { + if (responseToL1Cache_in.isReady(clockEdge())) { peek(responseToL1Cache_in, ResponseMsg, block_on="addr") { if (in_msg.Type == CoherenceResponseType:ACK) { trigger(Event:Ack, in_msg.addr, @@ -352,7 +355,7 @@ // Nothing from the unblock network // Mandatory Queue betweens Node's CPU and it's L1 caches in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -675,7 +678,7 @@ } action(j_popTriggerQueue, "j", desc="Pop trigger queue.") { - triggerQueue_in.dequeue(); + triggerQueue_in.dequeue(clockEdge()); } action(jj_unsetUseTimer, "\jj", desc="Unset use timer.") { @@ -683,11 +686,11 @@ } action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(m_decrementNumberOfMessages, "m", desc="Decrement the number of messages for which we're waiting") { @@ -706,7 +709,7 @@ } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseToL1Cache_in.dequeue(); + responseToL1Cache_in.dequeue(clockEdge()); } action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") { @@ -720,7 +723,8 @@ } action(o_scheduleUseTimeout, "oo", desc="Schedule a use timeout.") { - useTimerTable.set(address, use_timeout_latency); + useTimerTable.set(address, + clockEdge() + cyclesToTicks(use_timeout_latency)); } action(ub_dmaUnblockL2Cache, "ub", desc="Send dma ack to l2 cache") { @@ -907,11 +911,11 @@ } action(z_recycleRequestQueue, "z", desc="Send the head of the mandatory queue to the back of the queue.") { - requestNetwork_in.recycle(); + requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(zz_recycleMandatoryQueue, "\z", desc="Send the head of the mandatory queue to the back of the queue.") { - mandatoryQueue_in.recycle(); + mandatoryQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } //***************************************************** diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -30,6 +30,7 @@ : CacheMemory * L2cache; Cycles response_latency := 2; Cycles request_latency := 2; + Cycles recycle_latency := 10; // L2 BANK QUEUES // From local bank of L2 cache TO the network @@ -226,6 +227,8 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; PerfectCacheMemory localDirectory, template=""; + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE b); @@ -557,7 +560,7 @@ // Trigger Queue in_port(triggerQueue_in, TriggerMsg, triggerQueue) { - if (triggerQueue_in.isReady()) { + if (triggerQueue_in.isReady(clockEdge())) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { trigger(Event:All_Acks, in_msg.addr, @@ -572,7 +575,7 @@ // Request Network in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg) { if (in_msg.Type == CoherenceRequestType:GETX || in_msg.Type == CoherenceRequestType:DMA_WRITE) { if (in_msg.Requestor == machineID) { @@ -605,7 +608,7 @@ } in_port(L1requestNetwork_in, RequestMsg, L1RequestToL2Cache) { - if (L1requestNetwork_in.isReady()) { + if (L1requestNetwork_in.isReady(clockEdge())) { peek(L1requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceRequestType:GETX) { @@ -640,7 +643,7 @@ // Response Network in_port(responseNetwork_in, ResponseMsg, responseToL2Cache) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceResponseType:ACK) { @@ -1344,7 +1347,7 @@ } action(m_popRequestQueue, "m", desc="Pop request queue.") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(m_decrementNumberOfMessagesInt, "\m", desc="Decrement the number of messages for which we're waiting") { @@ -1369,15 +1372,15 @@ } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseNetwork_in.dequeue(); + responseNetwork_in.dequeue(clockEdge()); } action(n_popTriggerQueue, "\n", desc="Pop trigger queue.") { - triggerQueue_in.dequeue(); + triggerQueue_in.dequeue(clockEdge()); } action(o_popL1RequestQueue, "o", desc="Pop L1 request queue.") { - L1requestNetwork_in.dequeue(); + L1requestNetwork_in.dequeue(clockEdge()); } @@ -1516,21 +1519,21 @@ peek(L1requestNetwork_in, RequestMsg) { APPEND_TRANSITION_COMMENT(in_msg.Requestor); } - L1requestNetwork_in.recycle(); + L1requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(zz_recycleRequestQueue, "\zz", desc="Send the head of the mandatory queue to the back of the queue.") { peek(requestNetwork_in, RequestMsg) { APPEND_TRANSITION_COMMENT(in_msg.Requestor); } - requestNetwork_in.recycle(); + requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(zz_recycleResponseQueue, "\z\z", desc="Send the head of the mandatory queue to the back of the queue.") { peek(responseNetwork_in, ResponseMsg) { APPEND_TRANSITION_COMMENT(in_msg.Sender); } - responseNetwork_in.recycle(); + responseNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(da_sendDmaAckUnblock, "da", desc="Send dma ack to global directory") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_directory-dir.sm --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -30,6 +30,7 @@ : DirectoryMemory * directory; Cycles directory_latency := 6; Cycles to_memory_controller_latency := 1; + Cycles recycle_latency := 10; // Message Queues MessageBuffer * requestToDir, network="From", virtual_network="1", @@ -118,6 +119,8 @@ // ** OBJECTS ** TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_tbe(TBE b); void unset_tbe(); @@ -228,7 +231,7 @@ // ** IN_PORTS ** in_port(unblockNetwork_in, ResponseMsg, responseToDir) { - if (unblockNetwork_in.isReady()) { + if (unblockNetwork_in.isReady(clockEdge())) { peek(unblockNetwork_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:UNBLOCK) { if (getDirectoryEntry(in_msg.addr).WaitingUnblocks == 1) { @@ -261,7 +264,7 @@ } in_port(requestQueue_in, RequestMsg, requestToDir) { - if (requestQueue_in.isReady()) { + if (requestQueue_in.isReady(clockEdge())) { peek(requestQueue_in, RequestMsg) { if (in_msg.Type == CoherenceRequestType:GETS) { trigger(Event:GETS, in_msg.addr, TBEs.lookup(in_msg.addr)); @@ -288,7 +291,7 @@ // off-chip memory request/response is done in_port(memQueue_in, MemoryMsg, responseFromMemory) { - if (memQueue_in.isReady()) { + if (memQueue_in.isReady(clockEdge())) { peek(memQueue_in, MemoryMsg) { if (in_msg.Type == MemoryRequestType:MEMORY_READ) { trigger(Event:Memory_Data, in_msg.addr, TBEs.lookup(in_msg.addr)); @@ -438,11 +441,11 @@ } action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") { - requestQueue_in.dequeue(); + requestQueue_in.dequeue(clockEdge()); } action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") { - unblockNetwork_in.dequeue(); + unblockNetwork_in.dequeue(clockEdge()); } action(m_addUnlockerToSharers, "m", desc="Add the unlocker to the sharer list") { @@ -461,7 +464,7 @@ } action(q_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); + memQueue_in.dequeue(clockEdge()); } action(qf_queueMemoryFetchRequest, "qf", desc="Queue off-chip fetch request") { @@ -501,7 +504,7 @@ } action(zz_recycleRequest, "\z", desc="Recycle the request queue") { - requestQueue_in.recycle(); + requestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(a_sendDMAAck, "\a", desc="Send DMA Ack that write completed, along with Inv Ack count") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_directory-dma.sm --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Tue Jul 21 10:26:32 2015 -0500 @@ -74,6 +74,7 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; State cur_state; + Tick clockEdge(); void set_tbe(TBE b); void unset_tbe(); @@ -104,7 +105,7 @@ out_port(triggerQueue_out, TriggerMsg, triggerQueue, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress, @@ -120,7 +121,7 @@ } in_port(dmaResponseQueue_in, ResponseMsg, responseFromDir, desc="...") { - if (dmaResponseQueue_in.isReady()) { + if (dmaResponseQueue_in.isReady(clockEdge())) { peek( dmaResponseQueue_in, ResponseMsg) { if (in_msg.Type == CoherenceResponseType:DMA_ACK) { trigger(Event:DMA_Ack, makeLineAddress(in_msg.addr), @@ -141,7 +142,7 @@ // Trigger Queue in_port(triggerQueue_in, TriggerMsg, triggerQueue) { - if (triggerQueue_in.isReady()) { + if (triggerQueue_in.isReady(clockEdge())) { peek(triggerQueue_in, TriggerMsg) { if (in_msg.Type == TriggerType:ALL_ACKS) { trigger(Event:All_Acks, in_msg.addr, TBEs.lookup(in_msg.addr)); @@ -215,15 +216,15 @@ } action(p_popRequestQueue, "p", desc="Pop request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(p_popResponseQueue, "\p", desc="Pop request queue") { - dmaResponseQueue_in.dequeue(); + dmaResponseQueue_in.dequeue(clockEdge()); } action(p_popTriggerQueue, "pp", desc="Pop trigger queue") { - triggerQueue_in.dequeue(); + triggerQueue_in.dequeue(clockEdge()); } action(t_updateTBEData, "t", desc="Update TBE Data") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -184,6 +184,8 @@ int countReadStarvingForAddress(Addr); } + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE b); @@ -458,25 +460,26 @@ // Use Timer in_port(useTimerTable_in, Addr, useTimerTable, rank=5) { - if (useTimerTable_in.isReady()) { - TBE tbe := L1_TBEs.lookup(useTimerTable.readyAddress()); + if (useTimerTable_in.isReady(clockEdge())) { + Addr readyAddress := useTimerTable.nextAddress(); + TBE tbe := L1_TBEs.lookup(readyAddress); - if (persistentTable.isLocked(useTimerTable.readyAddress()) && - (persistentTable.findSmallest(useTimerTable.readyAddress()) != machineID)) { - if (persistentTable.typeOfSmallest(useTimerTable.readyAddress()) == AccessType:Write) { - trigger(Event:Use_TimeoutStarverX, useTimerTable.readyAddress(), - getCacheEntry(useTimerTable.readyAddress()), tbe); + if (persistentTable.isLocked(readyAddress) && + (persistentTable.findSmallest(readyAddress) != machineID)) { + if (persistentTable.typeOfSmallest(readyAddress) == AccessType:Write) { + trigger(Event:Use_TimeoutStarverX, readyAddress, + getCacheEntry(readyAddress), tbe); } else { - trigger(Event:Use_TimeoutStarverS, useTimerTable.readyAddress(), - getCacheEntry(useTimerTable.readyAddress()), tbe); + trigger(Event:Use_TimeoutStarverS, readyAddress, + getCacheEntry(readyAddress), tbe); } } else { if (no_mig_atomic && IsAtomic(tbe)) { - trigger(Event:Use_TimeoutNoStarvers_NoMig, useTimerTable.readyAddress(), - getCacheEntry(useTimerTable.readyAddress()), tbe); + trigger(Event:Use_TimeoutNoStarvers_NoMig, readyAddress, + getCacheEntry(readyAddress), tbe); } else { - trigger(Event:Use_TimeoutNoStarvers, useTimerTable.readyAddress(), - getCacheEntry(useTimerTable.readyAddress()), tbe); + trigger(Event:Use_TimeoutNoStarvers, readyAddress, + getCacheEntry(readyAddress), tbe); } } } @@ -484,16 +487,17 @@ // Reissue Timer in_port(reissueTimerTable_in, Addr, reissueTimerTable, rank=4) { - if (reissueTimerTable_in.isReady()) { - trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(), - getCacheEntry(reissueTimerTable.readyAddress()), - L1_TBEs.lookup(reissueTimerTable.readyAddress())); + Tick current_time := clockEdge(); + if (reissueTimerTable_in.isReady(current_time)) { + Addr addr := reissueTimerTable.nextAddress(); + trigger(Event:Request_Timeout, addr, getCacheEntry(addr), + L1_TBEs.lookup(addr)); } } // Persistent Network in_port(persistentNetwork_in, PersistentMsg, persistentToL1Cache, rank=3) { - if (persistentNetwork_in.isReady()) { + if (persistentNetwork_in.isReady(clockEdge())) { peek(persistentNetwork_in, PersistentMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); @@ -543,7 +547,7 @@ // Response Network in_port(responseNetwork_in, ResponseMsg, responseToL1Cache, rank=2) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); @@ -614,7 +618,7 @@ // Request Network in_port(requestNetwork_in, RequestMsg, requestToL1Cache) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg, block_on="addr") { assert(in_msg.Destination.isElement(machineID)); @@ -661,7 +665,7 @@ // Mandatory Queue in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -794,7 +798,7 @@ // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, reissue_wakeup_latency); + reissueTimerTable.set(address, cyclesToTicks(reissue_wakeup_latency)); } } else { @@ -846,9 +850,10 @@ // Set a wakeup timer if (dynamic_timeout_enabled) { - reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4); + reissueTimerTable.set( + address, cyclesToTicks(averageLatencyEstimate())); } else { - reissueTimerTable.set(address, fixed_timeout_latency); + reissueTimerTable.set(address, cyclesToTicks(fixed_timeout_latency)); } } @@ -913,7 +918,7 @@ // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, reissue_wakeup_latency); + reissueTimerTable.set(address, cyclesToTicks(reissue_wakeup_latency)); } } else { @@ -970,9 +975,10 @@ // Set a wakeup timer if (dynamic_timeout_enabled) { - reissueTimerTable.set(address, (5 * averageLatencyEstimate()) / 4); + reissueTimerTable.set( + address, cyclesToTicks(averageLatencyEstimate())); } else { - reissueTimerTable.set(address, fixed_timeout_latency); + reissueTimerTable.set(address, cyclesToTicks(fixed_timeout_latency)); } } } @@ -1375,23 +1381,23 @@ } action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(l_popPersistentQueue, "l", desc="Pop persistent queue.") { - persistentNetwork_in.dequeue(); + persistentNetwork_in.dequeue(clockEdge()); } action(m_popRequestQueue, "m", desc="Pop request queue.") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseNetwork_in.dequeue(); + responseNetwork_in.dequeue(clockEdge()); } action(o_scheduleUseTimeout, "o", desc="Schedule a use timeout.") { - useTimerTable.set(address, use_timeout_latency); + useTimerTable.set(address, cyclesToTicks(use_timeout_latency)); } action(p_informL2AboutTokenLoss, "p", desc="Inform L2 about loss of all tokens") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_token-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -149,6 +149,7 @@ PersistentTable persistentTable; PerfectCacheMemory localDirectory, template=""; + Tick clockEdge(); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); @@ -315,7 +316,7 @@ // Persistent Network in_port(persistentNetwork_in, PersistentMsg, persistentToL2Cache) { - if (persistentNetwork_in.isReady()) { + if (persistentNetwork_in.isReady(clockEdge())) { peek(persistentNetwork_in, PersistentMsg) { assert(in_msg.Destination.isElement(machineID)); @@ -355,7 +356,7 @@ // Request Network in_port(requestNetwork_in, RequestMsg, GlobalRequestToL2Cache) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); @@ -378,7 +379,7 @@ } in_port(L1requestNetwork_in, RequestMsg, L1RequestToL2Cache) { - if (L1requestNetwork_in.isReady()) { + if (L1requestNetwork_in.isReady(clockEdge())) { peek(L1requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.addr); @@ -402,7 +403,7 @@ // Response Network in_port(responseNetwork_in, ResponseMsg, responseToL2Cache) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); Entry cache_entry := getCacheEntry(in_msg.addr); @@ -859,19 +860,19 @@ } action(l_popPersistentQueue, "l", desc="Pop persistent queue.") { - persistentNetwork_in.dequeue(); + persistentNetwork_in.dequeue(clockEdge()); } action(m_popRequestQueue, "m", desc="Pop request queue.") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseNetwork_in.dequeue(); + responseNetwork_in.dequeue(clockEdge()); } action(o_popL1RequestQueue, "o", desc="Pop L1 request queue.") { - L1requestNetwork_in.dequeue(); + L1requestNetwork_in.dequeue(clockEdge()); } diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_token-dir.sm --- a/src/mem/protocol/MOESI_CMP_token-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -34,6 +34,7 @@ Cycles fixed_timeout_latency := 100; Cycles reissue_wakeup_latency := 10; Cycles to_memory_controller_latency := 1; + Cycles recycle_latency := 10; // Message Queues from dir to other controllers / network MessageBuffer * dmaResponseFromDir, network="To", virtual_network="5", @@ -171,6 +172,8 @@ bool starving, default="false"; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; + Tick clockEdge(); + Tick cyclesToTicks(Cycles c); void set_tbe(TBE b); void unset_tbe(); @@ -275,7 +278,7 @@ // ** IN_PORTS ** // off-chip memory request/response is done in_port(memQueue_in, MemoryMsg, responseFromMemory) { - if (memQueue_in.isReady()) { + if (memQueue_in.isReady(clockEdge())) { peek(memQueue_in, MemoryMsg) { if (in_msg.Type == MemoryRequestType:MEMORY_READ) { trigger(Event:Memory_Data, in_msg.addr, TBEs.lookup(in_msg.addr)); @@ -291,14 +294,15 @@ // Reissue Timer in_port(reissueTimerTable_in, Addr, reissueTimerTable) { - if (reissueTimerTable_in.isReady()) { - trigger(Event:Request_Timeout, reissueTimerTable.readyAddress(), - TBEs.lookup(reissueTimerTable.readyAddress())); + Tick current_time := clockEdge(); + if (reissueTimerTable_in.isReady(current_time)) { + Addr addr := reissueTimerTable.nextAddress(); + trigger(Event:Request_Timeout, addr, TBEs.lookup(addr)); } } in_port(responseNetwork_in, ResponseMsg, responseToDir) { - if (responseNetwork_in.isReady()) { + if (responseNetwork_in.isReady(clockEdge())) { peek(responseNetwork_in, ResponseMsg) { assert(in_msg.Destination.isElement(machineID)); if (getDirectoryEntry(in_msg.addr).Tokens + in_msg.Tokens == max_tokens()) { @@ -337,7 +341,7 @@ } in_port(persistentNetwork_in, PersistentMsg, persistentToDir) { - if (persistentNetwork_in.isReady()) { + if (persistentNetwork_in.isReady(clockEdge())) { peek(persistentNetwork_in, PersistentMsg) { assert(in_msg.Destination.isElement(machineID)); @@ -399,7 +403,7 @@ } in_port(requestNetwork_in, RequestMsg, requestToDir) { - if (requestNetwork_in.isReady()) { + if (requestNetwork_in.isReady(clockEdge())) { peek(requestNetwork_in, RequestMsg) { assert(in_msg.Destination.isElement(machineID)); if (in_msg.Type == CoherenceRequestType:GETS) { @@ -414,7 +418,7 @@ } in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir) { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, DMARequestMsg) { if (in_msg.Type == DMARequestType:READ) { trigger(Event:DMA_READ, in_msg.LineAddress, TBEs.lookup(in_msg.LineAddress)); @@ -489,7 +493,7 @@ // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, reissue_wakeup_latency); + reissueTimerTable.set(address, cyclesToTicks(reissue_wakeup_latency)); } } @@ -557,7 +561,7 @@ // IssueCount. // Set a wakeup timer - reissueTimerTable.set(address, reissue_wakeup_latency); + reissueTimerTable.set(address, cyclesToTicks(reissue_wakeup_latency)); } } @@ -751,35 +755,35 @@ } action(j_popIncomingRequestQueue, "j", desc="Pop incoming request queue") { - requestNetwork_in.dequeue(); + requestNetwork_in.dequeue(clockEdge()); } action(z_recycleRequest, "z", desc="Recycle the request queue") { - requestNetwork_in.recycle(); + requestNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(k_popIncomingResponseQueue, "k", desc="Pop incoming response queue") { - responseNetwork_in.dequeue(); + responseNetwork_in.dequeue(clockEdge()); } action(kz_recycleResponse, "kz", desc="Recycle incoming response queue") { - responseNetwork_in.recycle(); + responseNetwork_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(l_popIncomingPersistentQueue, "l", desc="Pop incoming persistent queue") { - persistentNetwork_in.dequeue(); + persistentNetwork_in.dequeue(clockEdge()); } action(p_popDmaRequestQueue, "pd", desc="pop dma request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(y_recycleDmaRequestQueue, "y", desc="recycle dma request queue") { - dmaRequestQueue_in.recycle(); + dmaRequestQueue_in.recycle(clockEdge(), cyclesToTicks(recycle_latency)); } action(l_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); + memQueue_in.dequeue(clockEdge()); } action(r_bounceResponse, "r", desc="Bounce response to starving processor") { @@ -803,7 +807,7 @@ // if (reissueTimerTable.isSet(address)) { reissueTimerTable.unset(address); - reissueTimerTable.set(address, fixed_timeout_latency); + reissueTimerTable.set(address, cyclesToTicks(fixed_timeout_latency)); } } @@ -811,7 +815,7 @@ // // currently only support a fixed timeout latency // - reissueTimerTable.set(address, fixed_timeout_latency); + reissueTimerTable.set(address, cyclesToTicks(fixed_timeout_latency)); } action(ut_unsetReissueTimer, "ut", desc="Unset reissue timer.") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_CMP_token-dma.sm --- a/src/mem/protocol/MOESI_CMP_token-dma.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Tue Jul 21 10:26:32 2015 -0500 @@ -54,6 +54,8 @@ MessageBuffer mandatoryQueue, ordered="false"; State cur_state; + Tick clockEdge(); + State getState(Addr addr) { return cur_state; } @@ -79,7 +81,7 @@ out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress); @@ -93,7 +95,7 @@ } in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") { - if (dmaResponseQueue_in.isReady()) { + if (dmaResponseQueue_in.isReady(clockEdge())) { peek( dmaResponseQueue_in, DMAResponseMsg) { if (in_msg.Type == DMAResponseType:ACK) { trigger(Event:Ack, in_msg.LineAddress); @@ -149,11 +151,11 @@ } action(p_popRequestQueue, "p", desc="Pop request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(p_popResponseQueue, "\p", desc="Pop request queue") { - dmaResponseQueue_in.dequeue(); + dmaResponseQueue_in.dequeue(clockEdge()); } transition(READY, ReadRequest, BUSY_RD) { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -182,6 +182,7 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; + Tick clockEdge(); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE b); @@ -333,7 +334,7 @@ // Trigger Queue in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=3) { - if (triggerQueue_in.isReady()) { + if (triggerQueue_in.isReady(clockEdge())) { peek(triggerQueue_in, TriggerMsg) { Entry cache_entry := getCacheEntry(in_msg.addr); @@ -356,7 +357,7 @@ // Response Network in_port(responseToCache_in, ResponseMsg, responseToCache, rank=2) { - if (responseToCache_in.isReady()) { + if (responseToCache_in.isReady(clockEdge())) { peek(responseToCache_in, ResponseMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); @@ -381,7 +382,7 @@ // Forward Network in_port(forwardToCache_in, RequestMsg, forwardToCache, rank=1) { - if (forwardToCache_in.isReady()) { + if (forwardToCache_in.isReady(clockEdge())) { peek(forwardToCache_in, RequestMsg, block_on="addr") { Entry cache_entry := getCacheEntry(in_msg.addr); @@ -425,7 +426,7 @@ // Mandatory Queue in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...", rank=0) { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest, block_on="LineAddress") { // Check for data access to blocks in I-cache and ifetchs to blocks in D-cache @@ -941,15 +942,15 @@ } action(j_popTriggerQueue, "j", desc="Pop trigger queue.") { - triggerQueue_in.dequeue(); + triggerQueue_in.dequeue(clockEdge()); } action(k_popMandatoryQueue, "k", desc="Pop mandatory queue.") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(l_popForwardQueue, "l", desc="Pop forwareded request queue.") { - forwardToCache_in.dequeue(); + forwardToCache_in.dequeue(clockEdge()); } action(hp_copyFromTBEToL2, "li", desc="Copy data from TBE to L2 cache entry.") { @@ -1008,7 +1009,7 @@ } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseToCache_in.dequeue(); + responseToCache_in.dequeue(clockEdge()); } action(ll_L2toL1Transfer, "ll", desc="") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_hammer-dir.sm --- a/src/mem/protocol/MOESI_hammer-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -181,6 +181,7 @@ bool isPresent(Addr); } + Tick clockEdge(); void set_cache_entry(AbstractCacheEntry b); void unset_cache_entry(); void set_tbe(TBE a); @@ -313,7 +314,7 @@ // Trigger Queue in_port(triggerQueue_in, TriggerMsg, triggerQueue, rank=5) { - if (triggerQueue_in.isReady()) { + if (triggerQueue_in.isReady(clockEdge())) { peek(triggerQueue_in, TriggerMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -337,7 +338,7 @@ } in_port(unblockNetwork_in, ResponseMsg, unblockToDir, rank=4) { - if (unblockNetwork_in.isReady()) { + if (unblockNetwork_in.isReady(clockEdge())) { peek(unblockNetwork_in, ResponseMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -366,7 +367,7 @@ // Response Network in_port(responseToDir_in, ResponseMsg, responseToDir, rank=3) { - if (responseToDir_in.isReady()) { + if (responseToDir_in.isReady(clockEdge())) { peek(responseToDir_in, ResponseMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -389,7 +390,7 @@ // off-chip memory request/response is done in_port(memQueue_in, MemoryMsg, responseFromMemory, rank=2) { - if (memQueue_in.isReady()) { + if (memQueue_in.isReady(clockEdge())) { peek(memQueue_in, MemoryMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -406,7 +407,7 @@ } in_port(requestQueue_in, RequestMsg, requestToDir, rank=1) { - if (requestQueue_in.isReady()) { + if (requestQueue_in.isReady(clockEdge())) { peek(requestQueue_in, RequestMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.addr); TBE tbe := TBEs.lookup(in_msg.addr); @@ -440,7 +441,7 @@ } in_port(dmaRequestQueue_in, DMARequestMsg, dmaRequestToDir, rank=0) { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, DMARequestMsg) { PfEntry pf_entry := getProbeFilterEntry(in_msg.LineAddress); TBE tbe := TBEs.lookup(in_msg.LineAddress); @@ -681,7 +682,7 @@ } action(n_popResponseQueue, "n", desc="Pop response queue") { - responseToDir_in.dequeue(); + responseToDir_in.dequeue(clockEdge()); } action(o_checkForCompletion, "o", desc="Check if we have received all the messages required for completion") { @@ -1114,14 +1115,14 @@ } action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") { - requestQueue_in.dequeue(); + requestQueue_in.dequeue(clockEdge()); } action(j_popIncomingUnblockQueue, "j", desc="Pop incoming unblock queue") { peek(unblockNetwork_in, ResponseMsg) { APPEND_TRANSITION_COMMENT(in_msg.Sender); } - unblockNetwork_in.dequeue(); + unblockNetwork_in.dequeue(clockEdge()); } action(k_wakeUpDependents, "k", desc="wake-up dependents") { @@ -1129,15 +1130,15 @@ } action(l_popMemQueue, "q", desc="Pop off-chip request queue") { - memQueue_in.dequeue(); + memQueue_in.dequeue(clockEdge()); } action(g_popTriggerQueue, "g", desc="Pop trigger queue") { - triggerQueue_in.dequeue(); + triggerQueue_in.dequeue(clockEdge()); } action(p_popDmaRequestQueue, "pd", desc="pop dma request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(zd_stallAndWaitDMARequest, "zd", desc="Stall and wait the dma request queue") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/MOESI_hammer-dma.sm --- a/src/mem/protocol/MOESI_hammer-dma.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-dma.sm Tue Jul 21 10:26:32 2015 -0500 @@ -52,6 +52,8 @@ MessageBuffer mandatoryQueue, ordered="false"; State cur_state; + Tick clockEdge(); + State getState(Addr addr) { return cur_state; } @@ -77,7 +79,7 @@ out_port(requestToDir_out, DMARequestMsg, requestToDir, desc="..."); in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") { - if (dmaRequestQueue_in.isReady()) { + if (dmaRequestQueue_in.isReady(clockEdge())) { peek(dmaRequestQueue_in, SequencerMsg) { if (in_msg.Type == SequencerRequestType:LD ) { trigger(Event:ReadRequest, in_msg.LineAddress); @@ -91,7 +93,7 @@ } in_port(dmaResponseQueue_in, DMAResponseMsg, responseFromDir, desc="...") { - if (dmaResponseQueue_in.isReady()) { + if (dmaResponseQueue_in.isReady(clockEdge())) { peek( dmaResponseQueue_in, DMAResponseMsg) { if (in_msg.Type == DMAResponseType:ACK) { trigger(Event:Ack, in_msg.LineAddress); @@ -147,11 +149,11 @@ } action(p_popRequestQueue, "p", desc="Pop request queue") { - dmaRequestQueue_in.dequeue(); + dmaRequestQueue_in.dequeue(clockEdge()); } action(p_popResponseQueue, "\p", desc="Pop request queue") { - dmaResponseQueue_in.dequeue(); + dmaResponseQueue_in.dequeue(clockEdge()); } transition(READY, ReadRequest, BUSY_RD) { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/Network_test-cache.sm --- a/src/mem/protocol/Network_test-cache.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/Network_test-cache.sm Tue Jul 21 10:26:32 2015 -0500 @@ -69,6 +69,7 @@ } // FUNCTIONS + Tick clockEdge(); // cpu/testers/networktest/networktest.cc generates packets of the type // ReadReq, INST_FETCH, and WriteReq. @@ -130,7 +131,7 @@ // Mandatory Queue in_port(mandatoryQueue_in, RubyRequest, mandatoryQueue, desc="...") { - if (mandatoryQueue_in.isReady()) { + if (mandatoryQueue_in.isReady(clockEdge())) { peek(mandatoryQueue_in, RubyRequest) { trigger(mandatory_request_type_to_event(in_msg.Type), in_msg.LineAddress, getCacheEntry(in_msg.LineAddress)); @@ -175,7 +176,7 @@ } action(m_popMandatoryQueue, "m", desc="Pop the mandatory request queue") { - mandatoryQueue_in.dequeue(); + mandatoryQueue_in.dequeue(clockEdge()); } action(r_load_hit, "r", desc="Notify sequencer the load completed.") { diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/Network_test-dir.sm --- a/src/mem/protocol/Network_test-dir.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/Network_test-dir.sm Tue Jul 21 10:26:32 2015 -0500 @@ -60,7 +60,9 @@ DataBlock DataBlk, desc="data for the block"; } - // ** OBJECTS ** + // ** FUNCTIONS ** + Tick clockEdge(); + State getState(Addr addr) { return State:I; } @@ -87,7 +89,7 @@ // ** IN_PORTS ** in_port(requestQueue_in, RequestMsg, requestToDir) { - if (requestQueue_in.isReady()) { + if (requestQueue_in.isReady(clockEdge())) { peek(requestQueue_in, RequestMsg) { if (in_msg.Type == CoherenceRequestType:MSG) { trigger(Event:Receive_Request, in_msg.addr); @@ -98,7 +100,7 @@ } } in_port(forwardQueue_in, RequestMsg, forwardToDir) { - if (forwardQueue_in.isReady()) { + if (forwardQueue_in.isReady(clockEdge())) { peek(forwardQueue_in, RequestMsg) { if (in_msg.Type == CoherenceRequestType:MSG) { trigger(Event:Receive_Forward, in_msg.addr); @@ -109,7 +111,7 @@ } } in_port(responseQueue_in, RequestMsg, responseToDir) { - if (responseQueue_in.isReady()) { + if (responseQueue_in.isReady(clockEdge())) { peek(responseQueue_in, RequestMsg) { if (in_msg.Type == CoherenceRequestType:MSG) { trigger(Event:Receive_Response, in_msg.addr); @@ -123,15 +125,15 @@ // Actions action(i_popIncomingRequestQueue, "i", desc="Pop incoming request queue") { - requestQueue_in.dequeue(); + requestQueue_in.dequeue(clockEdge()); } action(f_popIncomingForwardQueue, "f", desc="Pop incoming forward queue") { - forwardQueue_in.dequeue(); + forwardQueue_in.dequeue(clockEdge()); } action(r_popIncomingResponseQueue, "r", desc="Pop incoming response queue") { - responseQueue_in.dequeue(); + responseQueue_in.dequeue(clockEdge()); } // TRANSITIONS diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/RubySlicc_Exports.sm --- a/src/mem/protocol/RubySlicc_Exports.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/RubySlicc_Exports.sm Tue Jul 21 10:26:32 2015 -0500 @@ -37,6 +37,7 @@ external_type(Packet, primitive="yes"); external_type(Addr, primitive="yes"); external_type(Cycles, primitive="yes", default="Cycles(0)"); +external_type(Tick, primitive="yes", default="0"); structure(DataBlock, external = "yes", desc="..."){ void clear(); diff -r c07e8733dc6a -r f66800e62c22 src/mem/protocol/RubySlicc_Types.sm --- a/src/mem/protocol/RubySlicc_Types.sm Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/protocol/RubySlicc_Types.sm Tue Jul 21 10:26:32 2015 -0500 @@ -40,9 +40,9 @@ external_type(Scalar, primitive="yes"); structure(InPort, external = "yes", primitive="yes") { - bool isReady(); - Cycles dequeue(); - void recycle(); + bool isReady(Tick current_time); + Tick dequeue(Tick current_time); + void recycle(Tick current_time, Tick recycle_latency); bool isEmpty(); } @@ -169,9 +169,9 @@ } structure (TimerTable, inport="yes", external = "yes") { - bool isReady(); - Addr readyAddress(); - void set(Addr, Cycles); + bool isReady(Tick); + Addr nextAddress(); + void set(Addr, Tick); void unset(Addr); bool isSet(Addr); } diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/MessageBuffer.hh --- a/src/mem/ruby/network/MessageBuffer.hh Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/MessageBuffer.hh Tue Jul 21 10:26:32 2015 -0500 @@ -50,30 +50,27 @@ { public: MessageBuffer(const std::string &name = ""); - std::string name() const { return m_name; } - void setRecycleLatency(Cycles recycle_latency) - { m_recycle_latency = recycle_latency; } - - void reanalyzeMessages(Addr addr); - void reanalyzeAllMessages(); - void stallMessage(Addr addr); + void reanalyzeMessages(Addr addr, Tick current_time, + Tick reanalyze_latency); + void reanalyzeAllMessages(Tick current_time, Tick reanalyze_latency); + void stallMessage(Addr addr, Tick current_time); // TRUE if head of queue timestamp <= SystemTime - bool isReady() const; + bool isReady(Tick current_time) const; void - delayHead() + delayHead(Tick current_time, Tick delta) { MsgPtr m = m_prio_heap.front(); std::pop_heap(m_prio_heap.begin(), m_prio_heap.end(), std::greater()); m_prio_heap.pop_back(); - enqueue(m, Cycles(1)); + enqueue(m, current_time, delta); } - bool areNSlotsAvailable(unsigned int n); + bool areNSlotsAvailable(unsigned int n, Tick curTick); int getPriority() { return m_priority_rank; } void setPriority(int rank) { m_priority_rank = rank; } void setConsumer(Consumer* consumer) @@ -86,18 +83,6 @@ m_consumer = consumer; } - void setSender(ClockedObject* obj) - { - assert(m_sender == NULL || m_sender == obj); - m_sender = obj; - } - - void setReceiver(ClockedObject* obj) - { - assert(m_receiver == NULL || m_receiver == obj); - m_receiver = obj; - } - void setDescription(const std::string& name) { m_name = name; } std::string getDescription() { return m_name;} @@ -114,14 +99,13 @@ return m_prio_heap.front(); } - void enqueue(MsgPtr message) { enqueue(message, Cycles(1)); } - void enqueue(MsgPtr message, Cycles delta); + void enqueue(MsgPtr message, Tick curTick, Tick delta); //! Updates the delay cycles of the message at the head of the queue, //! removes it from the queue and returns its total delay. - Cycles dequeue(); + Tick dequeue(Tick current_time); - void recycle(); + void recycle(Tick current_time, Tick recycle_latency); bool isEmpty() const { return m_prio_heap.size() == 0; } void @@ -132,7 +116,7 @@ } void resize(unsigned int size) { m_max_size = size; } - unsigned int getSize(); + unsigned int getSize(Tick curTick); void setRandomization(bool random_flag) { m_randomization = random_flag; } void clear(); @@ -152,14 +136,7 @@ void reanalyzeList(std::list &, Tick); private: - //added by SS - Cycles m_recycle_latency; - // Data Members (m_ prefix) - //! The two ends of the buffer. - ClockedObject* m_sender; - ClockedObject* m_receiver; - //! Consumer to signal a wakeup(), can be NULL Consumer* m_consumer; std::vector m_prio_heap; @@ -172,12 +149,12 @@ std::string m_name; unsigned int m_max_size; - Cycles m_time_last_time_size_checked; + Tick m_time_last_time_size_checked; unsigned int m_size_last_time_size_checked; // variables used so enqueues appear to happen immediately, while // pop happen the next cycle - Cycles m_time_last_time_enqueue; + Tick m_time_last_time_enqueue; Tick m_time_last_time_pop; Tick m_last_arrival_time; @@ -196,7 +173,7 @@ int m_vnet_id; }; -Cycles random_time(); +Tick random_time(); inline std::ostream& operator<<(std::ostream& out, const MessageBuffer& obj) diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/MessageBuffer.cc --- a/src/mem/ruby/network/MessageBuffer.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/MessageBuffer.cc Tue Jul 21 10:26:32 2015 -0500 @@ -45,9 +45,6 @@ { m_msg_counter = 0; m_consumer = NULL; - m_sender = NULL; - m_receiver = NULL; - m_ordering_set = false; m_strict_fifo = true; m_max_size = 0; @@ -65,10 +62,10 @@ } unsigned int -MessageBuffer::getSize() +MessageBuffer::getSize(Tick curTick) { - if (m_time_last_time_size_checked != m_receiver->curCycle()) { - m_time_last_time_size_checked = m_receiver->curCycle(); + if (m_time_last_time_size_checked != curTick) { + m_time_last_time_size_checked = curTick; m_size_last_time_size_checked = m_prio_heap.size(); } @@ -76,7 +73,7 @@ } bool -MessageBuffer::areNSlotsAvailable(unsigned int n) +MessageBuffer::areNSlotsAvailable(unsigned int n, Tick curTick) { // fast path when message buffers have infinite size @@ -90,11 +87,11 @@ // size immediately unsigned int current_size = 0; - if (m_time_last_time_pop < m_sender->clockEdge()) { + if (m_time_last_time_pop < curTick) { // no pops this cycle - heap size is correct current_size = m_prio_heap.size(); } else { - if (m_time_last_time_enqueue < m_sender->curCycle()) { + if (m_time_last_time_enqueue < curTick) { // no enqueues this cycle - m_size_at_cycle_start is correct current_size = m_size_at_cycle_start; } else { @@ -130,26 +127,26 @@ } // FIXME - move me somewhere else -Cycles +Tick random_time() { - Cycles time(1); - time += Cycles(random_mt.random(0, 3)); // [0...3] + Tick time = 1; + time += random_mt.random(0, 3); // [0...3] if (random_mt.random(0, 7) == 0) { // 1 in 8 chance - time += Cycles(100 + random_mt.random(1, 15)); // 100 + [1...15] + time += 100 + random_mt.random(1, 15); // 100 + [1...15] } return time; } void -MessageBuffer::enqueue(MsgPtr message, Cycles delta) +MessageBuffer::enqueue(MsgPtr message, Tick current_time, Tick delta) { assert(m_ordering_set); // record current time incase we have a pop that also adjusts my size - if (m_time_last_time_enqueue < m_sender->curCycle()) { + if (m_time_last_time_enqueue < current_time) { m_msgs_this_cycle = 0; // first msg this cycle - m_time_last_time_enqueue = m_sender->curCycle(); + m_time_last_time_enqueue = current_time; } m_msg_counter++; @@ -158,23 +155,20 @@ // Calculate the arrival time of the message, that is, the first // cycle the message can be dequeued. assert(delta > 0); - Tick current_time = m_sender->clockEdge(); Tick arrival_time = 0; if (!RubySystem::getRandomization() || !m_randomization) { // No randomization - arrival_time = current_time + delta * m_sender->clockPeriod(); + arrival_time = current_time + delta; } else { // Randomization - ignore delta if (m_strict_fifo) { if (m_last_arrival_time < current_time) { m_last_arrival_time = current_time; } - arrival_time = m_last_arrival_time + - random_time() * m_sender->clockPeriod(); + arrival_time = m_last_arrival_time + random_time(); } else { - arrival_time = current_time + - random_time() * m_sender->clockPeriod(); + arrival_time = current_time + random_time(); } } @@ -184,9 +178,8 @@ if (arrival_time < m_last_arrival_time) { panic("FIFO ordering violated: %s name: %s current time: %d " "delta: %d arrival_time: %d last arrival_time: %d\n", - *this, m_name, current_time, - delta * m_sender->clockPeriod(), - arrival_time, m_last_arrival_time); + *this, m_name, current_time, delta, arrival_time, + m_last_arrival_time); } } @@ -199,10 +192,10 @@ Message* msg_ptr = message.get(); assert(msg_ptr != NULL); - assert(m_sender->clockEdge() >= msg_ptr->getLastEnqueueTime() && + assert(current_time >= msg_ptr->getLastEnqueueTime() && "ensure we aren't dequeued early"); - msg_ptr->updateDelayedTicks(m_sender->clockEdge()); + msg_ptr->updateDelayedTicks(current_time); msg_ptr->setLastEnqueueTime(arrival_time); msg_ptr->setMsgCounter(m_msg_counter); @@ -219,8 +212,8 @@ m_consumer->storeEventInfo(m_vnet_id); } -Cycles -MessageBuffer::dequeue() +Tick +MessageBuffer::dequeue(Tick current_time) { DPRINTF(RubyQueue, "Popping\n"); assert(isReady()); @@ -229,22 +222,20 @@ MsgPtr message = m_prio_heap.front(); // get the delay cycles - message->updateDelayedTicks(m_receiver->clockEdge()); - Cycles delayCycles = - m_receiver->ticksToCycles(message->getDelayedTicks()); + message->updateDelayedTicks(current_time); + Tick delay = message->getDelayedTicks(); // record previous size and time so the current buffer size isn't // adjusted until next cycle - if (m_time_last_time_pop < m_receiver->clockEdge()) { + if (m_time_last_time_pop < current_time) { m_size_at_cycle_start = m_prio_heap.size(); - m_time_last_time_pop = m_receiver->clockEdge(); + m_time_last_time_pop = current_time; } - pop_heap(m_prio_heap.begin(), m_prio_heap.end(), - greater()); + pop_heap(m_prio_heap.begin(), m_prio_heap.end(), greater()); m_prio_heap.pop_back(); - return delayCycles; + return delay; } void @@ -253,25 +244,26 @@ m_prio_heap.clear(); m_msg_counter = 0; - m_time_last_time_enqueue = Cycles(0); + m_time_last_time_enqueue = 0; m_time_last_time_pop = 0; m_size_at_cycle_start = 0; m_msgs_this_cycle = 0; } void -MessageBuffer::recycle() +MessageBuffer::recycle(Tick current_time, Tick recycle_latency) { DPRINTF(RubyQueue, "Recycling.\n"); assert(isReady()); MsgPtr node = m_prio_heap.front(); pop_heap(m_prio_heap.begin(), m_prio_heap.end(), greater()); - node->setLastEnqueueTime(m_receiver->clockEdge(m_recycle_latency)); + Tick future_time = current_time + recycle_latency; + node->setLastEnqueueTime(future_time); + m_prio_heap.back() = node; push_heap(m_prio_heap.begin(), m_prio_heap.end(), greater()); - m_consumer-> - scheduleEventAbsolute(m_receiver->clockEdge(m_recycle_latency)); + m_consumer->scheduleEventAbsolute(future_time); } void @@ -293,11 +285,12 @@ } void -MessageBuffer::reanalyzeMessages(Addr addr) +MessageBuffer::reanalyzeMessages(Addr addr, Tick current_time, + Tick reanalyze_latency) { DPRINTF(RubyQueue, "ReanalyzeMessages\n"); assert(m_stall_msg_map.count(addr) > 0); - Tick nextTick = m_receiver->clockEdge(Cycles(1)); + Tick nextTick = current_time + reanalyze_latency; // // Put all stalled messages associated with this address back on the @@ -308,10 +301,10 @@ } void -MessageBuffer::reanalyzeAllMessages() +MessageBuffer::reanalyzeAllMessages(Tick current_time, Tick reanalyze_latency) { DPRINTF(RubyQueue, "ReanalyzeAllMessages\n"); - Tick nextTick = m_receiver->clockEdge(Cycles(1)); + Tick nextTick = current_time + reanalyze_latency; // // Put all stalled messages associated with this address back on the @@ -325,14 +318,14 @@ } void -MessageBuffer::stallMessage(Addr addr) +MessageBuffer::stallMessage(Addr addr, Tick current_time) { DPRINTF(RubyQueue, "Stalling due to %s\n", addr); assert(isReady()); assert(getOffset(addr) == 0); MsgPtr message = m_prio_heap.front(); - dequeue(); + dequeue(current_time); // // Note: no event is scheduled to analyze the map at a later time. @@ -356,10 +349,10 @@ } bool -MessageBuffer::isReady() const +MessageBuffer::isReady(Tick current_time) const { return ((m_prio_heap.size() > 0) && - (m_prio_heap.front()->getLastEnqueueTime() <= m_receiver->clockEdge())); + (m_prio_heap.front()->getLastEnqueueTime() <= current_time)); } uint32_t diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc --- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc Tue Jul 21 10:26:32 2015 -0500 @@ -115,13 +115,6 @@ for (auto& it : in) { if (it != nullptr) { it->setConsumer(this); - it->setReceiver(this); - } - } - - for (auto& it : out) { - if (it != nullptr) { - it->setSender(this); } } } @@ -231,10 +224,10 @@ continue; } - while (b->isReady()) { // Is there a message waiting + while (b->isReady(clockEdge())) { // Is there a message waiting msg_ptr = b->peekMsgPtr(); if (flitisizeMessage(msg_ptr, vnet)) { - b->dequeue(); + b->dequeue(clockEdge()); } else { break; } @@ -253,7 +246,7 @@ free_signal = true; outNode_ptr[t_flit->get_vnet()]->enqueue( - t_flit->get_msg_ptr(), Cycles(1)); + t_flit->get_msg_ptr(), clockEdge(), cyclesToTicks(Cycles(1))); } // Simply send a credit back since we are not buffering // this flit in the NI @@ -363,7 +356,7 @@ continue; } - while (it->isReady()) { // Is there a message waiting + while (it->isReady(clockEdge())) { // Is there a message waiting scheduleEvent(Cycles(1)); return; } diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc --- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc Tue Jul 21 10:26:32 2015 -0500 @@ -99,13 +99,6 @@ for (auto& it: in) { if (it != nullptr) { it->setConsumer(this); - it->setReceiver(this); - } - } - - for (auto& it : out) { - if (it != nullptr) { - it->setSender(this); } } } @@ -250,10 +243,10 @@ continue; } - while (b->isReady()) { // Is there a message waiting + while (b->isReady(clockEdge())) { // Is there a message waiting msg_ptr = b->peekMsgPtr(); if (flitisizeMessage(msg_ptr, vnet)) { - b->dequeue(); + b->dequeue(clockEdge()); } else { break; } @@ -272,7 +265,7 @@ m_id, curCycle()); outNode_ptr[t_flit->get_vnet()]->enqueue( - t_flit->get_msg_ptr(), Cycles(1)); + t_flit->get_msg_ptr(), clockEdge(), cyclesToTicks(Cycles(1))); // signal the upstream router that this vc can be freed now inNetLink->release_vc_link(t_flit->get_vc(), @@ -334,7 +327,7 @@ continue; } - while (it->isReady()) { // Is there a message waiting + while (it->isReady(clockEdge())) { // Is there a message waiting scheduleEvent(Cycles(1)); return; } diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/simple/PerfectSwitch.cc --- a/src/mem/ruby/network/simple/PerfectSwitch.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/simple/PerfectSwitch.cc Tue Jul 21 10:26:32 2015 -0500 @@ -151,8 +151,9 @@ // temporary vectors to store the routing results vector output_links; vector output_link_destinations; + Tick current_time = m_switch->clockEdge(); - while (buffer->isReady()) { + while (buffer->isReady(current_time)) { DPRINTF(RubyNetwork, "incoming: %d\n", incoming); // Peek at message @@ -183,7 +184,7 @@ for (int out = 0; out < m_out.size(); out++) { int out_queue_length = 0; for (int v = 0; v < m_virtual_networks; v++) { - out_queue_length += m_out[out][v]->getSize(); + out_queue_length += m_out[out][v]->getSize(current_time); } int value = (out_queue_length << 8) | @@ -227,7 +228,7 @@ for (int i = 0; i < output_links.size(); i++) { int outgoing = output_links[i]; - if (!m_out[outgoing][vnet]->areNSlotsAvailable(1)) + if (!m_out[outgoing][vnet]->areNSlotsAvailable(1, current_time)) enough = false; DPRINTF(RubyNetwork, "Checking if node is blocked ..." @@ -258,7 +259,7 @@ } // Dequeue msg - buffer->dequeue(); + buffer->dequeue(current_time); m_pending_message_count[vnet]--; // Enqueue it - for all outgoing queues @@ -280,7 +281,8 @@ "inport[%d][%d] to outport [%d][%d].\n", incoming, vnet, outgoing, vnet); - m_out[outgoing][vnet]->enqueue(msg_ptr); + m_out[outgoing][vnet]->enqueue(msg_ptr, current_time, + m_switch->cyclesToTicks(Cycles(1))); } } } diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/simple/Switch.cc --- a/src/mem/ruby/network/simple/Switch.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/simple/Switch.cc Tue Jul 21 10:26:32 2015 -0500 @@ -67,12 +67,6 @@ Switch::addInPort(const vector& in) { m_perfect_switch->addInPort(in); - - for (auto& it : in) { - if (it != nullptr) { - it->setReceiver(this); - } - } } void @@ -93,10 +87,6 @@ vector intermediateBuffers; for (int i = 0; i < out.size(); ++i) { - if (out[i] != nullptr) { - out[i]->setSender(this); - } - MessageBuffer* buffer_ptr = new MessageBuffer; // Make these queues ordered buffer_ptr->setOrdering(true); @@ -106,9 +96,6 @@ intermediateBuffers.push_back(buffer_ptr); m_buffers_to_free.push_back(buffer_ptr); - - buffer_ptr->setSender(this); - buffer_ptr->setReceiver(this); } // Hook the queues to the PerfectSwitch diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/network/simple/Throttle.cc --- a/src/mem/ruby/network/simple/Throttle.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/network/simple/Throttle.cc Tue Jul 21 10:26:32 2015 -0500 @@ -31,6 +31,7 @@ #include "base/cast.hh" #include "base/cprintf.hh" #include "debug/RubyNetwork.hh" +#include "mem/ruby/network/simple/Switch.hh" #include "mem/ruby/network/simple/Throttle.hh" #include "mem/ruby/network/MessageBuffer.hh" #include "mem/ruby/network/Network.hh" @@ -94,14 +95,16 @@ if (out == nullptr || in == nullptr) { return; } + assert(m_units_remaining[vnet] >= 0); + Tick current_time = m_switch->clockEdge(); - while (bw_remaining > 0 && (in->isReady() || m_units_remaining[vnet] > 0) && - out->areNSlotsAvailable(1)) { - + while (bw_remaining > 0 && (in->isReady(current_time) || + m_units_remaining[vnet] > 0) && + out->areNSlotsAvailable(1, current_time)) { // See if we are done transferring the previous message on // this virtual network - if (m_units_remaining[vnet] == 0 && in->isReady()) { + if (m_units_remaining[vnet] == 0 && in->isReady(current_time)) { // Find the size of the message we are moving MsgPtr msg_ptr = in->peekMsgPtr(); Message *net_msg_ptr = msg_ptr.get(); @@ -114,8 +117,9 @@ m_ruby_system->curCycle()); // Move the message - in->dequeue(); - out->enqueue(msg_ptr, m_link_latency); + in->dequeue(current_time); + out->enqueue(msg_ptr, current_time, + m_switch->cyclesToTicks(m_link_latency)); // Count the message m_msg_counts[net_msg_ptr->getMessageSize()][vnet]++; @@ -128,8 +132,9 @@ bw_remaining = max(0, -diff); } - if (bw_remaining > 0 && (in->isReady() || m_units_remaining[vnet] > 0) && - !out->areNSlotsAvailable(1)) { + if (bw_remaining > 0 && (in->isReady(current_time) || + m_units_remaining[vnet] > 0) && + !out->areNSlotsAvailable(1, current_time)) { DPRINTF(RubyNetwork, "vnet: %d", vnet); // schedule me to wakeup again because I'm waiting for my diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/slicc_interface/AbstractController.hh --- a/src/mem/ruby/slicc_interface/AbstractController.hh Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/slicc_interface/AbstractController.hh Tue Jul 21 10:26:32 2015 -0500 @@ -151,6 +151,7 @@ int m_transitions_per_cycle; unsigned int m_buffer_size; Cycles m_recycle_latency; + Cycles m_reanalyze_latency; //! Counter for the number of cycles when the transitions carried out //! were equal to the maximum allowed diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/slicc_interface/AbstractController.cc --- a/src/mem/ruby/slicc_interface/AbstractController.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/slicc_interface/AbstractController.cc Tue Jul 21 10:26:32 2015 -0500 @@ -39,16 +39,11 @@ m_number_of_TBEs(p->number_of_TBEs), m_transitions_per_cycle(p->transitions_per_cycle), m_buffer_size(p->buffer_size), m_recycle_latency(p->recycle_latency), + m_reanalyze_latency(p->reanalyze_latency), memoryPort(csprintf("%s.memory", name()), this, ""), m_responseFromMemory_ptr(new MessageBuffer()) { - // Set the sender pointer of the response message buffer from the - // memory controller. - // This pointer is used for querying for the current time. - m_responseFromMemory_ptr->setSender(this); - m_responseFromMemory_ptr->setReceiver(this); m_responseFromMemory_ptr->setOrdering(false); - if (m_version == 0) { // Combine the statistics from all controllers // of this particular type. @@ -118,7 +113,8 @@ in_port_rank >= 0; in_port_rank--) { if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) { - (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr); + (*(m_waiting_buffers[addr]))[in_port_rank]-> + reanalyzeMessages(addr, clockEdge(), m_reanalyze_latency); } } delete m_waiting_buffers[addr]; @@ -138,7 +134,8 @@ in_port_rank >= 0; in_port_rank--) { if ((*(m_waiting_buffers[addr]))[in_port_rank] != NULL) { - (*(m_waiting_buffers[addr]))[in_port_rank]->reanalyzeMessages(addr); + (*(m_waiting_buffers[addr]))[in_port_rank]-> + reanalyzeMessages(addr, clockEdge(), m_reanalyze_latency); } } delete m_waiting_buffers[addr]; @@ -163,7 +160,8 @@ vec_iter != buf_iter->second->end(); ++vec_iter) { if (*vec_iter != NULL) { - (*vec_iter)->reanalyzeAllMessages(); + (*vec_iter)->reanalyzeAllMessages(clockEdge(), + m_reanalyze_latency); } } wokeUpMsgVecs.push_back(buf_iter->second); @@ -324,7 +322,8 @@ panic("Incorrect packet type received from memory controller!"); } - m_responseFromMemory_ptr->enqueue(msg); + m_responseFromMemory_ptr->enqueue(msg, clockEdge(), + cyclesToTicks(Cycles(1))); delete pkt; } diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/slicc_interface/Controller.py --- a/src/mem/ruby/slicc_interface/Controller.py Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/slicc_interface/Controller.py Tue Jul 21 10:26:32 2015 -0500 @@ -44,6 +44,8 @@ buffer_size = Param.UInt32(0, "max buffer size 0 means infinite") recycle_latency = Param.Cycles(10, "") + reanalyze_latency = Param.Cycles(1, "") + number_of_TBEs = Param.Int(256, "") ruby_system = Param.RubySystem("") diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/structures/TBETable.hh --- a/src/mem/ruby/structures/TBETable.hh Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/structures/TBETable.hh Tue Jul 21 10:26:32 2015 -0500 @@ -47,12 +47,12 @@ void allocate(Addr address); void deallocate(Addr address); bool - areNSlotsAvailable(int n) const + areNSlotsAvailable(int n, Tick current_time) const { return (m_number_of_TBEs - m_map.size()) >= n; } - ENTRY* lookup(Addr address); + ENTRY *lookup(Addr address); // Print cache contents void print(std::ostream& out) const; diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/structures/TimerTable.hh --- a/src/mem/ruby/structures/TimerTable.hh Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/structures/TimerTable.hh Tue Jul 21 10:26:32 2015 -0500 @@ -49,25 +49,16 @@ m_consumer_ptr = consumer_ptr; } - void setClockObj(ClockedObject* obj) - { - assert(m_clockobj_ptr == NULL); - m_clockobj_ptr = obj; - } - void setDescription(const std::string& name) { m_name = name; } - bool isReady() const; - Addr readyAddress() const; + bool isReady(Tick curTick) const; + Addr nextAddress() const; bool isSet(Addr address) const { return !!m_map.count(address); } - void set(Addr address, Cycles relative_latency); - void set(Addr address, uint64_t relative_latency) - { set(address, Cycles(relative_latency)); } - + void set(Addr address, Tick ready_time); void unset(Addr address); void print(std::ostream& out) const; @@ -82,14 +73,12 @@ // use a std::map for the address map as this container is sorted // and ensures a well-defined iteration order - typedef std::map AddressMap; + typedef std::map AddressMap; AddressMap m_map; mutable bool m_next_valid; - mutable Cycles m_next_time; // Only valid if m_next_valid is true + mutable Tick m_next_time; // Only valid if m_next_valid is true mutable Addr m_next_address; // Only valid if m_next_valid is true - //! Object used for querying time. - ClockedObject* m_clockobj_ptr; //! Consumer to signal a wakeup() Consumer* m_consumer_ptr; diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/structures/TimerTable.cc --- a/src/mem/ruby/structures/TimerTable.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/structures/TimerTable.cc Tue Jul 21 10:26:32 2015 -0500 @@ -33,14 +33,12 @@ : m_next_time(0) { m_consumer_ptr = NULL; - m_clockobj_ptr = NULL; - m_next_valid = false; m_next_address = 0; } bool -TimerTable::isReady() const +TimerTable::isReady(Tick curTick) const { if (m_map.empty()) return false; @@ -49,14 +47,12 @@ updateNext(); } assert(m_next_valid); - return (m_clockobj_ptr->curCycle() >= m_next_time); + return (curTick >= m_next_time); } Addr -TimerTable::readyAddress() const +TimerTable::nextAddress() const { - assert(isReady()); - if (!m_next_valid) { updateNext(); } @@ -65,17 +61,14 @@ } void -TimerTable::set(Addr address, Cycles relative_latency) +TimerTable::set(Addr address, Tick ready_time) { assert(address == makeLineAddress(address)); - assert(relative_latency > 0); assert(!m_map.count(address)); - Cycles ready_time = m_clockobj_ptr->curCycle() + relative_latency; m_map[address] = ready_time; assert(m_consumer_ptr != NULL); - m_consumer_ptr-> - scheduleEventAbsolute(m_clockobj_ptr->clockPeriod() * ready_time); + m_consumer_ptr->scheduleEventAbsolute(ready_time); m_next_valid = false; // Don't always recalculate the next ready address diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/system/DMASequencer.cc Tue Jul 21 10:26:32 2015 -0500 @@ -54,7 +54,6 @@ MemObject::init(); assert(m_controller != NULL); m_mandatory_q_ptr = m_controller->getMandatoryQueue(); - m_mandatory_q_ptr->setSender(this); m_is_busy = false; m_data_block_mask = ~ (~0 << RubySystem::getBlockSizeBits()); @@ -286,7 +285,7 @@ } assert(m_mandatory_q_ptr != NULL); - m_mandatory_q_ptr->enqueue(msg); + m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(Cycles(1))); active_request.bytes_issued += msg->getLen(); DPRINTF(RubyDma, "DMA request bytes issued %d, bytes completed %d, total len %d\n", diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/system/RubyPort.cc Tue Jul 21 10:26:32 2015 -0500 @@ -81,7 +81,6 @@ { assert(m_controller != NULL); m_mandatory_q_ptr = m_controller->getMandatoryQueue(); - m_mandatory_q_ptr->setSender(this); } BaseMasterPort & diff -r c07e8733dc6a -r f66800e62c22 src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/ruby/system/Sequencer.cc Tue Jul 21 10:26:32 2015 -0500 @@ -689,7 +689,7 @@ assert(latency > 0); assert(m_mandatory_q_ptr != NULL); - m_mandatory_q_ptr->enqueue(msg, latency); + m_mandatory_q_ptr->enqueue(msg, clockEdge(), cyclesToTicks(latency)); } template diff -r c07e8733dc6a -r f66800e62c22 src/mem/slicc/ast/EnqueueStatementAST.py --- a/src/mem/slicc/ast/EnqueueStatementAST.py Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/slicc/ast/EnqueueStatementAST.py Tue Jul 21 10:26:32 2015 -0500 @@ -64,9 +64,10 @@ if self.latexpr != None: ret_type, rcode = self.latexpr.inline(True) code("(${{self.queue_name.var.code}}).enqueue(" \ - "out_msg, Cycles($rcode));") + "out_msg, clockEdge(), cyclesToTicks(Cycles($rcode)));") else: - code("(${{self.queue_name.var.code}}).enqueue(out_msg);") + code("(${{self.queue_name.var.code}}).enqueue(out_msg, "\ + "clockEdge(), cyclesToTicks(Cycles(1)));") # End scope self.symtab.popFrame() diff -r c07e8733dc6a -r f66800e62c22 src/mem/slicc/ast/PeekStatementAST.py --- a/src/mem/slicc/ast/PeekStatementAST.py Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/slicc/ast/PeekStatementAST.py Tue Jul 21 10:26:32 2015 -0500 @@ -71,7 +71,7 @@ if (m_is_blocking && (m_block_map.count(in_msg_ptr->m_$address_field) == 1) && (m_block_map[in_msg_ptr->m_$address_field] != &$qcode)) { - $qcode.delayHead(); + $qcode.delayHead(clockEdge(), cyclesToTicks(Cycles(1))); continue; } ''') diff -r c07e8733dc6a -r f66800e62c22 src/mem/slicc/ast/StallAndWaitStatementAST.py --- a/src/mem/slicc/ast/StallAndWaitStatementAST.py Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py Tue Jul 21 10:26:32 2015 -0500 @@ -45,5 +45,5 @@ address_code = self.address.var.code code(''' stallBuffer(&($in_port_code), $address_code); - $in_port_code.stallMessage($address_code); + $in_port_code.stallMessage($address_code, clockEdge()); ''') diff -r c07e8733dc6a -r f66800e62c22 src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py Tue Jul 21 10:10:34 2015 -0500 +++ b/src/mem/slicc/symbols/StateMachine.py Tue Jul 21 10:26:32 2015 -0500 @@ -512,7 +512,6 @@ if var.ident.find("mandatoryQueue") >= 0: code(''' m_${{var.ident}}_ptr = new ${{var.type.c_ident}}(); -m_${{var.ident}}_ptr->setReceiver(this); ''') code(''' @@ -571,12 +570,6 @@ m_net_ptr->set${network}NetQueue(m_version + base, $ordered, $vnet, "$vnet_type", b); ''') - # Set the end - if network == "To": - code('$vid->setSender(this);') - else: - code('$vid->setReceiver(this);') - # Set ordering code('$vid->setOrdering(${{var["ordered"]}});') @@ -592,12 +585,6 @@ # Set buffer size code('$vid->resize(m_buffer_size);') - if "recycle_latency" in var: - code('$vid->setRecycleLatency( ' \ - 'Cycles(${{var["recycle_latency"]}}));') - else: - code('$vid->setRecycleLatency(m_recycle_latency);') - # set description (may be overriden later by port def) code(''' $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{var.ident}}]"); @@ -659,23 +646,6 @@ if vtype.isBuffer and "rank" in var: code('$vid->setPriority(${{var["rank"]}});') - # Set sender and receiver for trigger queue - if var.ident.find("triggerQueue") >= 0: - code('$vid->setSender(this);') - code('$vid->setReceiver(this);') - elif vtype.c_ident == "TimerTable": - code('$vid->setClockObj(this);') - elif var.ident.find("optionalQueue") >= 0: - code('$vid->setSender(this);') - code('$vid->setReceiver(this);') - - if vtype.isBuffer: - if "recycle_latency" in var: - code('$vid->setRecycleLatency( ' \ - 'Cycles(${{var["recycle_latency"]}}));') - else: - code('$vid->setRecycleLatency(m_recycle_latency);') - # Set the prefetchers code() for prefetcher in self.prefetchers: @@ -1264,7 +1234,7 @@ res = trans.resources for key,val in res.iteritems(): val = ''' -if (!%s.areNSlotsAvailable(%s)) +if (!%s.areNSlotsAvailable(%s, clockEdge())) return TransitionResult_ResourceStall; ''' % (key.code, val) case_sorter.append(val)