diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -327,6 +327,7 @@
     HCR hcr;
     uint32_t dacr;
     bool miscRegValid;
+    ContextID miscRegContext;
     ArmTranslationType curTranType;
 
     // Cached copies of system-level properties
# Node ID bb63caf9ccc100f91b2305f77cc4e5a22fe2b131
# Parent  c36d947bce2d63208bb8a5460b476a097c63dbfb
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -78,7 +78,7 @@
       stage2Mmu(NULL), rangeMRU(1),
       aarch64(false), aarch64EL(EL0), isPriv(false), isSecure(false),
       isHyp(false), asid(0), vmid(0), dacr(0),
-      miscRegValid(false), curTranType(NormalTran)
+      miscRegValid(false), miscRegContext(0), curTranType(NormalTran)
 {
     tableWalker->setTlb(this);
 
@@ -1214,7 +1214,8 @@
     // check if the regs have changed, or the translation mode is different.
     // NOTE: the tran type doesn't affect stage 2 TLB's as they only handle
     // one type of translation anyway
-    if (miscRegValid && ((tranType == curTranType) || isStage2)) {
+    if (miscRegValid && miscRegContext == tc->contextId() &&
+            ((tranType == curTranType) || isStage2)) {
         return;
     }
 
@@ -1310,6 +1311,7 @@
         }
     }
     miscRegValid = true;
+    miscRegContext = tc->contextId();
     curTranType  = tranType;
 }