diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MESI_Three_Level-L0cache.sm --- a/src/mem/protocol/MESI_Three_Level-L0cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -39,10 +39,10 @@ // To this node's L0 cache FROM the network MessageBuffer * bufferFromL1, network="From"; + + // Message queue between this controller and the processor + MessageBuffer * mandatoryQueue; { - // Message queue between this controller and the processor - MessageBuffer mandatoryQueue; - // STATES state_declaration(State, desc="Cache states", default="L0Cache_State_I") { // Base states diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MESI_Two_Level-L1cache.sm --- a/src/mem/protocol/MESI_Two_Level-L1cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -61,10 +61,13 @@ // a L2 bank -> this L1 MessageBuffer * responseToL1Cache, network="From", virtual_network="1", vnet_type="response"; + + // Request Buffer for prefetches + MessageBuffer * optionalQueue; + + // Buffer for requests generated by the processor core. + MessageBuffer * mandatoryQueue; { - // Request Buffer for prefetches - MessageBuffer optionalQueue; - // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { // Base states @@ -151,8 +154,6 @@ TBETable TBEs, template="", constructor="m_number_of_TBEs"; - MessageBuffer mandatoryQueue; - int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; Tick clockEdge(); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MESI_Two_Level-dir.sm --- a/src/mem/protocol/MESI_Two_Level-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -38,6 +38,8 @@ vnet_type="response"; MessageBuffer * responseFromDir, network="To", virtual_network="1", vnet_type="response"; + + MessageBuffer * responseFromMemory; { // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { @@ -185,8 +187,6 @@ (type == CoherenceRequestType:GETX); } - MessageBuffer responseFromMemory; - // ** OUT_PORTS ** out_port(responseNetwork_out, ResponseMsg, responseFromDir); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MESI_Two_Level-dma.sm --- a/src/mem/protocol/MESI_Two_Level-dma.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MESI_Two_Level-dma.sm Sun Aug 02 19:13:01 2015 -0500 @@ -35,6 +35,7 @@ vnet_type="response"; MessageBuffer * requestToDir, network="To", virtual_network="0", vnet_type="request"; + MessageBuffer * mandatoryQueue; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -49,7 +50,6 @@ Ack, desc="DMA write to memory completed"; } - MessageBuffer mandatoryQueue; State cur_state; Tick clockEdge(); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MI_example-cache.sm --- a/src/mem/protocol/MI_example-cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MI_example-cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -44,6 +44,8 @@ vnet_type="forward"; MessageBuffer * responseToCache, network="From", virtual_network="4", vnet_type="response"; + + MessageBuffer * mandatoryQueue; { // STATES state_declaration(State, desc="Cache states") { @@ -76,9 +78,6 @@ } // STRUCTURE DEFINITIONS - - MessageBuffer mandatoryQueue; - // CacheEntry structure(Entry, desc="...", interface="AbstractCacheEntry") { State CacheState, desc="cache state"; diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MI_example-dir.sm --- a/src/mem/protocol/MI_example-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MI_example-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -44,6 +44,7 @@ vnet_type="request"; MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", vnet_type="request"; + MessageBuffer * responseFromMemory; { // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { @@ -199,8 +200,6 @@ return num_functional_writes; } - MessageBuffer responseFromMemory; - // ** OUT_PORTS ** out_port(forwardNetwork_out, RequestMsg, forwardFromDir); out_port(responseNetwork_out, ResponseMsg, responseFromDir); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MI_example-dma.sm --- a/src/mem/protocol/MI_example-dma.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MI_example-dma.sm Sun Aug 02 19:13:01 2015 -0500 @@ -35,6 +35,7 @@ vnet_type="response"; MessageBuffer * requestToDir, network="To", virtual_network="0", vnet_type="request"; + MessageBuffer * mandatoryQueue; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -49,17 +50,16 @@ Ack, desc="DMA write to memory completed"; } - MessageBuffer mandatoryQueue; State cur_state; - Tick clockEdge(); Cycles ticksToCycles(Tick t); State getState(Addr addr) { return cur_state; } + void setState(Addr addr, State state) { - cur_state := state; + cur_state := state; } AccessPermission getAccessPermission(Addr addr) { diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_directory-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -52,6 +52,10 @@ // a L2 bank -> this L1 MessageBuffer * responseToL1Cache, network="From", virtual_network="2", vnet_type="response"; + + MessageBuffer * triggerQueue; + + MessageBuffer * mandatoryQueue; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -137,8 +141,6 @@ void set_tbe(TBE b); void unset_tbe(); - MessageBuffer mandatoryQueue, abstract_chip_ptr="true"; - TBETable TBEs, template="", constructor="m_number_of_TBEs"; TimerTable useTimerTable; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; @@ -257,8 +259,6 @@ } } - MessageBuffer triggerQueue; - // ** OUT_PORTS ** out_port(requestNetwork_out, RequestMsg, requestFromL1Cache); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_directory-L2cache.sm --- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -49,6 +49,7 @@ MessageBuffer * responseToL2Cache, network="From", virtual_network="2", vnet_type="response"; // a local L1 || mod-directory -> this L2 bank + MessageBuffer * triggerQueue; { // STATES state_declaration(State, desc="L2 Cache states", default="L2Cache_State_I") { @@ -547,8 +548,6 @@ return num_functional_writes; } - MessageBuffer triggerQueue; - out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache); out_port(localRequestNetwork_out, RequestMsg, L1RequestFromL2Cache); out_port(responseNetwork_out, ResponseMsg, responseFromL2Cache); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_directory-dir.sm --- a/src/mem/protocol/MOESI_CMP_directory-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -43,6 +43,7 @@ MessageBuffer * responseFromDir, network="To", virtual_network="2", vnet_type="response"; // Dir -> mod-L2 bank + MessageBuffer * responseFromMemory; { // STATES state_declaration(State, desc="Directory states", default="Directory_State_I") { @@ -223,8 +224,6 @@ return false; } - MessageBuffer responseFromMemory; - // ** OUT_PORTS ** out_port(forwardNetwork_out, RequestMsg, forwardFromDir); out_port(responseNetwork_out, ResponseMsg, responseFromDir); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_directory-dma.sm --- a/src/mem/protocol/MOESI_CMP_directory-dma.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm Sun Aug 02 19:13:01 2015 -0500 @@ -40,6 +40,8 @@ MessageBuffer * respToDir, network="To", virtual_network="2", vnet_type="dmaresponse"; + MessageBuffer * mandatoryQueue; + MessageBuffer * triggerQueue; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -69,8 +71,6 @@ bool isPresent(Addr); } - MessageBuffer mandatoryQueue; - MessageBuffer triggerQueue; TBETable TBEs, template="", constructor="m_number_of_TBEs"; State cur_state; diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_token-L1cache.sm --- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -61,7 +61,6 @@ MessageBuffer * requestFromL1Cache, network="To", virtual_network="1", vnet_type="request"; - // To this node's L1 cache FROM the network // a L2 bank -> this L1 @@ -73,6 +72,7 @@ MessageBuffer * requestToL1Cache, network="From", virtual_network="1", vnet_type="request"; + MessageBuffer * mandatoryQueue; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -196,8 +196,6 @@ TBETable L1_TBEs, template="", constructor="m_number_of_TBEs"; - MessageBuffer mandatoryQueue, abstract_chip_ptr="true"; - bool starving, default="false"; int l2_select_low_bit, default="RubySystem::getBlockSizeBits()"; diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_token-dir.sm --- a/src/mem/protocol/MOESI_CMP_token-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -62,6 +62,7 @@ MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", vnet_type="request"; + MessageBuffer * responseFromMemory; { // STATES state_declaration(State, desc="Directory states", default="Directory_State_O") { @@ -269,8 +270,6 @@ return num_functional_writes; } - MessageBuffer responseFromMemory; - // ** OUT_PORTS ** out_port(responseNetwork_out, ResponseMsg, responseFromDir); out_port(persistentNetwork_out, PersistentMsg, persistentFromDir); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_CMP_token-dma.sm --- a/src/mem/protocol/MOESI_CMP_token-dma.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_CMP_token-dma.sm Sun Aug 02 19:13:01 2015 -0500 @@ -37,6 +37,7 @@ MessageBuffer * reqToDirectory, network="To", virtual_network="0", vnet_type="request"; + MessageBuffer * mandatoryQueue; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -51,16 +52,15 @@ Ack, desc="DMA write to memory completed"; } - MessageBuffer mandatoryQueue; State cur_state; - Tick clockEdge(); State getState(Addr addr) { return cur_state; } + void setState(Addr addr, State state) { - cur_state := state; + cur_state := state; } AccessPermission getAccessPermission(Addr addr) { diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_hammer-cache.sm --- a/src/mem/protocol/MOESI_hammer-cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -56,6 +56,10 @@ vnet_type="forward"; MessageBuffer * responseToCache, network="From", virtual_network="4", vnet_type="response"; + + MessageBuffer * mandatoryQueue; + + MessageBuffer * triggerQueue; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -139,12 +143,7 @@ Block_Ack, desc="the directory is blocked and ready for the flush"; } - // TYPES - // STRUCTURE DEFINITIONS - - MessageBuffer mandatoryQueue; - // CacheEntry structure(Entry, desc="...", interface="AbstractCacheEntry") { State CacheState, desc="cache state"; @@ -321,10 +320,7 @@ return cache_entry.AtomicAccessed; } - MessageBuffer triggerQueue; - // ** OUT_PORTS ** - out_port(requestNetwork_out, RequestMsg, requestFromCache); out_port(responseNetwork_out, ResponseMsg, responseFromCache); out_port(unblockNetwork_out, ResponseMsg, unblockFromCache); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_hammer-dir.sm --- a/src/mem/protocol/MOESI_hammer-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -64,6 +64,9 @@ MessageBuffer * dmaRequestToDir, network="From", virtual_network="0", vnet_type="request"; + + MessageBuffer * triggerQueue; + MessageBuffer * responseFromMemory; { // STATES state_declaration(State, desc="Directory states", default="Directory_State_E") { @@ -301,9 +304,6 @@ } } - MessageBuffer triggerQueue; - MessageBuffer responseFromMemory; - // ** OUT_PORTS ** out_port(requestQueue_out, ResponseMsg, requestToDir); // For recycling requests out_port(forwardNetwork_out, RequestMsg, forwardFromDir); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/MOESI_hammer-dma.sm --- a/src/mem/protocol/MOESI_hammer-dma.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/MOESI_hammer-dma.sm Sun Aug 02 19:13:01 2015 -0500 @@ -35,6 +35,7 @@ vnet_type="response"; MessageBuffer * requestToDir, network="To", virtual_network="0", vnet_type="request"; + MessageBuffer * mandatoryQueue; { state_declaration(State, desc="DMA states", default="DMA_State_READY") { READY, AccessPermission:Invalid, desc="Ready to accept a new request"; @@ -49,7 +50,6 @@ Ack, desc="DMA write to memory completed"; } - MessageBuffer mandatoryQueue; State cur_state; Tick clockEdge(); diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/Network_test-cache.sm --- a/src/mem/protocol/Network_test-cache.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/Network_test-cache.sm Sun Aug 02 19:13:01 2015 -0500 @@ -42,6 +42,8 @@ vnet_type = "forward"; MessageBuffer * responseFromCache, network="To", virtual_network="2", vnet_type = "response"; + + MessageBuffer * mandatoryQueue; { // STATES state_declaration(State, desc="Cache states", default="L1Cache_State_I") { @@ -57,11 +59,8 @@ } // STRUCTURE DEFINITIONS - - MessageBuffer mandatoryQueue; DataBlock dummyData; - // CacheEntry structure(Entry, desc="...", interface="AbstractCacheEntry") { State CacheState, desc="cache state"; diff -r f1aee4086cf3 -r efd32f38e069 src/mem/protocol/Network_test-dir.sm --- a/src/mem/protocol/Network_test-dir.sm Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/protocol/Network_test-dir.sm Sun Aug 02 19:13:01 2015 -0500 @@ -68,7 +68,6 @@ } void setState(Addr addr, State state) { - } AccessPermission getAccessPermission(Addr addr) { diff -r f1aee4086cf3 -r efd32f38e069 src/mem/slicc/symbols/StateMachine.py --- a/src/mem/slicc/symbols/StateMachine.py Sun Aug 02 15:33:45 2015 -0500 +++ b/src/mem/slicc/symbols/StateMachine.py Sun Aug 02 19:13:01 2015 -0500 @@ -43,6 +43,7 @@ "Sequencer": "RubySequencer", "DirectoryMemory": "RubyDirectoryMemory", "MemoryControl": "MemoryControl", + "MessageBuffer": "MessageBuffer", "DMASequencer": "DMASequencer", "Prefetcher":"Prefetcher", "Cycles":"Cycles", @@ -234,11 +235,7 @@ if param.rvalue is not None: dflt_str = str(param.rvalue.inline()) + ', ' - if param.type_ast.type.c_ident == "MessageBuffer": - # The MessageBuffer MUST be instantiated in the protocol config - code('${{param.ident}} = Param.MessageBuffer("")') - - elif python_class_map.has_key(param.type_ast.type.c_ident): + if python_class_map.has_key(param.type_ast.type.c_ident): python_type = python_class_map[param.type_ast.type.c_ident] code('${{param.ident}} = Param.${{python_type}}(${dflt_str}"")') @@ -247,12 +244,6 @@ "type: '%s'. Please update the python_class_map " \ "in StateMachine.py", param.type_ast.type.c_ident) - # Also add any MessageBuffers declared internally to the controller - # Note: This includes mandatory and memory queues - for var in self.objects: - if var.type.c_ident == "MessageBuffer": - code('${{var.ident}} = Param.MessageBuffer("")') - code.dedent() code.write(path, '%s.py' % py_ident) @@ -303,8 +294,8 @@ static int getNumControllers(); void init(); - MessageBuffer* getMandatoryQueue() const; - MessageBuffer* getMemoryQueue() const; + MessageBuffer *getMandatoryQueue() const; + MessageBuffer *getMemoryQueue() const; void initNetQueues(); void printToStream(std::ostream& out) const; @@ -539,16 +530,6 @@ if re.compile("sequencer").search(param.ident): code('m_${{param.ident}}_ptr->setController(this);') - for var in self.objects: - # Some MessageBuffers (e.g. mandatory and memory queues) are - # instantiated internally to StateMachines but exposed to - # components outside SLICC, so make sure to set up this - # controller as their receivers - if var.type.c_ident == "MessageBuffer": - code(''' -m_${{var.ident}}_ptr = p->${{var.ident}}; -''') - code(''' for (int state = 0; state < ${ident}_State_NUM; state++) { @@ -628,14 +609,13 @@ code('(*$vid) = ${{var["default"]}};') else: # Normal Object - if var.type.c_ident != "MessageBuffer": - th = var.get("template", "") - expr = "%s = new %s%s" % (vid, vtype.c_ident, th) - args = "" - if "non_obj" not in vtype and not vtype.isEnumeration: - args = var.get("constructor", "") - code('$expr($args);') + th = var.get("template", "") + expr = "%s = new %s%s" % (vid, vtype.c_ident, th) + args = "" + if "non_obj" not in vtype and not vtype.isEnumeration: + args = var.get("constructor", "") + code('$expr($args);') code('assert($vid != NULL);') if "default" in var: