diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/cache/cache_impl.hh Thu Aug 06 22:40:58 2015 +0100 @@ -655,7 +655,7 @@ blk->status &= ~BlkHWPrefetched; // Don't notify on SWPrefetch - if (!pkt->cmd.isSWPrefetch()) + if (pkt->cmd != MemCmd::SoftPFReq) next_pf_time = prefetcher->notify(pkt); } @@ -697,7 +697,7 @@ // processing happens before any MSHR munging on the behalf of // this request because this new Request will be the one stored // into the MSHRs, not the original. - if (pkt->cmd.isSWPrefetch()) { + if (pkt->cmd == MemCmd::SoftPFReq) { assert(needsResponse); assert(pkt->req->hasPaddr()); assert(!pkt->req->isUncacheable()); @@ -784,7 +784,7 @@ // about the request if (prefetcher) { // Don't notify on SWPrefetch - if (!pkt->cmd.isSWPrefetch()) + if (pkt->cmd != MemCmd::SoftPFReq) next_pf_time = prefetcher->notify(pkt); } } @@ -834,7 +834,7 @@ if (prefetcher) { // Don't notify on SWPrefetch - if (!pkt->cmd.isSWPrefetch()) + if (pkt->cmd != MemCmd::SoftPFReq) next_pf_time = prefetcher->notify(pkt); } } @@ -1248,7 +1248,7 @@ completion_time = pkt->headerDelay; // Software prefetch handling for cache closest to core - if (tgt_pkt->cmd.isSWPrefetch()) { + if (tgt_pkt->cmd == MemCmd::SoftPFReq) { // a software prefetch would have already been ack'd immediately // with dummy data so the core would be able to retire it. // this request completes right here, so we deallocate it. diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/packet.hh --- a/src/mem/packet.hh Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/packet.hh Thu Aug 06 22:40:58 2015 +0100 @@ -144,13 +144,10 @@ IsRequest, //!< Issued by requester IsResponse, //!< Issue by responder NeedsResponse, //!< Requester needs response from target - IsSWPrefetch, - IsHWPrefetch, IsLlsc, //!< Alpha/MIPS LL or SC access HasData, //!< There is an associated payload IsError, //!< Error response IsPrint, //!< Print state matching address (for debugging) - IsFlush, //!< Flush the address from caches NUM_COMMAND_ATTRIBUTES }; @@ -200,13 +197,8 @@ */ bool hasData() const { return testCmdAttrib(HasData); } bool isLLSC() const { return testCmdAttrib(IsLlsc); } - bool isSWPrefetch() const { return testCmdAttrib(IsSWPrefetch); } - bool isHWPrefetch() const { return testCmdAttrib(IsHWPrefetch); } - bool isPrefetch() const { return testCmdAttrib(IsSWPrefetch) || - testCmdAttrib(IsHWPrefetch); } bool isError() const { return testCmdAttrib(IsError); } bool isPrint() const { return testCmdAttrib(IsPrint); } - bool isFlush() const { return testCmdAttrib(IsFlush); } const Command responseCommand() const @@ -487,7 +479,6 @@ bool isLLSC() const { return cmd.isLLSC(); } bool isError() const { return cmd.isError(); } bool isPrint() const { return cmd.isPrint(); } - bool isFlush() const { return cmd.isFlush(); } // Snoop flags void assertMemInhibit() diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/packet.cc --- a/src/mem/packet.cc Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/packet.cc Thu Aug 06 22:40:58 2015 +0100 @@ -90,16 +90,16 @@ /* CleanEvict */ { SET2(IsWrite, IsRequest), InvalidCmd, "CleanEvict" }, /* SoftPFReq */ - { SET4(IsRead, IsRequest, IsSWPrefetch, NeedsResponse), + { SET3(IsRead, IsRequest, NeedsResponse), SoftPFResp, "SoftPFReq" }, /* HardPFReq */ - { SET4(IsRead, IsRequest, IsHWPrefetch, NeedsResponse), + { SET3(IsRead, IsRequest, NeedsResponse), HardPFResp, "HardPFReq" }, /* SoftPFResp */ - { SET4(IsRead, IsResponse, IsSWPrefetch, HasData), + { SET3(IsRead, IsResponse, HasData), InvalidCmd, "SoftPFResp" }, /* HardPFResp */ - { SET4(IsRead, IsResponse, IsHWPrefetch, HasData), + { SET3(IsRead, IsResponse, HasData), InvalidCmd, "HardPFResp" }, /* WriteLineReq */ { SET5(IsWrite, NeedsExclusive, IsRequest, NeedsResponse, HasData), @@ -184,7 +184,7 @@ /* PrintReq */ { SET2(IsRequest, IsPrint), InvalidCmd, "PrintReq" }, /* Flush Request */ - { SET3(IsRequest, IsFlush, NeedsExclusive), InvalidCmd, "FlushReq" }, + { SET2(IsRequest, NeedsExclusive), InvalidCmd, "FlushReq" }, /* Invalidation Request */ { SET4(IsInvalidate, IsRequest, NeedsExclusive, NeedsResponse), InvalidateResp, "InvalidateReq" }, diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/ruby/system/DMASequencer.cc --- a/src/mem/ruby/system/DMASequencer.cc Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/ruby/system/DMASequencer.cc Thu Aug 06 22:40:58 2015 +0100 @@ -184,7 +184,7 @@ { bool needsResponse = pkt->needsResponse(); assert(!pkt->isLLSC()); - assert(!pkt->isFlush()); + assert(pkt->cmd != MemCmd::FlushReq); DPRINTF(RubyDma, "Hit callback needs response %d\n", needsResponse); diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/ruby/system/RubyPort.cc Thu Aug 06 22:40:58 2015 +0100 @@ -452,7 +452,7 @@ } // Flush requests don't access physical memory - if (pkt->isFlush()) { + if (pkt->cmd == MemCmd::FlushReq) { accessPhysMem = false; } diff -r 4c85cf876480 -r e6aa2b4cfbef src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Thu Aug 06 22:40:56 2015 +0100 +++ b/src/mem/ruby/system/Sequencer.cc Thu Aug 06 22:40:58 2015 +0100 @@ -527,7 +527,7 @@ if (RubySystem::getWarmupEnabled()) { data.setData(pkt->getConstPtr(), request_address.getOffset(), pkt->getSize()); - } else if (!pkt->isFlush()) { + } else if (pkt->cmd != MemCmd::FlushReq) { if ((type == RubyRequestType_LD) || (type == RubyRequestType_IFETCH) || (type == RubyRequestType_RMW_Read) || @@ -646,7 +646,7 @@ // Note: M5 packets do not differentiate ST from RMW_Write // primary_type = secondary_type = RubyRequestType_ST; - } else if (pkt->isFlush()) { + } else if (pkt->cmd == MemCmd::FlushReq) { primary_type = secondary_type = RubyRequestType_FLUSH; } else { panic("Unsupported ruby packet type\n"); @@ -682,7 +682,7 @@ // requests do not std::shared_ptr msg = std::make_shared(clockEdge(), pkt->getAddr(), - pkt->isFlush() ? + pkt->cmd == MemCmd::FlushReq ? nullptr : pkt->getPtr(), pkt->getSize(), pc, secondary_type, RubyAccessMode_Supervisor, pkt,