diff -r 3155a9ccb66b -r 32b13936bb3f src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh	Wed Nov 10 00:48:03 2010 -0600
+++ b/src/cpu/simple/timing.hh	Thu Nov 11 18:01:21 2010 -0600
@@ -140,7 +140,7 @@
       public:
 
         CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
-            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
+            : Port(_name, _cpu), cpu(_cpu), lat(_lat), retryEvent(this)
         { }
 
         bool snoopRangeSent;
@@ -161,12 +161,14 @@
         {
             PacketPtr pkt;
             TimingSimpleCPU *cpu;
+            CpuPort *port;
 
             TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
             const char *description() const { return "Timing CPU tick"; }
             void schedule(PacketPtr _pkt, Tick t);
         };
 
+        EventWrapper<Port, &Port::sendRetry> retryEvent;
     };
 
     class IcachePort : public CpuPort
diff -r 3155a9ccb66b -r 32b13936bb3f src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Wed Nov 10 00:48:03 2010 -0600
+++ b/src/cpu/simple/timing.cc	Thu Nov 11 18:01:21 2010 -0600
@@ -999,7 +999,16 @@
         if (next_tick == curTick) {
             cpu->completeDataAccess(pkt);
         } else {
-            tickEvent.schedule(pkt, next_tick);
+            if (!tickEvent.scheduled())
+                tickEvent.schedule(pkt, next_tick);
+            else {
+                // In the case of a split transaction and a cache that is
+                // faster than a CPU we could get two responses before
+                // next_tick expires
+                if (!retryEvent.scheduled())
+                    schedule(retryEvent, next_tick);
+                return false;
+            }
         }
 
         return true;