diff -r d96c9271bb59 -r 0a83a8d08c9e src/mem/ruby/slicc_interface/AbstractController.cc --- a/src/mem/ruby/slicc_interface/AbstractController.cc Fri Oct 16 08:09:18 2015 -0500 +++ b/src/mem/ruby/slicc_interface/AbstractController.cc Fri Oct 16 08:37:57 2015 -0500 @@ -191,6 +191,12 @@ m_block_map[addr] = port; } +bool +AbstractController::isBlocked(Addr addr) const +{ + return m_is_blocking && (m_block_map.find(addr) != m_block_map.end()); +} + void AbstractController::unblock(Addr addr) { diff -r d96c9271bb59 -r 0a83a8d08c9e src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Fri Oct 16 08:09:18 2015 -0500 +++ b/src/mem/ruby/system/Sequencer.cc Fri Oct 16 08:37:57 2015 -0500 @@ -172,6 +172,13 @@ } Addr line_addr = makeLineAddress(pkt->getAddr()); + + // Check if the line is blocked for a Locked_RMW + if (m_controller->isBlocked(line_addr) && + (request_type != RubyRequestType_Locked_RMW_Write)) { + return RequestStatus_Aliased; + } + // Create a default entry, mapping the address to NULL, the cast is // there to make gcc 4.4 happy RequestTable::value_type default_entry(line_addr, @@ -381,6 +388,9 @@ if(!m_usingNetworkTester) success = handleLlsc(address, request); + // Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the + // address variable here is assumed to be a line address, so when + // blocking buffers, must check line addresses. if (request->m_type == RubyRequestType_Locked_RMW_Read) { m_controller->blockOnQueue(address, m_mandatory_q_ptr); } else if (request->m_type == RubyRequestType_Locked_RMW_Write) { diff -r d96c9271bb59 -r 0a83a8d08c9e src/mem/ruby/slicc_interface/AbstractController.hh --- a/src/mem/ruby/slicc_interface/AbstractController.hh Fri Oct 16 08:09:18 2015 -0500 +++ b/src/mem/ruby/slicc_interface/AbstractController.hh Fri Oct 16 08:37:57 2015 -0500 @@ -72,6 +72,7 @@ // return instance name void blockOnQueue(Addr, MessageBuffer*); + bool isBlocked(Addr) const; void unblock(Addr); virtual MessageBuffer* getMandatoryQueue() const = 0;